1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Sricharan R <r.sricharan@ti.com> 6 * Nishant Kamat <nskamat@ti.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 #ifndef _MUX_DATA_DRA7XX_H_ 11 #define _MUX_DATA_DRA7XX_H_ 12 13 #include <asm/arch/mux_dra7xx.h> 14 15 const struct pad_conf_entry core_padconf_array_essential[] = { 16 {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ 17 {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ 18 {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ 19 {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ 20 {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ 21 {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ 22 {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ 23 {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ 24 #if defined(CONFIG_NOR) 25 /* NOR only pin-mux */ 26 {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */ 27 {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */ 28 {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */ 29 {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */ 30 {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */ 31 {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */ 32 {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */ 33 {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */ 34 {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */ 35 {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */ 36 {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */ 37 {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */ 38 {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */ 39 {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */ 40 {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */ 41 {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */ 42 {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */ 43 {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */ 44 {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */ 45 {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */ 46 {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */ 47 {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */ 48 {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */ 49 {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */ 50 {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */ 51 {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */ 52 {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */ 53 #else 54 /* eMMC pinmux */ 55 {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ 56 {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ 57 {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ 58 {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ 59 {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ 60 {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ 61 {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ 62 {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ 63 {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ 64 {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ 65 #endif 66 #if (CONFIG_CONS_INDEX == 1) 67 {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ 68 {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ 69 {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ 70 {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ 71 #elif (CONFIG_CONS_INDEX == 3) 72 {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */ 73 {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */ 74 #endif 75 {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ 76 {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ 77 {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ 78 {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ 79 {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) }, 80 {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) }, 81 {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) }, 82 {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) }, 83 {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) }, 84 {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) }, 85 {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) }, 86 {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) }, 87 {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) }, 88 {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) }, 89 {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) }, 90 {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) }, 91 {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) }, 92 {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) }, 93 {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) }, 94 {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) }, 95 {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) }, 96 {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) }, 97 {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)}, 98 {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)}, 99 {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)}, 100 {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)}, 101 {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)}, 102 {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)}, 103 #if defined(CONFIG_NAND) || defined(CONFIG_NOR) 104 /* NAND / NOR pin-mux */ 105 {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ 106 {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */ 107 {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */ 108 {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */ 109 {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */ 110 {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */ 111 {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */ 112 {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */ 113 {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */ 114 {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */ 115 {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */ 116 {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */ 117 {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */ 118 {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */ 119 {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */ 120 {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */ 121 {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */ 122 {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */ 123 {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */ 124 {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */ 125 {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */ 126 {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */ 127 /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */ 128 #else 129 /* QSPI pin-mux */ 130 {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ 131 {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ 132 {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ 133 {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ 134 {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ 135 {GPMC_A18, (M1)}, /* QSPI1_SCLK */ 136 {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */ 137 {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ 138 {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ 139 {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ 140 #endif /* CONFIG_NAND || CONFIG_NOR */ 141 {USB2_DRVVBUS, (M0 | IEN | FSC) }, 142 {SPI1_CS1, (PEN | IDIS | M14) }, 143 }; 144 145 const struct pad_conf_entry early_padconf[] = { 146 #if (CONFIG_CONS_INDEX == 1) 147 {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ 148 {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */ 149 #elif (CONFIG_CONS_INDEX == 3) 150 {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */ 151 {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */ 152 #endif 153 {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */ 154 {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */ 155 }; 156 157 #ifdef CONFIG_IODELAY_RECALIBRATION 158 const struct iodelay_cfg_entry iodelay_cfg_array[] = { 159 {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */ 160 {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */ 161 {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */ 162 {0x714, 196, 1522}, /* RGMMI0_RXD1_IN */ 163 {0x720, 40, 1860}, /* RGMMI0_RXD2_IN */ 164 {0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */ 165 {0x740, 0, 220}, /* RGMMI0_TXC_OUT */ 166 {0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */ 167 {0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */ 168 {0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */ 169 {0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */ 170 {0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */ 171 /* These values are for using RGMII1 configuration on VIN2a_x pins. */ 172 {0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */ 173 {0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */ 174 {0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */ 175 {0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */ 176 {0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */ 177 {0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */ 178 {0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */ 179 {0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */ 180 {0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */ 181 {0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */ 182 {0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */ 183 {0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */ 184 }; 185 #endif 186 187 const struct pad_conf_entry dra74x_core_padconf_array[] = { 188 {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ 189 {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ 190 {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ 191 {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ 192 {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ 193 {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ 194 {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ 195 {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ 196 {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ 197 {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ 198 {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ 199 {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ 200 {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ 201 {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ 202 {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ 203 {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ 204 {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */ 205 {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */ 206 {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */ 207 {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */ 208 {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */ 209 {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */ 210 {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */ 211 {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */ 212 {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */ 213 {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */ 214 {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */ 215 {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */ 216 {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */ 217 {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */ 218 {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */ 219 {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */ 220 {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */ 221 {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */ 222 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ 223 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ 224 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ 225 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ 226 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ 227 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ 228 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ 229 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ 230 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ 231 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ 232 {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */ 233 {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */ 234 {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */ 235 {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */ 236 {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */ 237 {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */ 238 {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */ 239 {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */ 240 {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */ 241 {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */ 242 {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */ 243 {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */ 244 {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */ 245 {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */ 246 {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */ 247 {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */ 248 {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */ 249 {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */ 250 {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */ 251 {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */ 252 {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */ 253 {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */ 254 {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */ 255 {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */ 256 {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */ 257 {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */ 258 {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */ 259 {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */ 260 {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */ 261 {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */ 262 {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */ 263 {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ 264 {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ 265 {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ 266 {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ 267 {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ 268 {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ 269 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ 270 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ 271 {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ 272 {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ 273 {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ 274 {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ 275 {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ 276 {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ 277 {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */ 278 {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ 279 {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ 280 {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ 281 {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ 282 {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ 283 {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ 284 {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ 285 {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ 286 {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ 287 {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ 288 {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ 289 {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ 290 {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ 291 {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ 292 {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ 293 {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ 294 {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ 295 {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ 296 {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ 297 {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ 298 {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ 299 {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ 300 {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ 301 {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ 302 {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ 303 {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ 304 {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ 305 {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ 306 {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ 307 {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ 308 {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ 309 {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ 310 {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ 311 {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ 312 {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ 313 {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ 314 {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ 315 {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ 316 {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ 317 {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ 318 {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ 319 {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */ 320 {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */ 321 {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ 322 {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */ 323 {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */ 324 {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */ 325 {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */ 326 {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */ 327 {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ 328 {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ 329 {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ 330 {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ 331 {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ 332 {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ 333 {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ 334 {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ 335 {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ 336 {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ 337 {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ 338 {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ 339 {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */ 340 {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */ 341 {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */ 342 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ 343 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ 344 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ 345 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ 346 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ 347 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ 348 {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */ 349 {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ 350 {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ 351 {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ 352 {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ 353 {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ 354 {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ 355 {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ 356 {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ 357 {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ 358 {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ 359 {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ 360 {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ 361 {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */ 362 {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ 363 {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */ 364 {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ 365 {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ 366 {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */ 367 {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */ 368 {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */ 369 {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */ 370 {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */ 371 {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */ 372 {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ 373 {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ 374 {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */ 375 {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ 376 }; 377 378 #ifdef CONFIG_IODELAY_RECALIBRATION 379 const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = { 380 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ 381 {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ 382 {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ 383 {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ 384 {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ 385 {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ 386 {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */ 387 {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */ 388 {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */ 389 {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */ 390 {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */ 391 {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */ 392 {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */ 393 {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */ 394 {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */ 395 {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */ 396 {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */ 397 {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */ 398 {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */ 399 {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */ 400 {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */ 401 {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */ 402 {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */ 403 {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */ 404 {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */ 405 {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */ 406 {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */ 407 {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */ 408 {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */ 409 {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */ 410 {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */ 411 {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */ 412 {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */ 413 {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */ 414 {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */ 415 {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */ 416 {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */ 417 {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */ 418 {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */ 419 {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */ 420 {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */ 421 {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */ 422 {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */ 423 {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */ 424 {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */ 425 {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */ 426 {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */ 427 {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ 428 {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ 429 {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ 430 {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ 431 {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ 432 {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ 433 }; 434 435 const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = { 436 {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */ 437 {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */ 438 {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */ 439 {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */ 440 {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */ 441 {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */ 442 {0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */ 443 {0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */ 444 {0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */ 445 {0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */ 446 {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */ 447 {0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */ 448 {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */ 449 {0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */ 450 {0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */ 451 {0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */ 452 {0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */ 453 {0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */ 454 {0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */ 455 {0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */ 456 {0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */ 457 {0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */ 458 {0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */ 459 {0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */ 460 {0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */ 461 {0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */ 462 {0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */ 463 {0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */ 464 {0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */ 465 {0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */ 466 {0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */ 467 {0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */ 468 {0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */ 469 {0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */ 470 {0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */ 471 {0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */ 472 {0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */ 473 {0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */ 474 {0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */ 475 {0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */ 476 {0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */ 477 {0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */ 478 {0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */ 479 {0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */ 480 {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */ 481 {0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */ 482 {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ 483 {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */ 484 {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */ 485 {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */ 486 {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */ 487 {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */ 488 {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */ 489 }; 490 #endif 491 492 #endif /* _MUX_DATA_DRA7XX_H_ */ 493