1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Sricharan R <r.sricharan@ti.com> 6 * Nishant Kamat <nskamat@ti.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 #ifndef _MUX_DATA_DRA7XX_H_ 11 #define _MUX_DATA_DRA7XX_H_ 12 13 #include <asm/arch/mux_dra7xx.h> 14 15 const struct pad_conf_entry core_padconf_array_essential[] = { 16 {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ 17 {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ 18 {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ 19 {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ 20 {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ 21 {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ 22 {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ 23 {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ 24 {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ 25 {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ 26 {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ 27 {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ 28 {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ 29 {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ 30 {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ 31 {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ 32 {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ 33 {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ 34 {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ 35 {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ 36 {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ 37 {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ 38 {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ 39 {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ 40 {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ 41 {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ 42 {RGMII0_TXC, (M0) }, 43 {RGMII0_TXCTL, (M0) }, 44 {RGMII0_TXD3, (M0) }, 45 {RGMII0_TXD2, (M0) }, 46 {RGMII0_TXD1, (M0) }, 47 {RGMII0_TXD0, (M0) }, 48 {RGMII0_RXC, (IEN | M0) }, 49 {RGMII0_RXCTL, (IEN | M0) }, 50 {RGMII0_RXD3, (IEN | M0) }, 51 {RGMII0_RXD2, (IEN | M0) }, 52 {RGMII0_RXD1, (IEN | M0) }, 53 {RGMII0_RXD0, (IEN | M0) }, 54 {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ 55 {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ 56 {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ 57 {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */ 58 {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */ 59 {GPMC_A18, (M1)}, /* QSPI1_SCLK */ 60 {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */ 61 {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ 62 {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ 63 {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ 64 {USB2_DRVVBUS, (M0 | IEN | FSC) }, 65 }; 66 #endif /* _MUX_DATA_DRA7XX_H_ */ 67