1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/gpio.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/mmc_host_def.h> 20 #include <asm/arch/sata.h> 21 #include <environment.h> 22 23 #include "mux_data.h" 24 25 #ifdef CONFIG_DRIVER_TI_CPSW 26 #include <cpsw.h> 27 #endif 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 /* GPIO 7_11 */ 32 #define GPIO_DDR_VTT_EN 203 33 34 const struct omap_sysinfo sysinfo = { 35 "Board: DRA7xx\n" 36 }; 37 38 /* 39 * Adjust I/O delays on the Tx control and data lines of each MAC port. This 40 * is a workaround in order to work properly with the DP83865 PHYs on the EVM. 41 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we 42 * essentially need to counteract the DRA7xx internal delay, and we do this 43 * by delaying the control and data lines. If not using this PHY, you probably 44 * don't need to do this stuff! 45 */ 46 static void dra7xx_adj_io_delay(const struct io_delay *io_dly) 47 { 48 int i = 0; 49 u32 reg_val; 50 u32 delta; 51 u32 coarse; 52 u32 fine; 53 54 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); 55 56 while(io_dly[i].addr) { 57 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, 58 io_dly[i].addr); 59 delta = io_dly[i].dly; 60 reg_val = readl(io_dly[i].addr) & 0x3ff; 61 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); 62 coarse = (coarse > 0x1F) ? (0x1F) : (coarse); 63 fine = (reg_val & 0x1F) + (delta & 0x1F); 64 fine = (fine > 0x1F) ? (0x1F) : (fine); 65 reg_val = CFG_IO_DELAY_ACCESS_PATTERN | 66 CFG_IO_DELAY_LOCK_MASK | 67 ((coarse << 5) | (fine)); 68 writel(reg_val, io_dly[i].addr); 69 i++; 70 } 71 72 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); 73 } 74 75 /** 76 * @brief board_init 77 * 78 * @return 0 79 */ 80 int board_init(void) 81 { 82 gpmc_init(); 83 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 84 85 return 0; 86 } 87 88 int board_late_init(void) 89 { 90 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 91 if (omap_revision() == DRA722_ES1_0) 92 setenv("board_name", "dra72x"); 93 else 94 setenv("board_name", "dra7xx"); 95 #endif 96 return 0; 97 } 98 99 static void do_set_mux32(u32 base, 100 struct pad_conf_entry const *array, int size) 101 { 102 int i; 103 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 104 105 for (i = 0; i < size; i++, pad++) 106 writel(pad->val, base + pad->offset); 107 } 108 109 void set_muxconf_regs_essential(void) 110 { 111 do_set_mux32((*ctrl)->control_padconf_core_base, 112 core_padconf_array_essential, 113 sizeof(core_padconf_array_essential) / 114 sizeof(struct pad_conf_entry)); 115 } 116 117 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 118 int board_mmc_init(bd_t *bis) 119 { 120 omap_mmc_init(0, 0, 0, -1, -1); 121 omap_mmc_init(1, 0, 0, -1, -1); 122 return 0; 123 } 124 #endif 125 126 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 127 int spl_start_uboot(void) 128 { 129 /* break into full u-boot on 'c' */ 130 if (serial_tstc() && serial_getc() == 'c') 131 return 1; 132 133 #ifdef CONFIG_SPL_ENV_SUPPORT 134 env_init(); 135 env_relocate_spec(); 136 if (getenv_yesno("boot_os") != 1) 137 return 1; 138 #endif 139 140 return 0; 141 } 142 #endif 143 144 #ifdef CONFIG_DRIVER_TI_CPSW 145 146 /* Delay value to add to calibrated value */ 147 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 148 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 149 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 150 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 151 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 152 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 153 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 154 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 155 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 156 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 157 158 extern u32 *const omap_si_rev; 159 160 static void cpsw_control(int enabled) 161 { 162 /* VTP can be added here */ 163 164 return; 165 } 166 167 static struct cpsw_slave_data cpsw_slaves[] = { 168 { 169 .slave_reg_ofs = 0x208, 170 .sliver_reg_ofs = 0xd80, 171 .phy_addr = 2, 172 }, 173 { 174 .slave_reg_ofs = 0x308, 175 .sliver_reg_ofs = 0xdc0, 176 .phy_addr = 3, 177 }, 178 }; 179 180 static struct cpsw_platform_data cpsw_data = { 181 .mdio_base = CPSW_MDIO_BASE, 182 .cpsw_base = CPSW_BASE, 183 .mdio_div = 0xff, 184 .channels = 8, 185 .cpdma_reg_ofs = 0x800, 186 .slaves = 2, 187 .slave_data = cpsw_slaves, 188 .ale_reg_ofs = 0xd00, 189 .ale_entries = 1024, 190 .host_port_reg_ofs = 0x108, 191 .hw_stats_reg_ofs = 0x900, 192 .bd_ram_ofs = 0x2000, 193 .mac_control = (1 << 5), 194 .control = cpsw_control, 195 .host_port_num = 0, 196 .version = CPSW_CTRL_VERSION_2, 197 }; 198 199 int board_eth_init(bd_t *bis) 200 { 201 int ret; 202 uint8_t mac_addr[6]; 203 uint32_t mac_hi, mac_lo; 204 uint32_t ctrl_val; 205 const struct io_delay io_dly[] = { 206 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, 207 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, 208 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, 209 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, 210 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, 211 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, 212 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, 213 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, 214 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, 215 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, 216 {0} 217 }; 218 219 /* Adjust IO delay for RGMII tx path */ 220 dra7xx_adj_io_delay(io_dly); 221 222 /* try reading mac address from efuse */ 223 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 224 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 225 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 226 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 227 mac_addr[2] = mac_hi & 0xFF; 228 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 229 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 230 mac_addr[5] = mac_lo & 0xFF; 231 232 if (!getenv("ethaddr")) { 233 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 234 235 if (is_valid_ether_addr(mac_addr)) 236 eth_setenv_enetaddr("ethaddr", mac_addr); 237 } 238 239 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 240 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 241 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 242 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 243 mac_addr[2] = mac_hi & 0xFF; 244 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 245 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 246 mac_addr[5] = mac_lo & 0xFF; 247 248 if (!getenv("eth1addr")) { 249 if (is_valid_ether_addr(mac_addr)) 250 eth_setenv_enetaddr("eth1addr", mac_addr); 251 } 252 253 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 254 ctrl_val |= 0x22; 255 writel(ctrl_val, (*ctrl)->control_core_control_io1); 256 257 if (*omap_si_rev == DRA722_ES1_0) 258 cpsw_data.active_slave = 1; 259 260 ret = cpsw_register(&cpsw_data); 261 if (ret < 0) 262 printf("Error %d registering CPSW switch\n", ret); 263 264 return ret; 265 } 266 #endif 267 268 #ifdef CONFIG_BOARD_EARLY_INIT_F 269 /* VTT regulator enable */ 270 static inline void vtt_regulator_enable(void) 271 { 272 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 273 return; 274 275 /* Do not enable VTT for DRA722 */ 276 if (omap_revision() == DRA722_ES1_0) 277 return; 278 279 /* 280 * EVM Rev G and later use gpio7_11 for DDR3 termination. 281 * This is safe enough to do on older revs. 282 */ 283 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 284 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 285 } 286 287 int board_early_init_f(void) 288 { 289 vtt_regulator_enable(); 290 return 0; 291 } 292 #endif 293