1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <asm/gpio.h> 17 #include <usb.h> 18 #include <linux/usb/gadget.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/dra7xx_iodelay.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/sata.h> 24 #include <environment.h> 25 #include <dwc3-uboot.h> 26 #include <dwc3-omap-uboot.h> 27 #include <ti-usb-phy-uboot.h> 28 29 #include "mux_data.h" 30 31 #ifdef CONFIG_DRIVER_TI_CPSW 32 #include <cpsw.h> 33 #endif 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* GPIO 7_11 */ 38 #define GPIO_DDR_VTT_EN 203 39 40 const struct omap_sysinfo sysinfo = { 41 "Board: DRA7xx\n" 42 }; 43 44 /** 45 * @brief board_init 46 * 47 * @return 0 48 */ 49 int board_init(void) 50 { 51 gpmc_init(); 52 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 53 54 return 0; 55 } 56 57 int board_late_init(void) 58 { 59 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 60 u32 id[4]; 61 62 if (omap_revision() == DRA722_ES1_0) 63 setenv("board_name", "dra72x"); 64 else 65 setenv("board_name", "dra7xx"); 66 67 id[0] = readl((*ctrl)->control_std_fuse_die_id_0); 68 id[1] = readl((*ctrl)->control_std_fuse_die_id_1); 69 usb_set_serial_num_from_die_id(id); 70 #endif 71 return 0; 72 } 73 74 void set_muxconf_regs_essential(void) 75 { 76 do_set_mux32((*ctrl)->control_padconf_core_base, 77 early_padconf, ARRAY_SIZE(early_padconf)); 78 } 79 80 #ifdef CONFIG_IODELAY_RECALIBRATION 81 void recalibrate_iodelay(void) 82 { 83 struct pad_conf_entry const *pads; 84 struct iodelay_cfg_entry const *iodelay; 85 int npads, niodelays; 86 87 switch (omap_revision()) { 88 case DRA722_ES1_0: 89 pads = core_padconf_array_essential; 90 npads = ARRAY_SIZE(core_padconf_array_essential); 91 iodelay = iodelay_cfg_array; 92 niodelays = ARRAY_SIZE(iodelay_cfg_array); 93 break; 94 case DRA752_ES1_0: 95 case DRA752_ES1_1: 96 pads = dra74x_core_padconf_array; 97 npads = ARRAY_SIZE(dra74x_core_padconf_array); 98 iodelay = dra742_es1_1_iodelay_cfg_array; 99 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); 100 break; 101 default: 102 case DRA752_ES2_0: 103 pads = dra74x_core_padconf_array; 104 npads = ARRAY_SIZE(dra74x_core_padconf_array); 105 iodelay = dra742_es2_0_iodelay_cfg_array; 106 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); 107 /* Setup port1 and port2 for rgmii with 'no-id' mode */ 108 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | 109 RGMII1_ID_MODE_N_MASK); 110 break; 111 } 112 __recalibrate_iodelay(pads, npads, iodelay, niodelays); 113 } 114 #endif 115 116 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 117 int board_mmc_init(bd_t *bis) 118 { 119 omap_mmc_init(0, 0, 0, -1, -1); 120 omap_mmc_init(1, 0, 0, -1, -1); 121 return 0; 122 } 123 #endif 124 125 #ifdef CONFIG_USB_DWC3 126 static struct dwc3_device usb_otg_ss1 = { 127 .maximum_speed = USB_SPEED_SUPER, 128 .base = DRA7_USB_OTG_SS1_BASE, 129 .tx_fifo_resize = false, 130 .index = 0, 131 }; 132 133 static struct dwc3_omap_device usb_otg_ss1_glue = { 134 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 135 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 136 .index = 0, 137 }; 138 139 static struct ti_usb_phy_device usb_phy1_device = { 140 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 141 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 142 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 143 .index = 0, 144 }; 145 146 static struct dwc3_device usb_otg_ss2 = { 147 .maximum_speed = USB_SPEED_SUPER, 148 .base = DRA7_USB_OTG_SS2_BASE, 149 .tx_fifo_resize = false, 150 .index = 1, 151 }; 152 153 static struct dwc3_omap_device usb_otg_ss2_glue = { 154 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 155 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 156 .index = 1, 157 }; 158 159 static struct ti_usb_phy_device usb_phy2_device = { 160 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 161 .index = 1, 162 }; 163 164 int board_usb_init(int index, enum usb_init_type init) 165 { 166 enable_usb_clocks(index); 167 switch (index) { 168 case 0: 169 if (init == USB_INIT_DEVICE) { 170 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 171 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 172 } else { 173 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 174 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 175 } 176 177 ti_usb_phy_uboot_init(&usb_phy1_device); 178 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 179 dwc3_uboot_init(&usb_otg_ss1); 180 break; 181 case 1: 182 if (init == USB_INIT_DEVICE) { 183 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 184 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 185 } else { 186 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; 187 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 188 } 189 190 ti_usb_phy_uboot_init(&usb_phy2_device); 191 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 192 dwc3_uboot_init(&usb_otg_ss2); 193 break; 194 default: 195 printf("Invalid Controller Index\n"); 196 } 197 198 return 0; 199 } 200 201 int board_usb_cleanup(int index, enum usb_init_type init) 202 { 203 switch (index) { 204 case 0: 205 case 1: 206 ti_usb_phy_uboot_exit(index); 207 dwc3_uboot_exit(index); 208 dwc3_omap_uboot_exit(index); 209 break; 210 default: 211 printf("Invalid Controller Index\n"); 212 } 213 disable_usb_clocks(index); 214 return 0; 215 } 216 217 int usb_gadget_handle_interrupts(int index) 218 { 219 u32 status; 220 221 status = dwc3_omap_uboot_interrupt_status(index); 222 if (status) 223 dwc3_uboot_handle_interrupt(index); 224 225 return 0; 226 } 227 #endif 228 229 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 230 int spl_start_uboot(void) 231 { 232 /* break into full u-boot on 'c' */ 233 if (serial_tstc() && serial_getc() == 'c') 234 return 1; 235 236 #ifdef CONFIG_SPL_ENV_SUPPORT 237 env_init(); 238 env_relocate_spec(); 239 if (getenv_yesno("boot_os") != 1) 240 return 1; 241 #endif 242 243 return 0; 244 } 245 #endif 246 247 #ifdef CONFIG_DRIVER_TI_CPSW 248 extern u32 *const omap_si_rev; 249 250 static void cpsw_control(int enabled) 251 { 252 /* VTP can be added here */ 253 254 return; 255 } 256 257 static struct cpsw_slave_data cpsw_slaves[] = { 258 { 259 .slave_reg_ofs = 0x208, 260 .sliver_reg_ofs = 0xd80, 261 .phy_addr = 2, 262 }, 263 { 264 .slave_reg_ofs = 0x308, 265 .sliver_reg_ofs = 0xdc0, 266 .phy_addr = 3, 267 }, 268 }; 269 270 static struct cpsw_platform_data cpsw_data = { 271 .mdio_base = CPSW_MDIO_BASE, 272 .cpsw_base = CPSW_BASE, 273 .mdio_div = 0xff, 274 .channels = 8, 275 .cpdma_reg_ofs = 0x800, 276 .slaves = 2, 277 .slave_data = cpsw_slaves, 278 .ale_reg_ofs = 0xd00, 279 .ale_entries = 1024, 280 .host_port_reg_ofs = 0x108, 281 .hw_stats_reg_ofs = 0x900, 282 .bd_ram_ofs = 0x2000, 283 .mac_control = (1 << 5), 284 .control = cpsw_control, 285 .host_port_num = 0, 286 .version = CPSW_CTRL_VERSION_2, 287 }; 288 289 int board_eth_init(bd_t *bis) 290 { 291 int ret; 292 uint8_t mac_addr[6]; 293 uint32_t mac_hi, mac_lo; 294 uint32_t ctrl_val; 295 296 /* try reading mac address from efuse */ 297 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 298 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 299 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 300 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 301 mac_addr[2] = mac_hi & 0xFF; 302 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 303 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 304 mac_addr[5] = mac_lo & 0xFF; 305 306 if (!getenv("ethaddr")) { 307 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 308 309 if (is_valid_ethaddr(mac_addr)) 310 eth_setenv_enetaddr("ethaddr", mac_addr); 311 } 312 313 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 314 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 315 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 316 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 317 mac_addr[2] = mac_hi & 0xFF; 318 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 319 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 320 mac_addr[5] = mac_lo & 0xFF; 321 322 if (!getenv("eth1addr")) { 323 if (is_valid_ethaddr(mac_addr)) 324 eth_setenv_enetaddr("eth1addr", mac_addr); 325 } 326 327 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 328 ctrl_val |= 0x22; 329 writel(ctrl_val, (*ctrl)->control_core_control_io1); 330 331 if (*omap_si_rev == DRA722_ES1_0) 332 cpsw_data.active_slave = 1; 333 334 ret = cpsw_register(&cpsw_data); 335 if (ret < 0) 336 printf("Error %d registering CPSW switch\n", ret); 337 338 return ret; 339 } 340 #endif 341 342 #ifdef CONFIG_BOARD_EARLY_INIT_F 343 /* VTT regulator enable */ 344 static inline void vtt_regulator_enable(void) 345 { 346 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 347 return; 348 349 /* Do not enable VTT for DRA722 */ 350 if (omap_revision() == DRA722_ES1_0) 351 return; 352 353 /* 354 * EVM Rev G and later use gpio7_11 for DDR3 termination. 355 * This is safe enough to do on older revs. 356 */ 357 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 358 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 359 } 360 361 int board_early_init_f(void) 362 { 363 vtt_regulator_enable(); 364 return 0; 365 } 366 #endif 367