1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <asm/gpio.h> 17 #include <usb.h> 18 #include <linux/usb/gadget.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/sys_proto.h> 21 #include <asm/arch/mmc_host_def.h> 22 #include <asm/arch/sata.h> 23 #include <environment.h> 24 #include <dwc3-uboot.h> 25 #include <dwc3-omap-uboot.h> 26 #include <ti-usb-phy-uboot.h> 27 28 #include "mux_data.h" 29 30 #ifdef CONFIG_DRIVER_TI_CPSW 31 #include <cpsw.h> 32 #endif 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* GPIO 7_11 */ 37 #define GPIO_DDR_VTT_EN 203 38 39 const struct omap_sysinfo sysinfo = { 40 "Board: DRA7xx\n" 41 }; 42 43 /* 44 * Adjust I/O delays on the Tx control and data lines of each MAC port. This 45 * is a workaround in order to work properly with the DP83865 PHYs on the EVM. 46 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we 47 * essentially need to counteract the DRA7xx internal delay, and we do this 48 * by delaying the control and data lines. If not using this PHY, you probably 49 * don't need to do this stuff! 50 */ 51 static void dra7xx_adj_io_delay(const struct io_delay *io_dly) 52 { 53 int i = 0; 54 u32 reg_val; 55 u32 delta; 56 u32 coarse; 57 u32 fine; 58 59 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); 60 61 while(io_dly[i].addr) { 62 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, 63 io_dly[i].addr); 64 delta = io_dly[i].dly; 65 reg_val = readl(io_dly[i].addr) & 0x3ff; 66 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); 67 coarse = (coarse > 0x1F) ? (0x1F) : (coarse); 68 fine = (reg_val & 0x1F) + (delta & 0x1F); 69 fine = (fine > 0x1F) ? (0x1F) : (fine); 70 reg_val = CFG_IO_DELAY_ACCESS_PATTERN | 71 CFG_IO_DELAY_LOCK_MASK | 72 ((coarse << 5) | (fine)); 73 writel(reg_val, io_dly[i].addr); 74 i++; 75 } 76 77 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); 78 } 79 80 /** 81 * @brief board_init 82 * 83 * @return 0 84 */ 85 int board_init(void) 86 { 87 gpmc_init(); 88 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 89 90 return 0; 91 } 92 93 int board_late_init(void) 94 { 95 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 96 if (omap_revision() == DRA722_ES1_0) 97 setenv("board_name", "dra72x"); 98 else 99 setenv("board_name", "dra7xx"); 100 #endif 101 return 0; 102 } 103 104 static void do_set_mux32(u32 base, 105 struct pad_conf_entry const *array, int size) 106 { 107 int i; 108 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 109 110 for (i = 0; i < size; i++, pad++) 111 writel(pad->val, base + pad->offset); 112 } 113 114 void set_muxconf_regs_essential(void) 115 { 116 do_set_mux32((*ctrl)->control_padconf_core_base, 117 core_padconf_array_essential, 118 sizeof(core_padconf_array_essential) / 119 sizeof(struct pad_conf_entry)); 120 } 121 122 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 123 int board_mmc_init(bd_t *bis) 124 { 125 omap_mmc_init(0, 0, 0, -1, -1); 126 omap_mmc_init(1, 0, 0, -1, -1); 127 return 0; 128 } 129 #endif 130 131 #ifdef CONFIG_USB_DWC3 132 static struct dwc3_device usb_otg_ss1 = { 133 .maximum_speed = USB_SPEED_SUPER, 134 .base = DRA7_USB_OTG_SS1_BASE, 135 .tx_fifo_resize = false, 136 .index = 0, 137 }; 138 139 static struct dwc3_omap_device usb_otg_ss1_glue = { 140 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 141 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 142 .vbus_id_status = OMAP_DWC3_VBUS_VALID, 143 .index = 0, 144 }; 145 146 static struct ti_usb_phy_device usb_phy1_device = { 147 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 148 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 149 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 150 .index = 0, 151 }; 152 153 static struct dwc3_device usb_otg_ss2 = { 154 .maximum_speed = USB_SPEED_SUPER, 155 .base = DRA7_USB_OTG_SS2_BASE, 156 .tx_fifo_resize = false, 157 .index = 1, 158 }; 159 160 static struct dwc3_omap_device usb_otg_ss2_glue = { 161 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 162 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 163 .vbus_id_status = OMAP_DWC3_VBUS_VALID, 164 .index = 1, 165 }; 166 167 static struct ti_usb_phy_device usb_phy2_device = { 168 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 169 .index = 1, 170 }; 171 172 int board_usb_init(int index, enum usb_init_type init) 173 { 174 switch (index) { 175 case 0: 176 if (init == USB_INIT_DEVICE) { 177 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 178 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 179 } else { 180 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 181 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 182 } 183 184 ti_usb_phy_uboot_init(&usb_phy1_device); 185 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 186 dwc3_uboot_init(&usb_otg_ss1); 187 break; 188 case 1: 189 if (init == USB_INIT_DEVICE) { 190 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 191 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 192 } else { 193 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; 194 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 195 } 196 197 ti_usb_phy_uboot_init(&usb_phy2_device); 198 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 199 dwc3_uboot_init(&usb_otg_ss2); 200 break; 201 default: 202 printf("Invalid Controller Index\n"); 203 } 204 205 return 0; 206 } 207 208 int board_usb_cleanup(int index, enum usb_init_type init) 209 { 210 switch (index) { 211 case 0: 212 case 1: 213 ti_usb_phy_uboot_exit(index); 214 dwc3_uboot_exit(index); 215 dwc3_omap_uboot_exit(index); 216 break; 217 default: 218 printf("Invalid Controller Index\n"); 219 } 220 return 0; 221 } 222 223 int usb_gadget_handle_interrupts(int index) 224 { 225 u32 status; 226 227 status = dwc3_omap_uboot_interrupt_status(index); 228 if (status) 229 dwc3_uboot_handle_interrupt(index); 230 231 return 0; 232 } 233 #endif 234 235 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 236 int spl_start_uboot(void) 237 { 238 /* break into full u-boot on 'c' */ 239 if (serial_tstc() && serial_getc() == 'c') 240 return 1; 241 242 #ifdef CONFIG_SPL_ENV_SUPPORT 243 env_init(); 244 env_relocate_spec(); 245 if (getenv_yesno("boot_os") != 1) 246 return 1; 247 #endif 248 249 return 0; 250 } 251 #endif 252 253 #ifdef CONFIG_DRIVER_TI_CPSW 254 255 /* Delay value to add to calibrated value */ 256 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 257 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 258 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 259 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 260 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 261 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 262 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 263 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 264 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 265 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 266 267 extern u32 *const omap_si_rev; 268 269 static void cpsw_control(int enabled) 270 { 271 /* VTP can be added here */ 272 273 return; 274 } 275 276 static struct cpsw_slave_data cpsw_slaves[] = { 277 { 278 .slave_reg_ofs = 0x208, 279 .sliver_reg_ofs = 0xd80, 280 .phy_addr = 2, 281 }, 282 { 283 .slave_reg_ofs = 0x308, 284 .sliver_reg_ofs = 0xdc0, 285 .phy_addr = 3, 286 }, 287 }; 288 289 static struct cpsw_platform_data cpsw_data = { 290 .mdio_base = CPSW_MDIO_BASE, 291 .cpsw_base = CPSW_BASE, 292 .mdio_div = 0xff, 293 .channels = 8, 294 .cpdma_reg_ofs = 0x800, 295 .slaves = 2, 296 .slave_data = cpsw_slaves, 297 .ale_reg_ofs = 0xd00, 298 .ale_entries = 1024, 299 .host_port_reg_ofs = 0x108, 300 .hw_stats_reg_ofs = 0x900, 301 .bd_ram_ofs = 0x2000, 302 .mac_control = (1 << 5), 303 .control = cpsw_control, 304 .host_port_num = 0, 305 .version = CPSW_CTRL_VERSION_2, 306 }; 307 308 int board_eth_init(bd_t *bis) 309 { 310 int ret; 311 uint8_t mac_addr[6]; 312 uint32_t mac_hi, mac_lo; 313 uint32_t ctrl_val; 314 const struct io_delay io_dly[] = { 315 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, 316 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, 317 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, 318 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, 319 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, 320 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, 321 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, 322 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, 323 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, 324 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, 325 {0} 326 }; 327 328 /* Adjust IO delay for RGMII tx path */ 329 dra7xx_adj_io_delay(io_dly); 330 331 /* try reading mac address from efuse */ 332 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 333 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 334 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 335 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 336 mac_addr[2] = mac_hi & 0xFF; 337 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 338 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 339 mac_addr[5] = mac_lo & 0xFF; 340 341 if (!getenv("ethaddr")) { 342 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 343 344 if (is_valid_ether_addr(mac_addr)) 345 eth_setenv_enetaddr("ethaddr", mac_addr); 346 } 347 348 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 349 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 350 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 351 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 352 mac_addr[2] = mac_hi & 0xFF; 353 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 354 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 355 mac_addr[5] = mac_lo & 0xFF; 356 357 if (!getenv("eth1addr")) { 358 if (is_valid_ether_addr(mac_addr)) 359 eth_setenv_enetaddr("eth1addr", mac_addr); 360 } 361 362 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 363 ctrl_val |= 0x22; 364 writel(ctrl_val, (*ctrl)->control_core_control_io1); 365 366 if (*omap_si_rev == DRA722_ES1_0) 367 cpsw_data.active_slave = 1; 368 369 ret = cpsw_register(&cpsw_data); 370 if (ret < 0) 371 printf("Error %d registering CPSW switch\n", ret); 372 373 return ret; 374 } 375 #endif 376 377 #ifdef CONFIG_BOARD_EARLY_INIT_F 378 /* VTT regulator enable */ 379 static inline void vtt_regulator_enable(void) 380 { 381 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 382 return; 383 384 /* Do not enable VTT for DRA722 */ 385 if (omap_revision() == DRA722_ES1_0) 386 return; 387 388 /* 389 * EVM Rev G and later use gpio7_11 for DDR3 termination. 390 * This is safe enough to do on older revs. 391 */ 392 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 393 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 394 } 395 396 int board_early_init_f(void) 397 { 398 vtt_regulator_enable(); 399 return 0; 400 } 401 #endif 402