1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/mmc_host_def.h> 17 #include <asm/arch/sata.h> 18 19 #include "mux_data.h" 20 21 #ifdef CONFIG_DRIVER_TI_CPSW 22 #include <cpsw.h> 23 #endif 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 const struct omap_sysinfo sysinfo = { 28 "Board: DRA7xx\n" 29 }; 30 31 /* 32 * Adjust I/O delays on the Tx control and data lines of each MAC port. This 33 * is a workaround in order to work properly with the DP83865 PHYs on the EVM. 34 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we 35 * essentially need to counteract the DRA7xx internal delay, and we do this 36 * by delaying the control and data lines. If not using this PHY, you probably 37 * don't need to do this stuff! 38 */ 39 static void dra7xx_adj_io_delay(const struct io_delay *io_dly) 40 { 41 int i = 0; 42 u32 reg_val; 43 u32 delta; 44 u32 coarse; 45 u32 fine; 46 47 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); 48 49 while(io_dly[i].addr) { 50 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, 51 io_dly[i].addr); 52 delta = io_dly[i].dly; 53 reg_val = readl(io_dly[i].addr) & 0x3ff; 54 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); 55 coarse = (coarse > 0x1F) ? (0x1F) : (coarse); 56 fine = (reg_val & 0x1F) + (delta & 0x1F); 57 fine = (fine > 0x1F) ? (0x1F) : (fine); 58 reg_val = CFG_IO_DELAY_ACCESS_PATTERN | 59 CFG_IO_DELAY_LOCK_MASK | 60 ((coarse << 5) | (fine)); 61 writel(reg_val, io_dly[i].addr); 62 i++; 63 } 64 65 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); 66 } 67 68 /** 69 * @brief board_init 70 * 71 * @return 0 72 */ 73 int board_init(void) 74 { 75 gpmc_init(); 76 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 77 78 return 0; 79 } 80 81 int board_late_init(void) 82 { 83 omap_sata_init(); 84 return 0; 85 } 86 87 /** 88 * @brief misc_init_r - Configure EVM board specific configurations 89 * such as power configurations, ethernet initialization as phase2 of 90 * boot sequence 91 * 92 * @return 0 93 */ 94 int misc_init_r(void) 95 { 96 return 0; 97 } 98 99 static void do_set_mux32(u32 base, 100 struct pad_conf_entry const *array, int size) 101 { 102 int i; 103 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 104 105 for (i = 0; i < size; i++, pad++) 106 writel(pad->val, base + pad->offset); 107 } 108 109 void set_muxconf_regs_essential(void) 110 { 111 do_set_mux32((*ctrl)->control_padconf_core_base, 112 core_padconf_array_essential, 113 sizeof(core_padconf_array_essential) / 114 sizeof(struct pad_conf_entry)); 115 } 116 117 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 118 int board_mmc_init(bd_t *bis) 119 { 120 omap_mmc_init(0, 0, 0, -1, -1); 121 omap_mmc_init(1, 0, 0, -1, -1); 122 return 0; 123 } 124 #endif 125 126 #ifdef CONFIG_DRIVER_TI_CPSW 127 128 /* Delay value to add to calibrated value */ 129 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 130 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 131 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 132 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 133 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 134 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 135 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 136 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 137 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 138 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 139 140 static void cpsw_control(int enabled) 141 { 142 /* VTP can be added here */ 143 144 return; 145 } 146 147 static struct cpsw_slave_data cpsw_slaves[] = { 148 { 149 .slave_reg_ofs = 0x208, 150 .sliver_reg_ofs = 0xd80, 151 .phy_id = 0, 152 }, 153 { 154 .slave_reg_ofs = 0x308, 155 .sliver_reg_ofs = 0xdc0, 156 .phy_id = 1, 157 }, 158 }; 159 160 static struct cpsw_platform_data cpsw_data = { 161 .mdio_base = CPSW_MDIO_BASE, 162 .cpsw_base = CPSW_BASE, 163 .mdio_div = 0xff, 164 .channels = 8, 165 .cpdma_reg_ofs = 0x800, 166 .slaves = 1, 167 .slave_data = cpsw_slaves, 168 .ale_reg_ofs = 0xd00, 169 .ale_entries = 1024, 170 .host_port_reg_ofs = 0x108, 171 .hw_stats_reg_ofs = 0x900, 172 .bd_ram_ofs = 0x2000, 173 .mac_control = (1 << 5), 174 .control = cpsw_control, 175 .host_port_num = 0, 176 .version = CPSW_CTRL_VERSION_2, 177 }; 178 179 int board_eth_init(bd_t *bis) 180 { 181 int ret; 182 uint8_t mac_addr[6]; 183 uint32_t mac_hi, mac_lo; 184 uint32_t ctrl_val; 185 const struct io_delay io_dly[] = { 186 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, 187 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, 188 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, 189 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, 190 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, 191 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, 192 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, 193 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, 194 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, 195 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, 196 {0} 197 }; 198 199 /* Adjust IO delay for RGMII tx path */ 200 dra7xx_adj_io_delay(io_dly); 201 202 /* try reading mac address from efuse */ 203 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 204 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 205 mac_addr[0] = mac_hi & 0xFF; 206 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 207 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 208 mac_addr[3] = mac_lo & 0xFF; 209 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 210 mac_addr[5] = (mac_lo & 0xFF0000) >> 16; 211 212 if (!getenv("ethaddr")) { 213 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 214 215 if (is_valid_ether_addr(mac_addr)) 216 eth_setenv_enetaddr("ethaddr", mac_addr); 217 } 218 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 219 ctrl_val |= 0x22; 220 writel(ctrl_val, (*ctrl)->control_core_control_io1); 221 222 ret = cpsw_register(&cpsw_data); 223 if (ret < 0) 224 printf("Error %d registering CPSW switch\n", ret); 225 226 return ret; 227 } 228 #endif 229