1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <linux/string.h> 17 #include <asm/gpio.h> 18 #include <usb.h> 19 #include <linux/usb/gadget.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/dra7xx_iodelay.h> 22 #include <asm/emif.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/mmc_host_def.h> 25 #include <asm/arch/sata.h> 26 #include <environment.h> 27 #include <dwc3-uboot.h> 28 #include <dwc3-omap-uboot.h> 29 #include <ti-usb-phy-uboot.h> 30 31 #include "mux_data.h" 32 #include "../common/board_detect.h" 33 34 #define board_is_dra74x_evm() board_ti_is("5777xCPU") 35 #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \ 36 (strncmp("H", board_ti_get_rev(), 1) <= 0) 37 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ 38 board_ti_get_emif2_size() 39 40 #ifdef CONFIG_DRIVER_TI_CPSW 41 #include <cpsw.h> 42 #endif 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 /* GPIO 7_11 */ 47 #define GPIO_DDR_VTT_EN 203 48 49 #define SYSINFO_BOARD_NAME_MAX_LEN 37 50 51 const struct omap_sysinfo sysinfo = { 52 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" 53 }; 54 55 static const struct emif_regs emif1_ddr3_532_mhz_1cs = { 56 .sdram_config_init = 0x61851ab2, 57 .sdram_config = 0x61851ab2, 58 .sdram_config2 = 0x08000000, 59 .ref_ctrl = 0x000040F1, 60 .ref_ctrl_final = 0x00001035, 61 .sdram_tim1 = 0xCCCF36B3, 62 .sdram_tim2 = 0x308F7FDA, 63 .sdram_tim3 = 0x427F88A8, 64 .read_idle_ctrl = 0x00050000, 65 .zq_config = 0x0007190B, 66 .temp_alert_config = 0x00000000, 67 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 68 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 69 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 70 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 71 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 72 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 73 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 74 .emif_rd_wr_lvl_rmp_win = 0x00000000, 75 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 76 .emif_rd_wr_lvl_ctl = 0x00000000, 77 .emif_rd_wr_exec_thresh = 0x00000305 78 }; 79 80 static const struct emif_regs emif2_ddr3_532_mhz_1cs = { 81 .sdram_config_init = 0x61851B32, 82 .sdram_config = 0x61851B32, 83 .sdram_config2 = 0x08000000, 84 .ref_ctrl = 0x000040F1, 85 .ref_ctrl_final = 0x00001035, 86 .sdram_tim1 = 0xCCCF36B3, 87 .sdram_tim2 = 0x308F7FDA, 88 .sdram_tim3 = 0x427F88A8, 89 .read_idle_ctrl = 0x00050000, 90 .zq_config = 0x0007190B, 91 .temp_alert_config = 0x00000000, 92 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 93 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 94 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 95 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 96 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 97 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 98 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 99 .emif_rd_wr_lvl_rmp_win = 0x00000000, 100 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 101 .emif_rd_wr_lvl_ctl = 0x00000000, 102 .emif_rd_wr_exec_thresh = 0x00000305 103 }; 104 105 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { 106 .sdram_config_init = 0x61862B32, 107 .sdram_config = 0x61862B32, 108 .sdram_config2 = 0x08000000, 109 .ref_ctrl = 0x0000514C, 110 .ref_ctrl_final = 0x0000144A, 111 .sdram_tim1 = 0xD113781C, 112 .sdram_tim2 = 0x30717FE3, 113 .sdram_tim3 = 0x409F86A8, 114 .read_idle_ctrl = 0x00050000, 115 .zq_config = 0x5007190B, 116 .temp_alert_config = 0x00000000, 117 .emif_ddr_phy_ctlr_1_init = 0x0024400D, 118 .emif_ddr_phy_ctlr_1 = 0x0E24400D, 119 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 120 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, 121 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, 122 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, 123 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, 124 .emif_rd_wr_lvl_rmp_win = 0x00000000, 125 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 126 .emif_rd_wr_lvl_ctl = 0x00000000, 127 .emif_rd_wr_exec_thresh = 0x00000305 128 }; 129 130 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { 131 .sdram_config_init = 0x61851ab2, 132 .sdram_config = 0x61851ab2, 133 .sdram_config2 = 0x08000000, 134 .ref_ctrl = 0x000040F1, 135 .ref_ctrl_final = 0x00001035, 136 .sdram_tim1 = 0xCCCF36B3, 137 .sdram_tim2 = 0x30BF7FDA, 138 .sdram_tim3 = 0x427F8BA8, 139 .read_idle_ctrl = 0x00050000, 140 .zq_config = 0x0007190B, 141 .temp_alert_config = 0x00000000, 142 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 143 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 144 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 145 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 146 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 147 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 148 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 149 .emif_rd_wr_lvl_rmp_win = 0x00000000, 150 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 151 .emif_rd_wr_lvl_ctl = 0x00000000, 152 .emif_rd_wr_exec_thresh = 0x00000305 153 }; 154 155 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { 156 .sdram_config_init = 0x61851B32, 157 .sdram_config = 0x61851B32, 158 .sdram_config2 = 0x08000000, 159 .ref_ctrl = 0x000040F1, 160 .ref_ctrl_final = 0x00001035, 161 .sdram_tim1 = 0xCCCF36B3, 162 .sdram_tim2 = 0x308F7FDA, 163 .sdram_tim3 = 0x427F88A8, 164 .read_idle_ctrl = 0x00050000, 165 .zq_config = 0x0007190B, 166 .temp_alert_config = 0x00000000, 167 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 168 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 169 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 170 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 171 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 172 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 173 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 174 .emif_rd_wr_lvl_rmp_win = 0x00000000, 175 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 176 .emif_rd_wr_lvl_ctl = 0x00000000, 177 .emif_rd_wr_exec_thresh = 0x00000305 178 }; 179 180 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 181 { 182 u64 ram_size; 183 184 ram_size = board_ti_get_emif_size(); 185 186 switch (omap_revision()) { 187 case DRA752_ES1_0: 188 case DRA752_ES1_1: 189 case DRA752_ES2_0: 190 switch (emif_nr) { 191 case 1: 192 if (ram_size > CONFIG_MAX_MEM_MAPPED) 193 *regs = &emif1_ddr3_532_mhz_1cs_2G; 194 else 195 *regs = &emif1_ddr3_532_mhz_1cs; 196 break; 197 case 2: 198 if (ram_size > CONFIG_MAX_MEM_MAPPED) 199 *regs = &emif2_ddr3_532_mhz_1cs_2G; 200 else 201 *regs = &emif2_ddr3_532_mhz_1cs; 202 break; 203 } 204 break; 205 case DRA722_ES1_0: 206 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; 207 break; 208 default: 209 *regs = &emif1_ddr3_532_mhz_1cs; 210 } 211 } 212 213 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = { 214 .dmm_lisa_map_0 = 0x0, 215 .dmm_lisa_map_1 = 0x80640300, 216 .dmm_lisa_map_2 = 0xC0500220, 217 .dmm_lisa_map_3 = 0xFF020100, 218 .is_ma_present = 0x1 219 }; 220 221 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { 222 .dmm_lisa_map_0 = 0x0, 223 .dmm_lisa_map_1 = 0x0, 224 .dmm_lisa_map_2 = 0x80600100, 225 .dmm_lisa_map_3 = 0xFF020100, 226 .is_ma_present = 0x1 227 }; 228 229 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { 230 .dmm_lisa_map_0 = 0x0, 231 .dmm_lisa_map_1 = 0x0, 232 .dmm_lisa_map_2 = 0x80740300, 233 .dmm_lisa_map_3 = 0xFF020100, 234 .is_ma_present = 0x1 235 }; 236 237 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 238 { 239 u64 ram_size; 240 241 ram_size = board_ti_get_emif_size(); 242 243 switch (omap_revision()) { 244 case DRA752_ES1_0: 245 case DRA752_ES1_1: 246 case DRA752_ES2_0: 247 if (ram_size > CONFIG_MAX_MEM_MAPPED) 248 *dmm_lisa_regs = &lisa_map_dra7_2GB; 249 else 250 *dmm_lisa_regs = &lisa_map_dra7_1536MB; 251 break; 252 case DRA722_ES1_0: 253 default: 254 *dmm_lisa_regs = &lisa_map_2G_x_2; 255 } 256 } 257 258 /** 259 * @brief board_init 260 * 261 * @return 0 262 */ 263 int board_init(void) 264 { 265 gpmc_init(); 266 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 267 268 return 0; 269 } 270 271 void dram_init_banksize(void) 272 { 273 u64 ram_size; 274 275 ram_size = board_ti_get_emif_size(); 276 277 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 278 gd->bd->bi_dram[0].size = get_effective_memsize(); 279 if (ram_size > CONFIG_MAX_MEM_MAPPED) { 280 gd->bd->bi_dram[1].start = 0x200000000; 281 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; 282 } 283 } 284 285 int board_late_init(void) 286 { 287 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 288 char *name = "unknown"; 289 290 if (is_dra72x()) 291 name = "dra72x"; 292 else 293 name = "dra7xx"; 294 295 set_board_info_env(name); 296 297 omap_die_id_serial(); 298 #endif 299 return 0; 300 } 301 302 #ifdef CONFIG_SPL_BUILD 303 void do_board_detect(void) 304 { 305 int rc; 306 307 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, 308 CONFIG_EEPROM_CHIP_ADDRESS); 309 if (rc) 310 printf("ti_i2c_eeprom_init failed %d\n", rc); 311 } 312 313 #else 314 315 void do_board_detect(void) 316 { 317 char *bname = NULL; 318 int rc; 319 320 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, 321 CONFIG_EEPROM_CHIP_ADDRESS); 322 if (rc) 323 printf("ti_i2c_eeprom_init failed %d\n", rc); 324 325 if (board_is_dra74x_evm()) { 326 bname = "DRA74x EVM"; 327 /* If EEPROM is not populated */ 328 } else { 329 if (is_dra72x()) 330 bname = "DRA72x EVM"; 331 else 332 bname = "DRA74x EVM"; 333 } 334 335 if (bname) 336 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 337 "Board: %s REV %s\n", bname, board_ti_get_rev()); 338 } 339 #endif /* CONFIG_SPL_BUILD */ 340 341 void set_muxconf_regs(void) 342 { 343 do_set_mux32((*ctrl)->control_padconf_core_base, 344 early_padconf, ARRAY_SIZE(early_padconf)); 345 } 346 347 #ifdef CONFIG_IODELAY_RECALIBRATION 348 void recalibrate_iodelay(void) 349 { 350 struct pad_conf_entry const *pads; 351 struct iodelay_cfg_entry const *iodelay; 352 int npads, niodelays; 353 354 switch (omap_revision()) { 355 case DRA722_ES1_0: 356 pads = dra72x_core_padconf_array; 357 npads = ARRAY_SIZE(dra72x_core_padconf_array); 358 iodelay = dra72_iodelay_cfg_array; 359 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array); 360 break; 361 case DRA752_ES1_0: 362 case DRA752_ES1_1: 363 pads = dra74x_core_padconf_array; 364 npads = ARRAY_SIZE(dra74x_core_padconf_array); 365 iodelay = dra742_es1_1_iodelay_cfg_array; 366 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); 367 break; 368 default: 369 case DRA752_ES2_0: 370 pads = dra74x_core_padconf_array; 371 npads = ARRAY_SIZE(dra74x_core_padconf_array); 372 iodelay = dra742_es2_0_iodelay_cfg_array; 373 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); 374 /* Setup port1 and port2 for rgmii with 'no-id' mode */ 375 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | 376 RGMII1_ID_MODE_N_MASK); 377 break; 378 } 379 __recalibrate_iodelay(pads, npads, iodelay, niodelays); 380 } 381 #endif 382 383 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 384 int board_mmc_init(bd_t *bis) 385 { 386 omap_mmc_init(0, 0, 0, -1, -1); 387 omap_mmc_init(1, 0, 0, -1, -1); 388 return 0; 389 } 390 #endif 391 392 #ifdef CONFIG_USB_DWC3 393 static struct dwc3_device usb_otg_ss1 = { 394 .maximum_speed = USB_SPEED_SUPER, 395 .base = DRA7_USB_OTG_SS1_BASE, 396 .tx_fifo_resize = false, 397 .index = 0, 398 }; 399 400 static struct dwc3_omap_device usb_otg_ss1_glue = { 401 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 402 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 403 .index = 0, 404 }; 405 406 static struct ti_usb_phy_device usb_phy1_device = { 407 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 408 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 409 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 410 .index = 0, 411 }; 412 413 static struct dwc3_device usb_otg_ss2 = { 414 .maximum_speed = USB_SPEED_SUPER, 415 .base = DRA7_USB_OTG_SS2_BASE, 416 .tx_fifo_resize = false, 417 .index = 1, 418 }; 419 420 static struct dwc3_omap_device usb_otg_ss2_glue = { 421 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 422 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 423 .index = 1, 424 }; 425 426 static struct ti_usb_phy_device usb_phy2_device = { 427 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 428 .index = 1, 429 }; 430 431 int board_usb_init(int index, enum usb_init_type init) 432 { 433 enable_usb_clocks(index); 434 switch (index) { 435 case 0: 436 if (init == USB_INIT_DEVICE) { 437 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 438 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 439 } else { 440 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 441 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 442 } 443 444 ti_usb_phy_uboot_init(&usb_phy1_device); 445 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 446 dwc3_uboot_init(&usb_otg_ss1); 447 break; 448 case 1: 449 if (init == USB_INIT_DEVICE) { 450 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 451 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 452 } else { 453 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; 454 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 455 } 456 457 ti_usb_phy_uboot_init(&usb_phy2_device); 458 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 459 dwc3_uboot_init(&usb_otg_ss2); 460 break; 461 default: 462 printf("Invalid Controller Index\n"); 463 } 464 465 return 0; 466 } 467 468 int board_usb_cleanup(int index, enum usb_init_type init) 469 { 470 switch (index) { 471 case 0: 472 case 1: 473 ti_usb_phy_uboot_exit(index); 474 dwc3_uboot_exit(index); 475 dwc3_omap_uboot_exit(index); 476 break; 477 default: 478 printf("Invalid Controller Index\n"); 479 } 480 disable_usb_clocks(index); 481 return 0; 482 } 483 484 int usb_gadget_handle_interrupts(int index) 485 { 486 u32 status; 487 488 status = dwc3_omap_uboot_interrupt_status(index); 489 if (status) 490 dwc3_uboot_handle_interrupt(index); 491 492 return 0; 493 } 494 #endif 495 496 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 497 int spl_start_uboot(void) 498 { 499 /* break into full u-boot on 'c' */ 500 if (serial_tstc() && serial_getc() == 'c') 501 return 1; 502 503 #ifdef CONFIG_SPL_ENV_SUPPORT 504 env_init(); 505 env_relocate_spec(); 506 if (getenv_yesno("boot_os") != 1) 507 return 1; 508 #endif 509 510 return 0; 511 } 512 #endif 513 514 #ifdef CONFIG_DRIVER_TI_CPSW 515 extern u32 *const omap_si_rev; 516 517 static void cpsw_control(int enabled) 518 { 519 /* VTP can be added here */ 520 521 return; 522 } 523 524 static struct cpsw_slave_data cpsw_slaves[] = { 525 { 526 .slave_reg_ofs = 0x208, 527 .sliver_reg_ofs = 0xd80, 528 .phy_addr = 2, 529 }, 530 { 531 .slave_reg_ofs = 0x308, 532 .sliver_reg_ofs = 0xdc0, 533 .phy_addr = 3, 534 }, 535 }; 536 537 static struct cpsw_platform_data cpsw_data = { 538 .mdio_base = CPSW_MDIO_BASE, 539 .cpsw_base = CPSW_BASE, 540 .mdio_div = 0xff, 541 .channels = 8, 542 .cpdma_reg_ofs = 0x800, 543 .slaves = 2, 544 .slave_data = cpsw_slaves, 545 .ale_reg_ofs = 0xd00, 546 .ale_entries = 1024, 547 .host_port_reg_ofs = 0x108, 548 .hw_stats_reg_ofs = 0x900, 549 .bd_ram_ofs = 0x2000, 550 .mac_control = (1 << 5), 551 .control = cpsw_control, 552 .host_port_num = 0, 553 .version = CPSW_CTRL_VERSION_2, 554 }; 555 556 int board_eth_init(bd_t *bis) 557 { 558 int ret; 559 uint8_t mac_addr[6]; 560 uint32_t mac_hi, mac_lo; 561 uint32_t ctrl_val; 562 563 /* try reading mac address from efuse */ 564 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 565 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 566 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 567 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 568 mac_addr[2] = mac_hi & 0xFF; 569 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 570 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 571 mac_addr[5] = mac_lo & 0xFF; 572 573 if (!getenv("ethaddr")) { 574 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 575 576 if (is_valid_ethaddr(mac_addr)) 577 eth_setenv_enetaddr("ethaddr", mac_addr); 578 } 579 580 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 581 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 582 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 583 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 584 mac_addr[2] = mac_hi & 0xFF; 585 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 586 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 587 mac_addr[5] = mac_lo & 0xFF; 588 589 if (!getenv("eth1addr")) { 590 if (is_valid_ethaddr(mac_addr)) 591 eth_setenv_enetaddr("eth1addr", mac_addr); 592 } 593 594 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 595 ctrl_val |= 0x22; 596 writel(ctrl_val, (*ctrl)->control_core_control_io1); 597 598 if (*omap_si_rev == DRA722_ES1_0) 599 cpsw_data.active_slave = 1; 600 601 ret = cpsw_register(&cpsw_data); 602 if (ret < 0) 603 printf("Error %d registering CPSW switch\n", ret); 604 605 return ret; 606 } 607 #endif 608 609 #ifdef CONFIG_BOARD_EARLY_INIT_F 610 /* VTT regulator enable */ 611 static inline void vtt_regulator_enable(void) 612 { 613 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 614 return; 615 616 /* Do not enable VTT for DRA722 */ 617 if (omap_revision() == DRA722_ES1_0) 618 return; 619 620 /* 621 * EVM Rev G and later use gpio7_11 for DDR3 termination. 622 * This is safe enough to do on older revs. 623 */ 624 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 625 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 626 } 627 628 int board_early_init_f(void) 629 { 630 vtt_regulator_enable(); 631 return 0; 632 } 633 #endif 634