1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/mmc_host_def.h> 18 #include <asm/arch/sata.h> 19 20 #include "mux_data.h" 21 22 #ifdef CONFIG_DRIVER_TI_CPSW 23 #include <cpsw.h> 24 #endif 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 const struct omap_sysinfo sysinfo = { 29 "Board: DRA7xx\n" 30 }; 31 32 /* 33 * Adjust I/O delays on the Tx control and data lines of each MAC port. This 34 * is a workaround in order to work properly with the DP83865 PHYs on the EVM. 35 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we 36 * essentially need to counteract the DRA7xx internal delay, and we do this 37 * by delaying the control and data lines. If not using this PHY, you probably 38 * don't need to do this stuff! 39 */ 40 static void dra7xx_adj_io_delay(const struct io_delay *io_dly) 41 { 42 int i = 0; 43 u32 reg_val; 44 u32 delta; 45 u32 coarse; 46 u32 fine; 47 48 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); 49 50 while(io_dly[i].addr) { 51 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, 52 io_dly[i].addr); 53 delta = io_dly[i].dly; 54 reg_val = readl(io_dly[i].addr) & 0x3ff; 55 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); 56 coarse = (coarse > 0x1F) ? (0x1F) : (coarse); 57 fine = (reg_val & 0x1F) + (delta & 0x1F); 58 fine = (fine > 0x1F) ? (0x1F) : (fine); 59 reg_val = CFG_IO_DELAY_ACCESS_PATTERN | 60 CFG_IO_DELAY_LOCK_MASK | 61 ((coarse << 5) | (fine)); 62 writel(reg_val, io_dly[i].addr); 63 i++; 64 } 65 66 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); 67 } 68 69 /** 70 * @brief board_init 71 * 72 * @return 0 73 */ 74 int board_init(void) 75 { 76 gpmc_init(); 77 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 78 79 return 0; 80 } 81 82 int board_late_init(void) 83 { 84 init_sata(0); 85 return 0; 86 } 87 88 /** 89 * @brief misc_init_r - Configure EVM board specific configurations 90 * such as power configurations, ethernet initialization as phase2 of 91 * boot sequence 92 * 93 * @return 0 94 */ 95 int misc_init_r(void) 96 { 97 return 0; 98 } 99 100 static void do_set_mux32(u32 base, 101 struct pad_conf_entry const *array, int size) 102 { 103 int i; 104 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 105 106 for (i = 0; i < size; i++, pad++) 107 writel(pad->val, base + pad->offset); 108 } 109 110 void set_muxconf_regs_essential(void) 111 { 112 do_set_mux32((*ctrl)->control_padconf_core_base, 113 core_padconf_array_essential, 114 sizeof(core_padconf_array_essential) / 115 sizeof(struct pad_conf_entry)); 116 } 117 118 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 119 int board_mmc_init(bd_t *bis) 120 { 121 omap_mmc_init(0, 0, 0, -1, -1); 122 omap_mmc_init(1, 0, 0, -1, -1); 123 return 0; 124 } 125 #endif 126 127 #ifdef CONFIG_DRIVER_TI_CPSW 128 129 /* Delay value to add to calibrated value */ 130 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 131 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 132 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 133 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 134 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 135 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 136 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 137 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 138 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 139 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 140 141 static void cpsw_control(int enabled) 142 { 143 /* VTP can be added here */ 144 145 return; 146 } 147 148 static struct cpsw_slave_data cpsw_slaves[] = { 149 { 150 .slave_reg_ofs = 0x208, 151 .sliver_reg_ofs = 0xd80, 152 .phy_id = 0, 153 }, 154 { 155 .slave_reg_ofs = 0x308, 156 .sliver_reg_ofs = 0xdc0, 157 .phy_id = 1, 158 }, 159 }; 160 161 static struct cpsw_platform_data cpsw_data = { 162 .mdio_base = CPSW_MDIO_BASE, 163 .cpsw_base = CPSW_BASE, 164 .mdio_div = 0xff, 165 .channels = 8, 166 .cpdma_reg_ofs = 0x800, 167 .slaves = 1, 168 .slave_data = cpsw_slaves, 169 .ale_reg_ofs = 0xd00, 170 .ale_entries = 1024, 171 .host_port_reg_ofs = 0x108, 172 .hw_stats_reg_ofs = 0x900, 173 .bd_ram_ofs = 0x2000, 174 .mac_control = (1 << 5), 175 .control = cpsw_control, 176 .host_port_num = 0, 177 .version = CPSW_CTRL_VERSION_2, 178 }; 179 180 int board_eth_init(bd_t *bis) 181 { 182 int ret; 183 uint8_t mac_addr[6]; 184 uint32_t mac_hi, mac_lo; 185 uint32_t ctrl_val; 186 const struct io_delay io_dly[] = { 187 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, 188 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, 189 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, 190 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, 191 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, 192 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, 193 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, 194 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, 195 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, 196 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, 197 {0} 198 }; 199 200 /* Adjust IO delay for RGMII tx path */ 201 dra7xx_adj_io_delay(io_dly); 202 203 /* try reading mac address from efuse */ 204 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 205 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 206 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 207 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 208 mac_addr[2] = mac_hi & 0xFF; 209 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 210 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 211 mac_addr[5] = mac_lo & 0xFF; 212 213 if (!getenv("ethaddr")) { 214 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 215 216 if (is_valid_ether_addr(mac_addr)) 217 eth_setenv_enetaddr("ethaddr", mac_addr); 218 } 219 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 220 ctrl_val |= 0x22; 221 writel(ctrl_val, (*ctrl)->control_core_control_io1); 222 223 ret = cpsw_register(&cpsw_data); 224 if (ret < 0) 225 printf("Error %d registering CPSW switch\n", ret); 226 227 return ret; 228 } 229 #endif 230