1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <asm/gpio.h> 17 #include <usb.h> 18 #include <linux/usb/gadget.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/dra7xx_iodelay.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/sata.h> 24 #include <environment.h> 25 #include <dwc3-uboot.h> 26 #include <dwc3-omap-uboot.h> 27 #include <ti-usb-phy-uboot.h> 28 29 #include "mux_data.h" 30 31 #ifdef CONFIG_DRIVER_TI_CPSW 32 #include <cpsw.h> 33 #endif 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* GPIO 7_11 */ 38 #define GPIO_DDR_VTT_EN 203 39 40 const struct omap_sysinfo sysinfo = { 41 "Board: DRA7xx\n" 42 }; 43 44 /** 45 * @brief board_init 46 * 47 * @return 0 48 */ 49 int board_init(void) 50 { 51 gpmc_init(); 52 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 53 54 return 0; 55 } 56 57 int board_late_init(void) 58 { 59 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 60 if (omap_revision() == DRA722_ES1_0) 61 setenv("board_name", "dra72x"); 62 else 63 setenv("board_name", "dra7xx"); 64 65 omap_die_id_serial(); 66 #endif 67 return 0; 68 } 69 70 void set_muxconf_regs_essential(void) 71 { 72 do_set_mux32((*ctrl)->control_padconf_core_base, 73 early_padconf, ARRAY_SIZE(early_padconf)); 74 } 75 76 #ifdef CONFIG_IODELAY_RECALIBRATION 77 void recalibrate_iodelay(void) 78 { 79 struct pad_conf_entry const *pads; 80 struct iodelay_cfg_entry const *iodelay; 81 int npads, niodelays; 82 83 switch (omap_revision()) { 84 case DRA722_ES1_0: 85 pads = core_padconf_array_essential; 86 npads = ARRAY_SIZE(core_padconf_array_essential); 87 iodelay = iodelay_cfg_array; 88 niodelays = ARRAY_SIZE(iodelay_cfg_array); 89 break; 90 case DRA752_ES1_0: 91 case DRA752_ES1_1: 92 pads = dra74x_core_padconf_array; 93 npads = ARRAY_SIZE(dra74x_core_padconf_array); 94 iodelay = dra742_es1_1_iodelay_cfg_array; 95 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); 96 break; 97 default: 98 case DRA752_ES2_0: 99 pads = dra74x_core_padconf_array; 100 npads = ARRAY_SIZE(dra74x_core_padconf_array); 101 iodelay = dra742_es2_0_iodelay_cfg_array; 102 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); 103 /* Setup port1 and port2 for rgmii with 'no-id' mode */ 104 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | 105 RGMII1_ID_MODE_N_MASK); 106 break; 107 } 108 __recalibrate_iodelay(pads, npads, iodelay, niodelays); 109 } 110 #endif 111 112 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 113 int board_mmc_init(bd_t *bis) 114 { 115 omap_mmc_init(0, 0, 0, -1, -1); 116 omap_mmc_init(1, 0, 0, -1, -1); 117 return 0; 118 } 119 #endif 120 121 #ifdef CONFIG_USB_DWC3 122 static struct dwc3_device usb_otg_ss1 = { 123 .maximum_speed = USB_SPEED_SUPER, 124 .base = DRA7_USB_OTG_SS1_BASE, 125 .tx_fifo_resize = false, 126 .index = 0, 127 }; 128 129 static struct dwc3_omap_device usb_otg_ss1_glue = { 130 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 131 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 132 .index = 0, 133 }; 134 135 static struct ti_usb_phy_device usb_phy1_device = { 136 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 137 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 138 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 139 .index = 0, 140 }; 141 142 static struct dwc3_device usb_otg_ss2 = { 143 .maximum_speed = USB_SPEED_SUPER, 144 .base = DRA7_USB_OTG_SS2_BASE, 145 .tx_fifo_resize = false, 146 .index = 1, 147 }; 148 149 static struct dwc3_omap_device usb_otg_ss2_glue = { 150 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 151 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 152 .index = 1, 153 }; 154 155 static struct ti_usb_phy_device usb_phy2_device = { 156 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 157 .index = 1, 158 }; 159 160 int board_usb_init(int index, enum usb_init_type init) 161 { 162 enable_usb_clocks(index); 163 switch (index) { 164 case 0: 165 if (init == USB_INIT_DEVICE) { 166 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 167 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 168 } else { 169 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 170 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 171 } 172 173 ti_usb_phy_uboot_init(&usb_phy1_device); 174 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 175 dwc3_uboot_init(&usb_otg_ss1); 176 break; 177 case 1: 178 if (init == USB_INIT_DEVICE) { 179 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 180 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 181 } else { 182 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; 183 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 184 } 185 186 ti_usb_phy_uboot_init(&usb_phy2_device); 187 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 188 dwc3_uboot_init(&usb_otg_ss2); 189 break; 190 default: 191 printf("Invalid Controller Index\n"); 192 } 193 194 return 0; 195 } 196 197 int board_usb_cleanup(int index, enum usb_init_type init) 198 { 199 switch (index) { 200 case 0: 201 case 1: 202 ti_usb_phy_uboot_exit(index); 203 dwc3_uboot_exit(index); 204 dwc3_omap_uboot_exit(index); 205 break; 206 default: 207 printf("Invalid Controller Index\n"); 208 } 209 disable_usb_clocks(index); 210 return 0; 211 } 212 213 int usb_gadget_handle_interrupts(int index) 214 { 215 u32 status; 216 217 status = dwc3_omap_uboot_interrupt_status(index); 218 if (status) 219 dwc3_uboot_handle_interrupt(index); 220 221 return 0; 222 } 223 #endif 224 225 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 226 int spl_start_uboot(void) 227 { 228 /* break into full u-boot on 'c' */ 229 if (serial_tstc() && serial_getc() == 'c') 230 return 1; 231 232 #ifdef CONFIG_SPL_ENV_SUPPORT 233 env_init(); 234 env_relocate_spec(); 235 if (getenv_yesno("boot_os") != 1) 236 return 1; 237 #endif 238 239 return 0; 240 } 241 #endif 242 243 #ifdef CONFIG_DRIVER_TI_CPSW 244 extern u32 *const omap_si_rev; 245 246 static void cpsw_control(int enabled) 247 { 248 /* VTP can be added here */ 249 250 return; 251 } 252 253 static struct cpsw_slave_data cpsw_slaves[] = { 254 { 255 .slave_reg_ofs = 0x208, 256 .sliver_reg_ofs = 0xd80, 257 .phy_addr = 2, 258 }, 259 { 260 .slave_reg_ofs = 0x308, 261 .sliver_reg_ofs = 0xdc0, 262 .phy_addr = 3, 263 }, 264 }; 265 266 static struct cpsw_platform_data cpsw_data = { 267 .mdio_base = CPSW_MDIO_BASE, 268 .cpsw_base = CPSW_BASE, 269 .mdio_div = 0xff, 270 .channels = 8, 271 .cpdma_reg_ofs = 0x800, 272 .slaves = 2, 273 .slave_data = cpsw_slaves, 274 .ale_reg_ofs = 0xd00, 275 .ale_entries = 1024, 276 .host_port_reg_ofs = 0x108, 277 .hw_stats_reg_ofs = 0x900, 278 .bd_ram_ofs = 0x2000, 279 .mac_control = (1 << 5), 280 .control = cpsw_control, 281 .host_port_num = 0, 282 .version = CPSW_CTRL_VERSION_2, 283 }; 284 285 int board_eth_init(bd_t *bis) 286 { 287 int ret; 288 uint8_t mac_addr[6]; 289 uint32_t mac_hi, mac_lo; 290 uint32_t ctrl_val; 291 292 /* try reading mac address from efuse */ 293 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 294 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 295 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 296 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 297 mac_addr[2] = mac_hi & 0xFF; 298 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 299 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 300 mac_addr[5] = mac_lo & 0xFF; 301 302 if (!getenv("ethaddr")) { 303 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 304 305 if (is_valid_ethaddr(mac_addr)) 306 eth_setenv_enetaddr("ethaddr", mac_addr); 307 } 308 309 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 310 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 311 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 312 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 313 mac_addr[2] = mac_hi & 0xFF; 314 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 315 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 316 mac_addr[5] = mac_lo & 0xFF; 317 318 if (!getenv("eth1addr")) { 319 if (is_valid_ethaddr(mac_addr)) 320 eth_setenv_enetaddr("eth1addr", mac_addr); 321 } 322 323 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 324 ctrl_val |= 0x22; 325 writel(ctrl_val, (*ctrl)->control_core_control_io1); 326 327 if (*omap_si_rev == DRA722_ES1_0) 328 cpsw_data.active_slave = 1; 329 330 ret = cpsw_register(&cpsw_data); 331 if (ret < 0) 332 printf("Error %d registering CPSW switch\n", ret); 333 334 return ret; 335 } 336 #endif 337 338 #ifdef CONFIG_BOARD_EARLY_INIT_F 339 /* VTT regulator enable */ 340 static inline void vtt_regulator_enable(void) 341 { 342 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 343 return; 344 345 /* Do not enable VTT for DRA722 */ 346 if (omap_revision() == DRA722_ES1_0) 347 return; 348 349 /* 350 * EVM Rev G and later use gpio7_11 for DDR3 termination. 351 * This is safe enough to do on older revs. 352 */ 353 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 354 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 355 } 356 357 int board_early_init_f(void) 358 { 359 vtt_regulator_enable(); 360 return 0; 361 } 362 #endif 363