1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/mmc_host_def.h> 17 18 #include "mux_data.h" 19 20 #ifdef CONFIG_DRIVER_TI_CPSW 21 #include <cpsw.h> 22 #endif 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 const struct omap_sysinfo sysinfo = { 27 "Board: DRA7xx\n" 28 }; 29 30 /* 31 * Adjust I/O delays on the Tx control and data lines of each MAC port. This 32 * is a workaround in order to work properly with the DP83865 PHYs on the EVM. 33 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we 34 * essentially need to counteract the DRA7xx internal delay, and we do this 35 * by delaying the control and data lines. If not using this PHY, you probably 36 * don't need to do this stuff! 37 */ 38 static void dra7xx_adj_io_delay(const struct io_delay *io_dly) 39 { 40 int i = 0; 41 u32 reg_val; 42 u32 delta; 43 u32 coarse; 44 u32 fine; 45 46 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); 47 48 while(io_dly[i].addr) { 49 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, 50 io_dly[i].addr); 51 delta = io_dly[i].dly; 52 reg_val = readl(io_dly[i].addr) & 0x3ff; 53 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); 54 coarse = (coarse > 0x1F) ? (0x1F) : (coarse); 55 fine = (reg_val & 0x1F) + (delta & 0x1F); 56 fine = (fine > 0x1F) ? (0x1F) : (fine); 57 reg_val = CFG_IO_DELAY_ACCESS_PATTERN | 58 CFG_IO_DELAY_LOCK_MASK | 59 ((coarse << 5) | (fine)); 60 writel(reg_val, io_dly[i].addr); 61 i++; 62 } 63 64 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); 65 } 66 67 /** 68 * @brief board_init 69 * 70 * @return 0 71 */ 72 int board_init(void) 73 { 74 gpmc_init(); 75 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 76 77 return 0; 78 } 79 80 /** 81 * @brief misc_init_r - Configure EVM board specific configurations 82 * such as power configurations, ethernet initialization as phase2 of 83 * boot sequence 84 * 85 * @return 0 86 */ 87 int misc_init_r(void) 88 { 89 return 0; 90 } 91 92 static void do_set_mux32(u32 base, 93 struct pad_conf_entry const *array, int size) 94 { 95 int i; 96 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 97 98 for (i = 0; i < size; i++, pad++) 99 writel(pad->val, base + pad->offset); 100 } 101 102 void set_muxconf_regs_essential(void) 103 { 104 do_set_mux32((*ctrl)->control_padconf_core_base, 105 core_padconf_array_essential, 106 sizeof(core_padconf_array_essential) / 107 sizeof(struct pad_conf_entry)); 108 } 109 110 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 111 int board_mmc_init(bd_t *bis) 112 { 113 omap_mmc_init(0, 0, 0, -1, -1); 114 omap_mmc_init(1, 0, 0, -1, -1); 115 return 0; 116 } 117 #endif 118 119 #ifdef CONFIG_DRIVER_TI_CPSW 120 121 /* Delay value to add to calibrated value */ 122 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 123 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 124 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 125 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 126 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 127 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 128 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 129 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 130 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 131 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 132 133 static void cpsw_control(int enabled) 134 { 135 /* VTP can be added here */ 136 137 return; 138 } 139 140 static struct cpsw_slave_data cpsw_slaves[] = { 141 { 142 .slave_reg_ofs = 0x208, 143 .sliver_reg_ofs = 0xd80, 144 .phy_id = 0, 145 }, 146 { 147 .slave_reg_ofs = 0x308, 148 .sliver_reg_ofs = 0xdc0, 149 .phy_id = 1, 150 }, 151 }; 152 153 static struct cpsw_platform_data cpsw_data = { 154 .mdio_base = CPSW_MDIO_BASE, 155 .cpsw_base = CPSW_BASE, 156 .mdio_div = 0xff, 157 .channels = 8, 158 .cpdma_reg_ofs = 0x800, 159 .slaves = 1, 160 .slave_data = cpsw_slaves, 161 .ale_reg_ofs = 0xd00, 162 .ale_entries = 1024, 163 .host_port_reg_ofs = 0x108, 164 .hw_stats_reg_ofs = 0x900, 165 .bd_ram_ofs = 0x2000, 166 .mac_control = (1 << 5), 167 .control = cpsw_control, 168 .host_port_num = 0, 169 .version = CPSW_CTRL_VERSION_2, 170 }; 171 172 int board_eth_init(bd_t *bis) 173 { 174 int ret; 175 uint8_t mac_addr[6]; 176 uint32_t mac_hi, mac_lo; 177 uint32_t ctrl_val; 178 const struct io_delay io_dly[] = { 179 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, 180 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, 181 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, 182 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, 183 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, 184 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, 185 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, 186 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, 187 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, 188 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, 189 {0} 190 }; 191 192 /* Adjust IO delay for RGMII tx path */ 193 dra7xx_adj_io_delay(io_dly); 194 195 /* try reading mac address from efuse */ 196 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 197 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 198 mac_addr[0] = mac_hi & 0xFF; 199 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 200 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 201 mac_addr[3] = mac_lo & 0xFF; 202 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 203 mac_addr[5] = (mac_lo & 0xFF0000) >> 16; 204 205 if (!getenv("ethaddr")) { 206 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 207 208 if (is_valid_ether_addr(mac_addr)) 209 eth_setenv_enetaddr("ethaddr", mac_addr); 210 } 211 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 212 ctrl_val |= 0x22; 213 writel(ctrl_val, (*ctrl)->control_core_control_io1); 214 215 ret = cpsw_register(&cpsw_data); 216 if (ret < 0) 217 printf("Error %d registering CPSW switch\n", ret); 218 219 return ret; 220 } 221 #endif 222