1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/mmc_host_def.h> 18 #include <asm/arch/sata.h> 19 #include <environment.h> 20 21 #include "mux_data.h" 22 23 #ifdef CONFIG_DRIVER_TI_CPSW 24 #include <cpsw.h> 25 #endif 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 const struct omap_sysinfo sysinfo = { 30 "Board: DRA7xx\n" 31 }; 32 33 /* 34 * Adjust I/O delays on the Tx control and data lines of each MAC port. This 35 * is a workaround in order to work properly with the DP83865 PHYs on the EVM. 36 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we 37 * essentially need to counteract the DRA7xx internal delay, and we do this 38 * by delaying the control and data lines. If not using this PHY, you probably 39 * don't need to do this stuff! 40 */ 41 static void dra7xx_adj_io_delay(const struct io_delay *io_dly) 42 { 43 int i = 0; 44 u32 reg_val; 45 u32 delta; 46 u32 coarse; 47 u32 fine; 48 49 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); 50 51 while(io_dly[i].addr) { 52 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, 53 io_dly[i].addr); 54 delta = io_dly[i].dly; 55 reg_val = readl(io_dly[i].addr) & 0x3ff; 56 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); 57 coarse = (coarse > 0x1F) ? (0x1F) : (coarse); 58 fine = (reg_val & 0x1F) + (delta & 0x1F); 59 fine = (fine > 0x1F) ? (0x1F) : (fine); 60 reg_val = CFG_IO_DELAY_ACCESS_PATTERN | 61 CFG_IO_DELAY_LOCK_MASK | 62 ((coarse << 5) | (fine)); 63 writel(reg_val, io_dly[i].addr); 64 i++; 65 } 66 67 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); 68 } 69 70 /** 71 * @brief board_init 72 * 73 * @return 0 74 */ 75 int board_init(void) 76 { 77 gpmc_init(); 78 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 79 80 return 0; 81 } 82 83 int board_late_init(void) 84 { 85 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 86 if (omap_revision() == DRA722_ES1_0) 87 setenv("board_name", "dra72x"); 88 else 89 setenv("board_name", "dra7xx"); 90 #endif 91 init_sata(0); 92 return 0; 93 } 94 95 /** 96 * @brief misc_init_r - Configure EVM board specific configurations 97 * such as power configurations, ethernet initialization as phase2 of 98 * boot sequence 99 * 100 * @return 0 101 */ 102 int misc_init_r(void) 103 { 104 return 0; 105 } 106 107 static void do_set_mux32(u32 base, 108 struct pad_conf_entry const *array, int size) 109 { 110 int i; 111 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 112 113 for (i = 0; i < size; i++, pad++) 114 writel(pad->val, base + pad->offset); 115 } 116 117 void set_muxconf_regs_essential(void) 118 { 119 do_set_mux32((*ctrl)->control_padconf_core_base, 120 core_padconf_array_essential, 121 sizeof(core_padconf_array_essential) / 122 sizeof(struct pad_conf_entry)); 123 } 124 125 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 126 int board_mmc_init(bd_t *bis) 127 { 128 omap_mmc_init(0, 0, 0, -1, -1); 129 omap_mmc_init(1, 0, 0, -1, -1); 130 return 0; 131 } 132 #endif 133 134 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 135 int spl_start_uboot(void) 136 { 137 /* break into full u-boot on 'c' */ 138 if (serial_tstc() && serial_getc() == 'c') 139 return 1; 140 141 #ifdef CONFIG_SPL_ENV_SUPPORT 142 env_init(); 143 env_relocate_spec(); 144 if (getenv_yesno("boot_os") != 1) 145 return 1; 146 #endif 147 148 return 0; 149 } 150 #endif 151 152 #ifdef CONFIG_DRIVER_TI_CPSW 153 154 /* Delay value to add to calibrated value */ 155 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 156 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 157 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 158 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 159 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 160 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 161 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 162 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 163 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 164 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 165 166 extern u32 *const omap_si_rev; 167 168 static void cpsw_control(int enabled) 169 { 170 /* VTP can be added here */ 171 172 return; 173 } 174 175 static struct cpsw_slave_data cpsw_slaves[] = { 176 { 177 .slave_reg_ofs = 0x208, 178 .sliver_reg_ofs = 0xd80, 179 .phy_addr = 2, 180 }, 181 { 182 .slave_reg_ofs = 0x308, 183 .sliver_reg_ofs = 0xdc0, 184 .phy_addr = 3, 185 }, 186 }; 187 188 static struct cpsw_platform_data cpsw_data = { 189 .mdio_base = CPSW_MDIO_BASE, 190 .cpsw_base = CPSW_BASE, 191 .mdio_div = 0xff, 192 .channels = 8, 193 .cpdma_reg_ofs = 0x800, 194 .slaves = 2, 195 .slave_data = cpsw_slaves, 196 .ale_reg_ofs = 0xd00, 197 .ale_entries = 1024, 198 .host_port_reg_ofs = 0x108, 199 .hw_stats_reg_ofs = 0x900, 200 .bd_ram_ofs = 0x2000, 201 .mac_control = (1 << 5), 202 .control = cpsw_control, 203 .host_port_num = 0, 204 .version = CPSW_CTRL_VERSION_2, 205 }; 206 207 int board_eth_init(bd_t *bis) 208 { 209 int ret; 210 uint8_t mac_addr[6]; 211 uint32_t mac_hi, mac_lo; 212 uint32_t ctrl_val; 213 const struct io_delay io_dly[] = { 214 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, 215 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, 216 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, 217 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, 218 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, 219 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, 220 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, 221 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, 222 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, 223 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, 224 {0} 225 }; 226 227 /* Adjust IO delay for RGMII tx path */ 228 dra7xx_adj_io_delay(io_dly); 229 230 /* try reading mac address from efuse */ 231 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 232 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 233 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 234 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 235 mac_addr[2] = mac_hi & 0xFF; 236 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 237 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 238 mac_addr[5] = mac_lo & 0xFF; 239 240 if (!getenv("ethaddr")) { 241 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 242 243 if (is_valid_ether_addr(mac_addr)) 244 eth_setenv_enetaddr("ethaddr", mac_addr); 245 } 246 247 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 248 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 249 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 250 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 251 mac_addr[2] = mac_hi & 0xFF; 252 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 253 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 254 mac_addr[5] = mac_lo & 0xFF; 255 256 if (!getenv("eth1addr")) { 257 if (is_valid_ether_addr(mac_addr)) 258 eth_setenv_enetaddr("eth1addr", mac_addr); 259 } 260 261 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 262 ctrl_val |= 0x22; 263 writel(ctrl_val, (*ctrl)->control_core_control_io1); 264 265 if (*omap_si_rev == DRA722_ES1_0) 266 cpsw_data.active_slave = 1; 267 268 ret = cpsw_register(&cpsw_data); 269 if (ret < 0) 270 printf("Error %d registering CPSW switch\n", ret); 271 272 return ret; 273 } 274 #endif 275