1 /* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com 3 * 4 * Author: Felipe Balbi <balbi@ti.com> 5 * 6 * Based on board/ti/dra7xx/evm.c 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <palmas.h> 13 #include <sata.h> 14 #include <usb.h> 15 #include <asm/omap_common.h> 16 #include <asm/emif.h> 17 #include <asm/gpio.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/dra7xx_iodelay.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/sata.h> 24 #include <asm/arch/gpio.h> 25 #include <asm/arch/omap.h> 26 #include <environment.h> 27 #include <usb.h> 28 #include <linux/usb/gadget.h> 29 #include <dwc3-uboot.h> 30 #include <dwc3-omap-uboot.h> 31 #include <ti-usb-phy-uboot.h> 32 33 #include "../common/board_detect.h" 34 #include "mux_data.h" 35 36 #define board_is_x15() board_ti_is("BBRDX15_") 37 #define board_is_am572x_evm() board_ti_is("AM572PM_") 38 39 #ifdef CONFIG_DRIVER_TI_CPSW 40 #include <cpsw.h> 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* GPIO 7_11 */ 46 #define GPIO_DDR_VTT_EN 203 47 48 #define SYSINFO_BOARD_NAME_MAX_LEN 45 49 50 const struct omap_sysinfo sysinfo = { 51 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n" 52 }; 53 54 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { 55 .dmm_lisa_map_3 = 0x80740300, 56 .is_ma_present = 0x1 57 }; 58 59 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 60 { 61 *dmm_lisa_regs = &beagle_x15_lisa_regs; 62 } 63 64 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { 65 .sdram_config_init = 0x61851b32, 66 .sdram_config = 0x61851b32, 67 .sdram_config2 = 0x08000000, 68 .ref_ctrl = 0x000040F1, 69 .ref_ctrl_final = 0x00001035, 70 .sdram_tim1 = 0xcccf36ab, 71 .sdram_tim2 = 0x308f7fda, 72 .sdram_tim3 = 0x409f88a8, 73 .read_idle_ctrl = 0x00050000, 74 .zq_config = 0x5007190b, 75 .temp_alert_config = 0x00000000, 76 .emif_ddr_phy_ctlr_1_init = 0x0024400b, 77 .emif_ddr_phy_ctlr_1 = 0x0e24400b, 78 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 79 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 80 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 81 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 82 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 83 .emif_rd_wr_lvl_rmp_win = 0x00000000, 84 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 85 .emif_rd_wr_lvl_ctl = 0x00000000, 86 .emif_rd_wr_exec_thresh = 0x00000305 87 }; 88 89 /* Ext phy ctrl regs 1-35 */ 90 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 91 0x10040100, 92 0x00910091, 93 0x00950095, 94 0x009B009B, 95 0x009E009E, 96 0x00980098, 97 0x00340034, 98 0x00350035, 99 0x00340034, 100 0x00310031, 101 0x00340034, 102 0x007F007F, 103 0x007F007F, 104 0x007F007F, 105 0x007F007F, 106 0x007F007F, 107 0x00480048, 108 0x004A004A, 109 0x00520052, 110 0x00550055, 111 0x00500050, 112 0x00000000, 113 0x00600020, 114 0x40011080, 115 0x08102040, 116 0x0, 117 0x0, 118 0x0, 119 0x0, 120 0x0, 121 0x0, 122 0x0, 123 0x0, 124 0x0, 125 0x0 126 }; 127 128 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { 129 .sdram_config_init = 0x61851b32, 130 .sdram_config = 0x61851b32, 131 .sdram_config2 = 0x08000000, 132 .ref_ctrl = 0x000040F1, 133 .ref_ctrl_final = 0x00001035, 134 .sdram_tim1 = 0xcccf36ab, 135 .sdram_tim2 = 0x308f7fda, 136 .sdram_tim3 = 0x409f88a8, 137 .read_idle_ctrl = 0x00050000, 138 .zq_config = 0x5007190b, 139 .temp_alert_config = 0x00000000, 140 .emif_ddr_phy_ctlr_1_init = 0x0024400b, 141 .emif_ddr_phy_ctlr_1 = 0x0e24400b, 142 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 143 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 144 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 145 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 146 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 147 .emif_rd_wr_lvl_rmp_win = 0x00000000, 148 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 149 .emif_rd_wr_lvl_ctl = 0x00000000, 150 .emif_rd_wr_exec_thresh = 0x00000305 151 }; 152 153 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 154 0x10040100, 155 0x00910091, 156 0x00950095, 157 0x009B009B, 158 0x009E009E, 159 0x00980098, 160 0x00340034, 161 0x00350035, 162 0x00340034, 163 0x00310031, 164 0x00340034, 165 0x007F007F, 166 0x007F007F, 167 0x007F007F, 168 0x007F007F, 169 0x007F007F, 170 0x00480048, 171 0x004A004A, 172 0x00520052, 173 0x00550055, 174 0x00500050, 175 0x00000000, 176 0x00600020, 177 0x40011080, 178 0x08102040, 179 0x0, 180 0x0, 181 0x0, 182 0x0, 183 0x0, 184 0x0, 185 0x0, 186 0x0, 187 0x0, 188 0x0 189 }; 190 191 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 192 { 193 switch (emif_nr) { 194 case 1: 195 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; 196 break; 197 case 2: 198 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; 199 break; 200 } 201 } 202 203 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) 204 { 205 switch (emif_nr) { 206 case 1: 207 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; 208 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); 209 break; 210 case 2: 211 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; 212 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); 213 break; 214 } 215 } 216 217 struct vcores_data beagle_x15_volts = { 218 .mpu.value = VDD_MPU_DRA752, 219 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, 220 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 221 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 222 .mpu.pmic = &tps659038, 223 224 .eve.value = VDD_EVE_DRA752, 225 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 226 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 227 .eve.addr = TPS659038_REG_ADDR_SMPS45, 228 .eve.pmic = &tps659038, 229 230 .gpu.value = VDD_GPU_DRA752, 231 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, 232 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 233 .gpu.addr = TPS659038_REG_ADDR_SMPS45, 234 .gpu.pmic = &tps659038, 235 236 .core.value = VDD_CORE_DRA752, 237 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, 238 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 239 .core.addr = TPS659038_REG_ADDR_SMPS6, 240 .core.pmic = &tps659038, 241 242 .iva.value = VDD_IVA_DRA752, 243 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, 244 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 245 .iva.addr = TPS659038_REG_ADDR_SMPS45, 246 .iva.pmic = &tps659038, 247 }; 248 249 #ifdef CONFIG_SPL_BUILD 250 /* No env to setup for SPL */ 251 static inline void setup_board_eeprom_env(void) { } 252 253 /* Override function to read eeprom information */ 254 void do_board_detect(void) 255 { 256 int rc; 257 258 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 259 CONFIG_EEPROM_CHIP_ADDRESS); 260 if (rc) 261 printf("ti_i2c_eeprom_init failed %d\n", rc); 262 } 263 264 #else /* CONFIG_SPL_BUILD */ 265 266 /* Override function to read eeprom information: actual i2c read done by SPL*/ 267 void do_board_detect(void) 268 { 269 char *bname = NULL; 270 int rc; 271 272 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 273 CONFIG_EEPROM_CHIP_ADDRESS); 274 if (rc) 275 printf("ti_i2c_eeprom_init failed %d\n", rc); 276 277 if (board_is_x15()) 278 bname = "BeagleBoard X15"; 279 else if (board_is_am572x_evm()) 280 bname = "AM572x EVM"; 281 282 if (bname) 283 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 284 "Board: %s REV %s\n", bname, board_ti_get_rev()); 285 } 286 287 static void setup_board_eeprom_env(void) 288 { 289 char *name = "beagle_x15"; 290 int rc; 291 292 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 293 CONFIG_EEPROM_CHIP_ADDRESS); 294 if (rc) 295 goto invalid_eeprom; 296 297 if (board_is_am572x_evm()) 298 name = "am57xx_evm"; 299 else 300 printf("Unidentified board claims %s in eeprom header\n", 301 board_ti_get_name()); 302 303 invalid_eeprom: 304 set_board_info_env(name); 305 } 306 307 #endif /* CONFIG_SPL_BUILD */ 308 309 void hw_data_init(void) 310 { 311 *prcm = &dra7xx_prcm; 312 *dplls_data = &dra7xx_dplls; 313 *omap_vcores = &beagle_x15_volts; 314 *ctrl = &dra7xx_ctrl; 315 } 316 317 int board_init(void) 318 { 319 gpmc_init(); 320 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 321 322 return 0; 323 } 324 325 int board_late_init(void) 326 { 327 setup_board_eeprom_env(); 328 329 /* 330 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds 331 * This is the POWERHOLD-in-Low behavior. 332 */ 333 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); 334 return 0; 335 } 336 337 void set_muxconf_regs(void) 338 { 339 do_set_mux32((*ctrl)->control_padconf_core_base, 340 early_padconf, ARRAY_SIZE(early_padconf)); 341 } 342 343 #ifdef CONFIG_IODELAY_RECALIBRATION 344 void recalibrate_iodelay(void) 345 { 346 __recalibrate_iodelay(core_padconf_array_essential, 347 ARRAY_SIZE(core_padconf_array_essential), 348 iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array)); 349 } 350 #endif 351 352 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 353 int board_mmc_init(bd_t *bis) 354 { 355 omap_mmc_init(0, 0, 0, -1, -1); 356 omap_mmc_init(1, 0, 0, -1, -1); 357 return 0; 358 } 359 #endif 360 361 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 362 int spl_start_uboot(void) 363 { 364 /* break into full u-boot on 'c' */ 365 if (serial_tstc() && serial_getc() == 'c') 366 return 1; 367 368 #ifdef CONFIG_SPL_ENV_SUPPORT 369 env_init(); 370 env_relocate_spec(); 371 if (getenv_yesno("boot_os") != 1) 372 return 1; 373 #endif 374 375 return 0; 376 } 377 #endif 378 379 #ifdef CONFIG_USB_DWC3 380 static struct dwc3_device usb_otg_ss1 = { 381 .maximum_speed = USB_SPEED_SUPER, 382 .base = DRA7_USB_OTG_SS1_BASE, 383 .tx_fifo_resize = false, 384 .index = 0, 385 }; 386 387 static struct dwc3_omap_device usb_otg_ss1_glue = { 388 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 389 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 390 .index = 0, 391 }; 392 393 static struct ti_usb_phy_device usb_phy1_device = { 394 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 395 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 396 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 397 .index = 0, 398 }; 399 400 static struct dwc3_device usb_otg_ss2 = { 401 .maximum_speed = USB_SPEED_HIGH, 402 .base = DRA7_USB_OTG_SS2_BASE, 403 .tx_fifo_resize = false, 404 .index = 1, 405 }; 406 407 static struct dwc3_omap_device usb_otg_ss2_glue = { 408 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 409 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 410 .index = 1, 411 }; 412 413 static struct ti_usb_phy_device usb_phy2_device = { 414 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 415 .index = 1, 416 }; 417 418 int board_usb_init(int index, enum usb_init_type init) 419 { 420 enable_usb_clocks(index); 421 switch (index) { 422 case 0: 423 if (init == USB_INIT_DEVICE) { 424 printf("port %d can't be used as device\n", index); 425 disable_usb_clocks(index); 426 return -EINVAL; 427 } else { 428 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 429 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 430 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 431 OTG_SS_CLKCTRL_MODULEMODE_HW | 432 OPTFCLKEN_REFCLK960M); 433 } 434 435 ti_usb_phy_uboot_init(&usb_phy1_device); 436 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 437 dwc3_uboot_init(&usb_otg_ss1); 438 break; 439 case 1: 440 if (init == USB_INIT_DEVICE) { 441 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 442 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 443 } else { 444 printf("port %d can't be used as host\n", index); 445 disable_usb_clocks(index); 446 return -EINVAL; 447 } 448 449 ti_usb_phy_uboot_init(&usb_phy2_device); 450 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 451 dwc3_uboot_init(&usb_otg_ss2); 452 break; 453 default: 454 printf("Invalid Controller Index\n"); 455 } 456 457 return 0; 458 } 459 460 int board_usb_cleanup(int index, enum usb_init_type init) 461 { 462 switch (index) { 463 case 0: 464 case 1: 465 ti_usb_phy_uboot_exit(index); 466 dwc3_uboot_exit(index); 467 dwc3_omap_uboot_exit(index); 468 break; 469 default: 470 printf("Invalid Controller Index\n"); 471 } 472 disable_usb_clocks(index); 473 return 0; 474 } 475 476 int usb_gadget_handle_interrupts(int index) 477 { 478 u32 status; 479 480 status = dwc3_omap_uboot_interrupt_status(index); 481 if (status) 482 dwc3_uboot_handle_interrupt(index); 483 484 return 0; 485 } 486 #endif 487 488 #ifdef CONFIG_DRIVER_TI_CPSW 489 490 /* Delay value to add to calibrated value */ 491 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 492 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 493 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 494 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 495 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 496 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 497 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 498 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 499 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 500 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 501 502 static void cpsw_control(int enabled) 503 { 504 /* VTP can be added here */ 505 } 506 507 static struct cpsw_slave_data cpsw_slaves[] = { 508 { 509 .slave_reg_ofs = 0x208, 510 .sliver_reg_ofs = 0xd80, 511 .phy_addr = 1, 512 }, 513 { 514 .slave_reg_ofs = 0x308, 515 .sliver_reg_ofs = 0xdc0, 516 .phy_addr = 2, 517 }, 518 }; 519 520 static struct cpsw_platform_data cpsw_data = { 521 .mdio_base = CPSW_MDIO_BASE, 522 .cpsw_base = CPSW_BASE, 523 .mdio_div = 0xff, 524 .channels = 8, 525 .cpdma_reg_ofs = 0x800, 526 .slaves = 1, 527 .slave_data = cpsw_slaves, 528 .ale_reg_ofs = 0xd00, 529 .ale_entries = 1024, 530 .host_port_reg_ofs = 0x108, 531 .hw_stats_reg_ofs = 0x900, 532 .bd_ram_ofs = 0x2000, 533 .mac_control = (1 << 5), 534 .control = cpsw_control, 535 .host_port_num = 0, 536 .version = CPSW_CTRL_VERSION_2, 537 }; 538 539 static u64 mac_to_u64(u8 mac[6]) 540 { 541 int i; 542 u64 addr = 0; 543 544 for (i = 0; i < 6; i++) { 545 addr <<= 8; 546 addr |= mac[i]; 547 } 548 549 return addr; 550 } 551 552 static void u64_to_mac(u64 addr, u8 mac[6]) 553 { 554 mac[5] = addr; 555 mac[4] = addr >> 8; 556 mac[3] = addr >> 16; 557 mac[2] = addr >> 24; 558 mac[1] = addr >> 32; 559 mac[0] = addr >> 40; 560 } 561 562 int board_eth_init(bd_t *bis) 563 { 564 int ret; 565 uint8_t mac_addr[6]; 566 uint32_t mac_hi, mac_lo; 567 uint32_t ctrl_val; 568 int i; 569 u64 mac1, mac2; 570 u8 mac_addr1[6], mac_addr2[6]; 571 int num_macs; 572 573 /* try reading mac address from efuse */ 574 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 575 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 576 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 577 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 578 mac_addr[2] = mac_hi & 0xFF; 579 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 580 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 581 mac_addr[5] = mac_lo & 0xFF; 582 583 if (!getenv("ethaddr")) { 584 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 585 586 if (is_valid_ethaddr(mac_addr)) 587 eth_setenv_enetaddr("ethaddr", mac_addr); 588 } 589 590 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 591 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 592 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 593 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 594 mac_addr[2] = mac_hi & 0xFF; 595 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 596 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 597 mac_addr[5] = mac_lo & 0xFF; 598 599 if (!getenv("eth1addr")) { 600 if (is_valid_ethaddr(mac_addr)) 601 eth_setenv_enetaddr("eth1addr", mac_addr); 602 } 603 604 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 605 ctrl_val |= 0x22; 606 writel(ctrl_val, (*ctrl)->control_core_control_io1); 607 608 ret = cpsw_register(&cpsw_data); 609 if (ret < 0) 610 printf("Error %d registering CPSW switch\n", ret); 611 612 /* 613 * Export any Ethernet MAC addresses from EEPROM. 614 * On AM57xx the 2 MAC addresses define the address range 615 */ 616 board_ti_get_eth_mac_addr(0, mac_addr1); 617 board_ti_get_eth_mac_addr(1, mac_addr2); 618 619 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { 620 mac1 = mac_to_u64(mac_addr1); 621 mac2 = mac_to_u64(mac_addr2); 622 623 /* must contain an address range */ 624 num_macs = mac2 - mac1 + 1; 625 /* <= 50 to protect against user programming error */ 626 if (num_macs > 0 && num_macs <= 50) { 627 for (i = 0; i < num_macs; i++) { 628 u64_to_mac(mac1 + i, mac_addr); 629 if (is_valid_ethaddr(mac_addr)) { 630 eth_setenv_enetaddr_by_index("eth", 631 i + 2, 632 mac_addr); 633 } 634 } 635 } 636 } 637 638 return ret; 639 } 640 #endif 641 642 #ifdef CONFIG_BOARD_EARLY_INIT_F 643 /* VTT regulator enable */ 644 static inline void vtt_regulator_enable(void) 645 { 646 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 647 return; 648 649 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 650 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 651 } 652 653 int board_early_init_f(void) 654 { 655 vtt_regulator_enable(); 656 return 0; 657 } 658 #endif 659