1 /* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com 3 * 4 * Author: Felipe Balbi <balbi@ti.com> 5 * 6 * Based on board/ti/dra7xx/evm.c 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <palmas.h> 13 #include <sata.h> 14 #include <usb.h> 15 #include <asm/omap_common.h> 16 #include <asm/emif.h> 17 #include <asm/gpio.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/dra7xx_iodelay.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/sata.h> 24 #include <asm/arch/gpio.h> 25 #include <asm/arch/omap.h> 26 #include <environment.h> 27 #include <usb.h> 28 #include <linux/usb/gadget.h> 29 #include <dwc3-uboot.h> 30 #include <dwc3-omap-uboot.h> 31 #include <ti-usb-phy-uboot.h> 32 33 #include "../common/board_detect.h" 34 #include "mux_data.h" 35 36 #define board_is_x15() board_ti_is("BBRDX15_") 37 #define board_is_am572x_evm() board_ti_is("AM572PM_") 38 #define board_is_am572x_idk() board_ti_is("AM572IDK") 39 40 #ifdef CONFIG_DRIVER_TI_CPSW 41 #include <cpsw.h> 42 #endif 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 /* GPIO 7_11 */ 47 #define GPIO_DDR_VTT_EN 203 48 49 #define SYSINFO_BOARD_NAME_MAX_LEN 45 50 51 const struct omap_sysinfo sysinfo = { 52 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n" 53 }; 54 55 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { 56 .dmm_lisa_map_3 = 0x80740300, 57 .is_ma_present = 0x1 58 }; 59 60 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 61 { 62 *dmm_lisa_regs = &beagle_x15_lisa_regs; 63 } 64 65 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { 66 .sdram_config_init = 0x61851b32, 67 .sdram_config = 0x61851b32, 68 .sdram_config2 = 0x08000000, 69 .ref_ctrl = 0x000040F1, 70 .ref_ctrl_final = 0x00001035, 71 .sdram_tim1 = 0xcccf36ab, 72 .sdram_tim2 = 0x308f7fda, 73 .sdram_tim3 = 0x409f88a8, 74 .read_idle_ctrl = 0x00050000, 75 .zq_config = 0x5007190b, 76 .temp_alert_config = 0x00000000, 77 .emif_ddr_phy_ctlr_1_init = 0x0024400b, 78 .emif_ddr_phy_ctlr_1 = 0x0e24400b, 79 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 80 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 81 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 82 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 83 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 84 .emif_rd_wr_lvl_rmp_win = 0x00000000, 85 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 86 .emif_rd_wr_lvl_ctl = 0x00000000, 87 .emif_rd_wr_exec_thresh = 0x00000305 88 }; 89 90 /* Ext phy ctrl regs 1-35 */ 91 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 92 0x10040100, 93 0x00910091, 94 0x00950095, 95 0x009B009B, 96 0x009E009E, 97 0x00980098, 98 0x00340034, 99 0x00350035, 100 0x00340034, 101 0x00310031, 102 0x00340034, 103 0x007F007F, 104 0x007F007F, 105 0x007F007F, 106 0x007F007F, 107 0x007F007F, 108 0x00480048, 109 0x004A004A, 110 0x00520052, 111 0x00550055, 112 0x00500050, 113 0x00000000, 114 0x00600020, 115 0x40011080, 116 0x08102040, 117 0x0, 118 0x0, 119 0x0, 120 0x0, 121 0x0, 122 0x0, 123 0x0, 124 0x0, 125 0x0, 126 0x0 127 }; 128 129 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { 130 .sdram_config_init = 0x61851b32, 131 .sdram_config = 0x61851b32, 132 .sdram_config2 = 0x08000000, 133 .ref_ctrl = 0x000040F1, 134 .ref_ctrl_final = 0x00001035, 135 .sdram_tim1 = 0xcccf36b3, 136 .sdram_tim2 = 0x308f7fda, 137 .sdram_tim3 = 0x407f88a8, 138 .read_idle_ctrl = 0x00050000, 139 .zq_config = 0x5007190b, 140 .temp_alert_config = 0x00000000, 141 .emif_ddr_phy_ctlr_1_init = 0x0024400b, 142 .emif_ddr_phy_ctlr_1 = 0x0e24400b, 143 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 144 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 145 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 146 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 147 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 148 .emif_rd_wr_lvl_rmp_win = 0x00000000, 149 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 150 .emif_rd_wr_lvl_ctl = 0x00000000, 151 .emif_rd_wr_exec_thresh = 0x00000305 152 }; 153 154 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 155 0x10040100, 156 0x00910091, 157 0x00950095, 158 0x009B009B, 159 0x009E009E, 160 0x00980098, 161 0x00340034, 162 0x00350035, 163 0x00340034, 164 0x00310031, 165 0x00340034, 166 0x007F007F, 167 0x007F007F, 168 0x007F007F, 169 0x007F007F, 170 0x007F007F, 171 0x00480048, 172 0x004A004A, 173 0x00520052, 174 0x00550055, 175 0x00500050, 176 0x00000000, 177 0x00600020, 178 0x40011080, 179 0x08102040, 180 0x0, 181 0x0, 182 0x0, 183 0x0, 184 0x0, 185 0x0, 186 0x0, 187 0x0, 188 0x0, 189 0x0 190 }; 191 192 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 193 { 194 switch (emif_nr) { 195 case 1: 196 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; 197 break; 198 case 2: 199 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; 200 break; 201 } 202 } 203 204 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) 205 { 206 switch (emif_nr) { 207 case 1: 208 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; 209 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); 210 break; 211 case 2: 212 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; 213 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); 214 break; 215 } 216 } 217 218 struct vcores_data beagle_x15_volts = { 219 .mpu.value = VDD_MPU_DRA752, 220 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, 221 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 222 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 223 .mpu.pmic = &tps659038, 224 225 .eve.value = VDD_EVE_DRA752, 226 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 227 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 228 .eve.addr = TPS659038_REG_ADDR_SMPS45, 229 .eve.pmic = &tps659038, 230 231 .gpu.value = VDD_GPU_DRA752, 232 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, 233 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 234 .gpu.addr = TPS659038_REG_ADDR_SMPS45, 235 .gpu.pmic = &tps659038, 236 237 .core.value = VDD_CORE_DRA752, 238 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, 239 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 240 .core.addr = TPS659038_REG_ADDR_SMPS6, 241 .core.pmic = &tps659038, 242 243 .iva.value = VDD_IVA_DRA752, 244 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, 245 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 246 .iva.addr = TPS659038_REG_ADDR_SMPS45, 247 .iva.pmic = &tps659038, 248 }; 249 250 #ifdef CONFIG_SPL_BUILD 251 /* No env to setup for SPL */ 252 static inline void setup_board_eeprom_env(void) { } 253 254 /* Override function to read eeprom information */ 255 void do_board_detect(void) 256 { 257 int rc; 258 259 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 260 CONFIG_EEPROM_CHIP_ADDRESS); 261 if (rc) 262 printf("ti_i2c_eeprom_init failed %d\n", rc); 263 } 264 265 #else /* CONFIG_SPL_BUILD */ 266 267 /* Override function to read eeprom information: actual i2c read done by SPL*/ 268 void do_board_detect(void) 269 { 270 char *bname = NULL; 271 int rc; 272 273 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 274 CONFIG_EEPROM_CHIP_ADDRESS); 275 if (rc) 276 printf("ti_i2c_eeprom_init failed %d\n", rc); 277 278 if (board_is_x15()) 279 bname = "BeagleBoard X15"; 280 else if (board_is_am572x_evm()) 281 bname = "AM572x EVM"; 282 else if (board_is_am572x_idk()) 283 bname = "AM572x IDK"; 284 285 if (bname) 286 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 287 "Board: %s REV %s\n", bname, board_ti_get_rev()); 288 } 289 290 static void setup_board_eeprom_env(void) 291 { 292 char *name = "beagle_x15"; 293 int rc; 294 295 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 296 CONFIG_EEPROM_CHIP_ADDRESS); 297 if (rc) 298 goto invalid_eeprom; 299 300 if (board_is_am572x_evm()) 301 name = "am57xx_evm"; 302 else if (board_is_am572x_idk()) 303 name = "am572x_idk"; 304 else 305 printf("Unidentified board claims %s in eeprom header\n", 306 board_ti_get_name()); 307 308 invalid_eeprom: 309 set_board_info_env(name); 310 } 311 312 #endif /* CONFIG_SPL_BUILD */ 313 314 void hw_data_init(void) 315 { 316 *prcm = &dra7xx_prcm; 317 *dplls_data = &dra7xx_dplls; 318 *omap_vcores = &beagle_x15_volts; 319 *ctrl = &dra7xx_ctrl; 320 } 321 322 int board_init(void) 323 { 324 gpmc_init(); 325 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 326 327 return 0; 328 } 329 330 int board_late_init(void) 331 { 332 setup_board_eeprom_env(); 333 334 /* 335 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds 336 * This is the POWERHOLD-in-Low behavior. 337 */ 338 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); 339 return 0; 340 } 341 342 void set_muxconf_regs(void) 343 { 344 do_set_mux32((*ctrl)->control_padconf_core_base, 345 early_padconf, ARRAY_SIZE(early_padconf)); 346 } 347 348 #ifdef CONFIG_IODELAY_RECALIBRATION 349 void recalibrate_iodelay(void) 350 { 351 const struct pad_conf_entry *pconf; 352 const struct iodelay_cfg_entry *iod; 353 int pconf_sz, iod_sz; 354 355 if (board_is_am572x_idk()) { 356 pconf = core_padconf_array_essential_am572x_idk; 357 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); 358 iod = iodelay_cfg_array_am572x_idk; 359 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk); 360 } else { 361 /* Common for X15/GPEVM */ 362 pconf = core_padconf_array_essential_x15; 363 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15); 364 iod = iodelay_cfg_array_x15; 365 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15); 366 } 367 368 __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz); 369 } 370 #endif 371 372 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 373 int board_mmc_init(bd_t *bis) 374 { 375 omap_mmc_init(0, 0, 0, -1, -1); 376 omap_mmc_init(1, 0, 0, -1, -1); 377 return 0; 378 } 379 #endif 380 381 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 382 int spl_start_uboot(void) 383 { 384 /* break into full u-boot on 'c' */ 385 if (serial_tstc() && serial_getc() == 'c') 386 return 1; 387 388 #ifdef CONFIG_SPL_ENV_SUPPORT 389 env_init(); 390 env_relocate_spec(); 391 if (getenv_yesno("boot_os") != 1) 392 return 1; 393 #endif 394 395 return 0; 396 } 397 #endif 398 399 #ifdef CONFIG_USB_DWC3 400 static struct dwc3_device usb_otg_ss1 = { 401 .maximum_speed = USB_SPEED_SUPER, 402 .base = DRA7_USB_OTG_SS1_BASE, 403 .tx_fifo_resize = false, 404 .index = 0, 405 }; 406 407 static struct dwc3_omap_device usb_otg_ss1_glue = { 408 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 409 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 410 .index = 0, 411 }; 412 413 static struct ti_usb_phy_device usb_phy1_device = { 414 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 415 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 416 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 417 .index = 0, 418 }; 419 420 static struct dwc3_device usb_otg_ss2 = { 421 .maximum_speed = USB_SPEED_HIGH, 422 .base = DRA7_USB_OTG_SS2_BASE, 423 .tx_fifo_resize = false, 424 .index = 1, 425 }; 426 427 static struct dwc3_omap_device usb_otg_ss2_glue = { 428 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 429 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 430 .index = 1, 431 }; 432 433 static struct ti_usb_phy_device usb_phy2_device = { 434 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 435 .index = 1, 436 }; 437 438 int board_usb_init(int index, enum usb_init_type init) 439 { 440 enable_usb_clocks(index); 441 switch (index) { 442 case 0: 443 if (init == USB_INIT_DEVICE) { 444 printf("port %d can't be used as device\n", index); 445 disable_usb_clocks(index); 446 return -EINVAL; 447 } else { 448 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 449 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 450 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 451 OTG_SS_CLKCTRL_MODULEMODE_HW | 452 OPTFCLKEN_REFCLK960M); 453 } 454 455 ti_usb_phy_uboot_init(&usb_phy1_device); 456 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 457 dwc3_uboot_init(&usb_otg_ss1); 458 break; 459 case 1: 460 if (init == USB_INIT_DEVICE) { 461 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 462 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 463 } else { 464 printf("port %d can't be used as host\n", index); 465 disable_usb_clocks(index); 466 return -EINVAL; 467 } 468 469 ti_usb_phy_uboot_init(&usb_phy2_device); 470 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 471 dwc3_uboot_init(&usb_otg_ss2); 472 break; 473 default: 474 printf("Invalid Controller Index\n"); 475 } 476 477 return 0; 478 } 479 480 int board_usb_cleanup(int index, enum usb_init_type init) 481 { 482 switch (index) { 483 case 0: 484 case 1: 485 ti_usb_phy_uboot_exit(index); 486 dwc3_uboot_exit(index); 487 dwc3_omap_uboot_exit(index); 488 break; 489 default: 490 printf("Invalid Controller Index\n"); 491 } 492 disable_usb_clocks(index); 493 return 0; 494 } 495 496 int usb_gadget_handle_interrupts(int index) 497 { 498 u32 status; 499 500 status = dwc3_omap_uboot_interrupt_status(index); 501 if (status) 502 dwc3_uboot_handle_interrupt(index); 503 504 return 0; 505 } 506 #endif 507 508 #ifdef CONFIG_DRIVER_TI_CPSW 509 510 /* Delay value to add to calibrated value */ 511 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 512 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 513 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 514 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 515 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 516 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 517 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 518 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 519 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 520 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 521 522 static void cpsw_control(int enabled) 523 { 524 /* VTP can be added here */ 525 } 526 527 static struct cpsw_slave_data cpsw_slaves[] = { 528 { 529 .slave_reg_ofs = 0x208, 530 .sliver_reg_ofs = 0xd80, 531 .phy_addr = 1, 532 }, 533 { 534 .slave_reg_ofs = 0x308, 535 .sliver_reg_ofs = 0xdc0, 536 .phy_addr = 2, 537 }, 538 }; 539 540 static struct cpsw_platform_data cpsw_data = { 541 .mdio_base = CPSW_MDIO_BASE, 542 .cpsw_base = CPSW_BASE, 543 .mdio_div = 0xff, 544 .channels = 8, 545 .cpdma_reg_ofs = 0x800, 546 .slaves = 1, 547 .slave_data = cpsw_slaves, 548 .ale_reg_ofs = 0xd00, 549 .ale_entries = 1024, 550 .host_port_reg_ofs = 0x108, 551 .hw_stats_reg_ofs = 0x900, 552 .bd_ram_ofs = 0x2000, 553 .mac_control = (1 << 5), 554 .control = cpsw_control, 555 .host_port_num = 0, 556 .version = CPSW_CTRL_VERSION_2, 557 }; 558 559 static u64 mac_to_u64(u8 mac[6]) 560 { 561 int i; 562 u64 addr = 0; 563 564 for (i = 0; i < 6; i++) { 565 addr <<= 8; 566 addr |= mac[i]; 567 } 568 569 return addr; 570 } 571 572 static void u64_to_mac(u64 addr, u8 mac[6]) 573 { 574 mac[5] = addr; 575 mac[4] = addr >> 8; 576 mac[3] = addr >> 16; 577 mac[2] = addr >> 24; 578 mac[1] = addr >> 32; 579 mac[0] = addr >> 40; 580 } 581 582 int board_eth_init(bd_t *bis) 583 { 584 int ret; 585 uint8_t mac_addr[6]; 586 uint32_t mac_hi, mac_lo; 587 uint32_t ctrl_val; 588 int i; 589 u64 mac1, mac2; 590 u8 mac_addr1[6], mac_addr2[6]; 591 int num_macs; 592 593 /* try reading mac address from efuse */ 594 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 595 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 596 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 597 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 598 mac_addr[2] = mac_hi & 0xFF; 599 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 600 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 601 mac_addr[5] = mac_lo & 0xFF; 602 603 if (!getenv("ethaddr")) { 604 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 605 606 if (is_valid_ethaddr(mac_addr)) 607 eth_setenv_enetaddr("ethaddr", mac_addr); 608 } 609 610 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 611 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 612 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 613 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 614 mac_addr[2] = mac_hi & 0xFF; 615 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 616 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 617 mac_addr[5] = mac_lo & 0xFF; 618 619 if (!getenv("eth1addr")) { 620 if (is_valid_ethaddr(mac_addr)) 621 eth_setenv_enetaddr("eth1addr", mac_addr); 622 } 623 624 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 625 ctrl_val |= 0x22; 626 writel(ctrl_val, (*ctrl)->control_core_control_io1); 627 628 /* The phy address for the AM572x IDK are different than x15 */ 629 if (board_is_am572x_idk()) { 630 cpsw_data.slave_data[0].phy_addr = 0; 631 cpsw_data.slave_data[1].phy_addr = 1; 632 } 633 634 ret = cpsw_register(&cpsw_data); 635 if (ret < 0) 636 printf("Error %d registering CPSW switch\n", ret); 637 638 /* 639 * Export any Ethernet MAC addresses from EEPROM. 640 * On AM57xx the 2 MAC addresses define the address range 641 */ 642 board_ti_get_eth_mac_addr(0, mac_addr1); 643 board_ti_get_eth_mac_addr(1, mac_addr2); 644 645 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { 646 mac1 = mac_to_u64(mac_addr1); 647 mac2 = mac_to_u64(mac_addr2); 648 649 /* must contain an address range */ 650 num_macs = mac2 - mac1 + 1; 651 /* <= 50 to protect against user programming error */ 652 if (num_macs > 0 && num_macs <= 50) { 653 for (i = 0; i < num_macs; i++) { 654 u64_to_mac(mac1 + i, mac_addr); 655 if (is_valid_ethaddr(mac_addr)) { 656 eth_setenv_enetaddr_by_index("eth", 657 i + 2, 658 mac_addr); 659 } 660 } 661 } 662 } 663 664 return ret; 665 } 666 #endif 667 668 #ifdef CONFIG_BOARD_EARLY_INIT_F 669 /* VTT regulator enable */ 670 static inline void vtt_regulator_enable(void) 671 { 672 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 673 return; 674 675 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 676 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 677 } 678 679 int board_early_init_f(void) 680 { 681 vtt_regulator_enable(); 682 return 0; 683 } 684 #endif 685