1 /* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com 3 * 4 * Author: Felipe Balbi <balbi@ti.com> 5 * 6 * Based on board/ti/dra7xx/evm.c 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <palmas.h> 13 #include <sata.h> 14 #include <usb.h> 15 #include <asm/omap_common.h> 16 #include <asm/omap_sec_common.h> 17 #include <asm/emif.h> 18 #include <asm/gpio.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/dra7xx_iodelay.h> 22 #include <asm/arch/sys_proto.h> 23 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/sata.h> 25 #include <asm/arch/gpio.h> 26 #include <asm/arch/omap.h> 27 #include <environment.h> 28 #include <usb.h> 29 #include <linux/usb/gadget.h> 30 #include <dwc3-uboot.h> 31 #include <dwc3-omap-uboot.h> 32 #include <ti-usb-phy-uboot.h> 33 34 #include "../common/board_detect.h" 35 #include "mux_data.h" 36 37 #define board_is_x15() board_ti_is("BBRDX15_") 38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \ 39 (strncmp("B.10", board_ti_get_rev(), 3) <= 0)) 40 #define board_is_am572x_evm() board_ti_is("AM572PM_") 41 #define board_is_am572x_evm_reva3() \ 42 (board_ti_is("AM572PM_") && \ 43 (strncmp("A.30", board_ti_get_rev(), 3) <= 0)) 44 #define board_is_am572x_idk() board_ti_is("AM572IDK") 45 #define board_is_am571x_idk() board_ti_is("AM571IDK") 46 47 #ifdef CONFIG_DRIVER_TI_CPSW 48 #include <cpsw.h> 49 #endif 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 /* GPIO 7_11 */ 54 #define GPIO_DDR_VTT_EN 203 55 56 #define SYSINFO_BOARD_NAME_MAX_LEN 45 57 58 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB 59 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20 60 61 const struct omap_sysinfo sysinfo = { 62 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n" 63 }; 64 65 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { 66 .dmm_lisa_map_3 = 0x80740300, 67 .is_ma_present = 0x1 68 }; 69 70 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { 71 .dmm_lisa_map_3 = 0x80640100, 72 .is_ma_present = 0x1 73 }; 74 75 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 76 { 77 if (board_is_am571x_idk()) 78 *dmm_lisa_regs = &am571x_idk_lisa_regs; 79 else 80 *dmm_lisa_regs = &beagle_x15_lisa_regs; 81 } 82 83 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { 84 .sdram_config_init = 0x61851b32, 85 .sdram_config = 0x61851b32, 86 .sdram_config2 = 0x08000000, 87 .ref_ctrl = 0x000040F1, 88 .ref_ctrl_final = 0x00001035, 89 .sdram_tim1 = 0xcccf36ab, 90 .sdram_tim2 = 0x308f7fda, 91 .sdram_tim3 = 0x409f88a8, 92 .read_idle_ctrl = 0x00050000, 93 .zq_config = 0x5007190b, 94 .temp_alert_config = 0x00000000, 95 .emif_ddr_phy_ctlr_1_init = 0x0024400b, 96 .emif_ddr_phy_ctlr_1 = 0x0e24400b, 97 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 98 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 99 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 100 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 101 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 102 .emif_rd_wr_lvl_rmp_win = 0x00000000, 103 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 104 .emif_rd_wr_lvl_ctl = 0x00000000, 105 .emif_rd_wr_exec_thresh = 0x00000305 106 }; 107 108 /* Ext phy ctrl regs 1-35 */ 109 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 110 0x10040100, 111 0x00910091, 112 0x00950095, 113 0x009B009B, 114 0x009E009E, 115 0x00980098, 116 0x00340034, 117 0x00350035, 118 0x00340034, 119 0x00310031, 120 0x00340034, 121 0x007F007F, 122 0x007F007F, 123 0x007F007F, 124 0x007F007F, 125 0x007F007F, 126 0x00480048, 127 0x004A004A, 128 0x00520052, 129 0x00550055, 130 0x00500050, 131 0x00000000, 132 0x00600020, 133 0x40011080, 134 0x08102040, 135 0x0, 136 0x0, 137 0x0, 138 0x0, 139 0x0, 140 0x0, 141 0x0, 142 0x0, 143 0x0, 144 0x0 145 }; 146 147 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { 148 .sdram_config_init = 0x61851b32, 149 .sdram_config = 0x61851b32, 150 .sdram_config2 = 0x08000000, 151 .ref_ctrl = 0x000040F1, 152 .ref_ctrl_final = 0x00001035, 153 .sdram_tim1 = 0xcccf36b3, 154 .sdram_tim2 = 0x308f7fda, 155 .sdram_tim3 = 0x407f88a8, 156 .read_idle_ctrl = 0x00050000, 157 .zq_config = 0x5007190b, 158 .temp_alert_config = 0x00000000, 159 .emif_ddr_phy_ctlr_1_init = 0x0024400b, 160 .emif_ddr_phy_ctlr_1 = 0x0e24400b, 161 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 162 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 163 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 164 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 165 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 166 .emif_rd_wr_lvl_rmp_win = 0x00000000, 167 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 168 .emif_rd_wr_lvl_ctl = 0x00000000, 169 .emif_rd_wr_exec_thresh = 0x00000305 170 }; 171 172 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 173 0x10040100, 174 0x00910091, 175 0x00950095, 176 0x009B009B, 177 0x009E009E, 178 0x00980098, 179 0x00340034, 180 0x00350035, 181 0x00340034, 182 0x00310031, 183 0x00340034, 184 0x007F007F, 185 0x007F007F, 186 0x007F007F, 187 0x007F007F, 188 0x007F007F, 189 0x00480048, 190 0x004A004A, 191 0x00520052, 192 0x00550055, 193 0x00500050, 194 0x00000000, 195 0x00600020, 196 0x40011080, 197 0x08102040, 198 0x0, 199 0x0, 200 0x0, 201 0x0, 202 0x0, 203 0x0, 204 0x0, 205 0x0, 206 0x0, 207 0x0 208 }; 209 210 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 211 { 212 switch (emif_nr) { 213 case 1: 214 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; 215 break; 216 case 2: 217 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; 218 break; 219 } 220 } 221 222 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) 223 { 224 switch (emif_nr) { 225 case 1: 226 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; 227 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); 228 break; 229 case 2: 230 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; 231 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); 232 break; 233 } 234 } 235 236 struct vcores_data beagle_x15_volts = { 237 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 238 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 239 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 240 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 241 .mpu.pmic = &tps659038, 242 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 243 244 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 245 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 246 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 247 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 248 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 249 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 250 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 251 .eve.addr = TPS659038_REG_ADDR_SMPS45, 252 .eve.pmic = &tps659038, 253 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 254 255 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 256 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 257 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 258 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 259 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 260 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 261 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 262 .gpu.addr = TPS659038_REG_ADDR_SMPS45, 263 .gpu.pmic = &tps659038, 264 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 265 266 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 267 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 268 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 269 .core.addr = TPS659038_REG_ADDR_SMPS6, 270 .core.pmic = &tps659038, 271 272 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 273 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 274 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 275 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 276 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 277 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 278 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 279 .iva.addr = TPS659038_REG_ADDR_SMPS45, 280 .iva.pmic = &tps659038, 281 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 282 }; 283 284 struct vcores_data am572x_idk_volts = { 285 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 286 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 287 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 288 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 289 .mpu.pmic = &tps659038, 290 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 291 292 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 293 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 294 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 295 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 296 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 297 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 298 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 299 .eve.addr = TPS659038_REG_ADDR_SMPS45, 300 .eve.pmic = &tps659038, 301 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 302 303 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 304 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 305 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 306 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 307 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 308 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 309 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 310 .gpu.addr = TPS659038_REG_ADDR_SMPS6, 311 .gpu.pmic = &tps659038, 312 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 313 314 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 315 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 316 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 317 .core.addr = TPS659038_REG_ADDR_SMPS7, 318 .core.pmic = &tps659038, 319 320 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 321 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 322 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 323 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 324 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 325 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 326 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 327 .iva.addr = TPS659038_REG_ADDR_SMPS8, 328 .iva.pmic = &tps659038, 329 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 330 }; 331 332 int get_voltrail_opp(int rail_offset) 333 { 334 int opp; 335 336 switch (rail_offset) { 337 case VOLT_MPU: 338 opp = DRA7_MPU_OPP; 339 break; 340 case VOLT_CORE: 341 opp = DRA7_CORE_OPP; 342 break; 343 case VOLT_GPU: 344 opp = DRA7_GPU_OPP; 345 break; 346 case VOLT_EVE: 347 opp = DRA7_DSPEVE_OPP; 348 break; 349 case VOLT_IVA: 350 opp = DRA7_IVA_OPP; 351 break; 352 default: 353 opp = OPP_NOM; 354 } 355 356 return opp; 357 } 358 359 360 #ifdef CONFIG_SPL_BUILD 361 /* No env to setup for SPL */ 362 static inline void setup_board_eeprom_env(void) { } 363 364 /* Override function to read eeprom information */ 365 void do_board_detect(void) 366 { 367 int rc; 368 369 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 370 CONFIG_EEPROM_CHIP_ADDRESS); 371 if (rc) 372 printf("ti_i2c_eeprom_init failed %d\n", rc); 373 } 374 375 #else /* CONFIG_SPL_BUILD */ 376 377 /* Override function to read eeprom information: actual i2c read done by SPL*/ 378 void do_board_detect(void) 379 { 380 char *bname = NULL; 381 int rc; 382 383 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 384 CONFIG_EEPROM_CHIP_ADDRESS); 385 if (rc) 386 printf("ti_i2c_eeprom_init failed %d\n", rc); 387 388 if (board_is_x15()) 389 bname = "BeagleBoard X15"; 390 else if (board_is_am572x_evm()) 391 bname = "AM572x EVM"; 392 else if (board_is_am572x_idk()) 393 bname = "AM572x IDK"; 394 else if (board_is_am571x_idk()) 395 bname = "AM571x IDK"; 396 397 if (bname) 398 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 399 "Board: %s REV %s\n", bname, board_ti_get_rev()); 400 } 401 402 static void setup_board_eeprom_env(void) 403 { 404 char *name = "beagle_x15"; 405 int rc; 406 407 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 408 CONFIG_EEPROM_CHIP_ADDRESS); 409 if (rc) 410 goto invalid_eeprom; 411 412 if (board_is_x15()) { 413 if (board_is_x15_revb1()) 414 name = "beagle_x15_revb1"; 415 else 416 name = "beagle_x15"; 417 } else if (board_is_am572x_evm()) { 418 if (board_is_am572x_evm_reva3()) 419 name = "am57xx_evm_reva3"; 420 else 421 name = "am57xx_evm"; 422 } else if (board_is_am572x_idk()) { 423 name = "am572x_idk"; 424 } else if (board_is_am571x_idk()) { 425 name = "am571x_idk"; 426 } else { 427 printf("Unidentified board claims %s in eeprom header\n", 428 board_ti_get_name()); 429 } 430 431 invalid_eeprom: 432 set_board_info_env(name); 433 } 434 435 #endif /* CONFIG_SPL_BUILD */ 436 437 void vcores_init(void) 438 { 439 if (board_is_am572x_idk()) 440 *omap_vcores = &am572x_idk_volts; 441 else 442 *omap_vcores = &beagle_x15_volts; 443 } 444 445 void hw_data_init(void) 446 { 447 *prcm = &dra7xx_prcm; 448 *dplls_data = &dra7xx_dplls; 449 *ctrl = &dra7xx_ctrl; 450 } 451 452 int board_init(void) 453 { 454 gpmc_init(); 455 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 456 457 return 0; 458 } 459 460 int board_late_init(void) 461 { 462 setup_board_eeprom_env(); 463 u8 val; 464 465 /* 466 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds 467 * This is the POWERHOLD-in-Low behavior. 468 */ 469 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); 470 471 /* 472 * Default FIT boot on HS devices. Non FIT images are not allowed 473 * on HS devices. 474 */ 475 if (get_device_type() == HS_DEVICE) 476 setenv("boot_fit", "1"); 477 478 /* 479 * Set the GPIO7 Pad to POWERHOLD. This has higher priority 480 * over DEV_CTRL.DEV_ON bit. This can be reset in case of 481 * PMIC Power off. So to be on the safer side set it back 482 * to POWERHOLD mode irrespective of the current state. 483 */ 484 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2, 485 &val); 486 val = val | TPS65903X_PAD2_POWERHOLD_MASK; 487 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2, 488 val); 489 490 omap_die_id_serial(); 491 492 return 0; 493 } 494 495 void set_muxconf_regs(void) 496 { 497 do_set_mux32((*ctrl)->control_padconf_core_base, 498 early_padconf, ARRAY_SIZE(early_padconf)); 499 } 500 501 #ifdef CONFIG_IODELAY_RECALIBRATION 502 void recalibrate_iodelay(void) 503 { 504 const struct pad_conf_entry *pconf; 505 const struct iodelay_cfg_entry *iod; 506 int pconf_sz, iod_sz; 507 int ret; 508 509 if (board_is_am572x_idk()) { 510 pconf = core_padconf_array_essential_am572x_idk; 511 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); 512 iod = iodelay_cfg_array_am572x_idk; 513 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk); 514 } else if (board_is_am571x_idk()) { 515 pconf = core_padconf_array_essential_am571x_idk; 516 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk); 517 iod = iodelay_cfg_array_am571x_idk; 518 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk); 519 } else { 520 /* Common for X15/GPEVM */ 521 pconf = core_padconf_array_essential_x15; 522 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15); 523 /* There never was an SR1.0 X15.. So.. */ 524 if (omap_revision() == DRA752_ES1_1) { 525 iod = iodelay_cfg_array_x15_sr1_1; 526 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1); 527 } else { 528 /* Since full production should switch to SR2.0 */ 529 iod = iodelay_cfg_array_x15_sr2_0; 530 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0); 531 } 532 } 533 534 /* Setup I/O isolation */ 535 ret = __recalibrate_iodelay_start(); 536 if (ret) 537 goto err; 538 539 /* Do the muxing here */ 540 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); 541 542 /* Now do the weird minor deltas that should be safe */ 543 if (board_is_x15() || board_is_am572x_evm()) { 544 if (board_is_x15_revb1() || board_is_am572x_evm_reva3()) { 545 pconf = core_padconf_array_delta_x15_sr2_0; 546 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0); 547 } else { 548 pconf = core_padconf_array_delta_x15_sr1_1; 549 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1); 550 } 551 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); 552 } 553 554 /* Setup IOdelay configuration */ 555 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz); 556 err: 557 /* Closeup.. remove isolation */ 558 __recalibrate_iodelay_end(ret); 559 } 560 #endif 561 562 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 563 int board_mmc_init(bd_t *bis) 564 { 565 omap_mmc_init(0, 0, 0, -1, -1); 566 omap_mmc_init(1, 0, 0, -1, -1); 567 return 0; 568 } 569 #endif 570 571 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 572 int spl_start_uboot(void) 573 { 574 /* break into full u-boot on 'c' */ 575 if (serial_tstc() && serial_getc() == 'c') 576 return 1; 577 578 #ifdef CONFIG_SPL_ENV_SUPPORT 579 env_init(); 580 env_relocate_spec(); 581 if (getenv_yesno("boot_os") != 1) 582 return 1; 583 #endif 584 585 return 0; 586 } 587 #endif 588 589 #ifdef CONFIG_USB_DWC3 590 static struct dwc3_device usb_otg_ss2 = { 591 .maximum_speed = USB_SPEED_HIGH, 592 .base = DRA7_USB_OTG_SS2_BASE, 593 .tx_fifo_resize = false, 594 .index = 1, 595 }; 596 597 static struct dwc3_omap_device usb_otg_ss2_glue = { 598 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 599 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 600 .index = 1, 601 }; 602 603 static struct ti_usb_phy_device usb_phy2_device = { 604 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 605 .index = 1, 606 }; 607 608 int usb_gadget_handle_interrupts(int index) 609 { 610 u32 status; 611 612 status = dwc3_omap_uboot_interrupt_status(index); 613 if (status) 614 dwc3_uboot_handle_interrupt(index); 615 616 return 0; 617 } 618 #endif /* CONFIG_USB_DWC3 */ 619 620 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 621 int board_usb_init(int index, enum usb_init_type init) 622 { 623 enable_usb_clocks(index); 624 switch (index) { 625 case 0: 626 if (init == USB_INIT_DEVICE) { 627 printf("port %d can't be used as device\n", index); 628 disable_usb_clocks(index); 629 return -EINVAL; 630 } 631 break; 632 case 1: 633 if (init == USB_INIT_DEVICE) { 634 #ifdef CONFIG_USB_DWC3 635 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 636 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 637 ti_usb_phy_uboot_init(&usb_phy2_device); 638 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 639 dwc3_uboot_init(&usb_otg_ss2); 640 #endif 641 } else { 642 printf("port %d can't be used as host\n", index); 643 disable_usb_clocks(index); 644 return -EINVAL; 645 } 646 647 break; 648 default: 649 printf("Invalid Controller Index\n"); 650 } 651 652 return 0; 653 } 654 655 int board_usb_cleanup(int index, enum usb_init_type init) 656 { 657 #ifdef CONFIG_USB_DWC3 658 switch (index) { 659 case 0: 660 case 1: 661 if (init == USB_INIT_DEVICE) { 662 ti_usb_phy_uboot_exit(index); 663 dwc3_uboot_exit(index); 664 dwc3_omap_uboot_exit(index); 665 } 666 break; 667 default: 668 printf("Invalid Controller Index\n"); 669 } 670 #endif 671 disable_usb_clocks(index); 672 return 0; 673 } 674 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 675 676 #ifdef CONFIG_DRIVER_TI_CPSW 677 678 /* Delay value to add to calibrated value */ 679 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 680 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 681 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 682 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 683 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 684 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 685 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 686 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 687 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 688 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 689 690 static void cpsw_control(int enabled) 691 { 692 /* VTP can be added here */ 693 } 694 695 static struct cpsw_slave_data cpsw_slaves[] = { 696 { 697 .slave_reg_ofs = 0x208, 698 .sliver_reg_ofs = 0xd80, 699 .phy_addr = 1, 700 }, 701 { 702 .slave_reg_ofs = 0x308, 703 .sliver_reg_ofs = 0xdc0, 704 .phy_addr = 2, 705 }, 706 }; 707 708 static struct cpsw_platform_data cpsw_data = { 709 .mdio_base = CPSW_MDIO_BASE, 710 .cpsw_base = CPSW_BASE, 711 .mdio_div = 0xff, 712 .channels = 8, 713 .cpdma_reg_ofs = 0x800, 714 .slaves = 1, 715 .slave_data = cpsw_slaves, 716 .ale_reg_ofs = 0xd00, 717 .ale_entries = 1024, 718 .host_port_reg_ofs = 0x108, 719 .hw_stats_reg_ofs = 0x900, 720 .bd_ram_ofs = 0x2000, 721 .mac_control = (1 << 5), 722 .control = cpsw_control, 723 .host_port_num = 0, 724 .version = CPSW_CTRL_VERSION_2, 725 }; 726 727 static u64 mac_to_u64(u8 mac[6]) 728 { 729 int i; 730 u64 addr = 0; 731 732 for (i = 0; i < 6; i++) { 733 addr <<= 8; 734 addr |= mac[i]; 735 } 736 737 return addr; 738 } 739 740 static void u64_to_mac(u64 addr, u8 mac[6]) 741 { 742 mac[5] = addr; 743 mac[4] = addr >> 8; 744 mac[3] = addr >> 16; 745 mac[2] = addr >> 24; 746 mac[1] = addr >> 32; 747 mac[0] = addr >> 40; 748 } 749 750 int board_eth_init(bd_t *bis) 751 { 752 int ret; 753 uint8_t mac_addr[6]; 754 uint32_t mac_hi, mac_lo; 755 uint32_t ctrl_val; 756 int i; 757 u64 mac1, mac2; 758 u8 mac_addr1[6], mac_addr2[6]; 759 int num_macs; 760 761 /* try reading mac address from efuse */ 762 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 763 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 764 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 765 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 766 mac_addr[2] = mac_hi & 0xFF; 767 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 768 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 769 mac_addr[5] = mac_lo & 0xFF; 770 771 if (!getenv("ethaddr")) { 772 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 773 774 if (is_valid_ethaddr(mac_addr)) 775 eth_setenv_enetaddr("ethaddr", mac_addr); 776 } 777 778 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 779 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 780 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 781 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 782 mac_addr[2] = mac_hi & 0xFF; 783 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 784 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 785 mac_addr[5] = mac_lo & 0xFF; 786 787 if (!getenv("eth1addr")) { 788 if (is_valid_ethaddr(mac_addr)) 789 eth_setenv_enetaddr("eth1addr", mac_addr); 790 } 791 792 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 793 ctrl_val |= 0x22; 794 writel(ctrl_val, (*ctrl)->control_core_control_io1); 795 796 /* The phy address for the AM57xx IDK are different than x15 */ 797 if (board_is_am572x_idk() || board_is_am571x_idk()) { 798 cpsw_data.slave_data[0].phy_addr = 0; 799 cpsw_data.slave_data[1].phy_addr = 1; 800 } 801 802 ret = cpsw_register(&cpsw_data); 803 if (ret < 0) 804 printf("Error %d registering CPSW switch\n", ret); 805 806 /* 807 * Export any Ethernet MAC addresses from EEPROM. 808 * On AM57xx the 2 MAC addresses define the address range 809 */ 810 board_ti_get_eth_mac_addr(0, mac_addr1); 811 board_ti_get_eth_mac_addr(1, mac_addr2); 812 813 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { 814 mac1 = mac_to_u64(mac_addr1); 815 mac2 = mac_to_u64(mac_addr2); 816 817 /* must contain an address range */ 818 num_macs = mac2 - mac1 + 1; 819 /* <= 50 to protect against user programming error */ 820 if (num_macs > 0 && num_macs <= 50) { 821 for (i = 0; i < num_macs; i++) { 822 u64_to_mac(mac1 + i, mac_addr); 823 if (is_valid_ethaddr(mac_addr)) { 824 eth_setenv_enetaddr_by_index("eth", 825 i + 2, 826 mac_addr); 827 } 828 } 829 } 830 } 831 832 return ret; 833 } 834 #endif 835 836 #ifdef CONFIG_BOARD_EARLY_INIT_F 837 /* VTT regulator enable */ 838 static inline void vtt_regulator_enable(void) 839 { 840 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 841 return; 842 843 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 844 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 845 } 846 847 int board_early_init_f(void) 848 { 849 vtt_regulator_enable(); 850 return 0; 851 } 852 #endif 853 854 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 855 int ft_board_setup(void *blob, bd_t *bd) 856 { 857 ft_cpu_setup(blob, bd); 858 859 return 0; 860 } 861 #endif 862 863 #ifdef CONFIG_SPL_LOAD_FIT 864 int board_fit_config_name_match(const char *name) 865 { 866 if (board_is_x15()) { 867 if (board_is_x15_revb1()) { 868 if (!strcmp(name, "am57xx-beagle-x15-revb1")) 869 return 0; 870 } else if (!strcmp(name, "am57xx-beagle-x15")) { 871 return 0; 872 } 873 } else if (board_is_am572x_evm() && 874 !strcmp(name, "am57xx-beagle-x15")) { 875 return 0; 876 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) { 877 return 0; 878 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) { 879 return 0; 880 } 881 882 return -1; 883 } 884 #endif 885 886 #ifdef CONFIG_TI_SECURE_DEVICE 887 void board_fit_image_post_process(void **p_image, size_t *p_size) 888 { 889 secure_boot_verify_image(p_image, p_size); 890 } 891 892 void board_tee_image_process(ulong tee_image, size_t tee_size) 893 { 894 secure_tee_install((u32)tee_image); 895 } 896 897 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 898 #endif 899