174cc8b09SKipisz, Steven /* 274cc8b09SKipisz, Steven * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com 374cc8b09SKipisz, Steven * 474cc8b09SKipisz, Steven * Author: Felipe Balbi <balbi@ti.com> 574cc8b09SKipisz, Steven * 674cc8b09SKipisz, Steven * Based on board/ti/dra7xx/evm.c 774cc8b09SKipisz, Steven * 874cc8b09SKipisz, Steven * SPDX-License-Identifier: GPL-2.0+ 974cc8b09SKipisz, Steven */ 1074cc8b09SKipisz, Steven 1174cc8b09SKipisz, Steven #include <common.h> 1274cc8b09SKipisz, Steven #include <palmas.h> 1374cc8b09SKipisz, Steven #include <sata.h> 1474cc8b09SKipisz, Steven #include <usb.h> 1574cc8b09SKipisz, Steven #include <asm/omap_common.h> 1617c29873SAndreas Dannenberg #include <asm/omap_sec_common.h> 1774cc8b09SKipisz, Steven #include <asm/emif.h> 1874cc8b09SKipisz, Steven #include <asm/gpio.h> 1974cc8b09SKipisz, Steven #include <asm/arch/gpio.h> 2074cc8b09SKipisz, Steven #include <asm/arch/clock.h> 2174cc8b09SKipisz, Steven #include <asm/arch/dra7xx_iodelay.h> 2274cc8b09SKipisz, Steven #include <asm/arch/sys_proto.h> 2374cc8b09SKipisz, Steven #include <asm/arch/mmc_host_def.h> 2474cc8b09SKipisz, Steven #include <asm/arch/sata.h> 2574cc8b09SKipisz, Steven #include <asm/arch/gpio.h> 2674cc8b09SKipisz, Steven #include <asm/arch/omap.h> 2774cc8b09SKipisz, Steven #include <environment.h> 2874cc8b09SKipisz, Steven #include <usb.h> 2974cc8b09SKipisz, Steven #include <linux/usb/gadget.h> 3074cc8b09SKipisz, Steven #include <dwc3-uboot.h> 3174cc8b09SKipisz, Steven #include <dwc3-omap-uboot.h> 3274cc8b09SKipisz, Steven #include <ti-usb-phy-uboot.h> 33*c413baa9SKishon Vijay Abraham I #include <mmc.h> 3474cc8b09SKipisz, Steven 35212f96f6SKipisz, Steven #include "../common/board_detect.h" 3674cc8b09SKipisz, Steven #include "mux_data.h" 3774cc8b09SKipisz, Steven 38212f96f6SKipisz, Steven #define board_is_x15() board_ti_is("BBRDX15_") 39f7f9f6beSLokesh Vutla #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \ 4070879224SLokesh Vutla !strncmp("B.10", board_ti_get_rev(), 3)) 41f70a4272SLokesh Vutla #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \ 42f70a4272SLokesh Vutla !strncmp("C.00", board_ti_get_rev(), 3)) 43212f96f6SKipisz, Steven #define board_is_am572x_evm() board_ti_is("AM572PM_") 44bf43ce6cSNishanth Menon #define board_is_am572x_evm_reva3() \ 45bf43ce6cSNishanth Menon (board_ti_is("AM572PM_") && \ 4670879224SLokesh Vutla !strncmp("A.30", board_ti_get_rev(), 3)) 479646b95fSLokesh Vutla #define board_is_am574x_idk() board_ti_is("AM574IDK") 48c020d355SSteve Kipisz #define board_is_am572x_idk() board_ti_is("AM572IDK") 494d8397c6SSteve Kipisz #define board_is_am571x_idk() board_ti_is("AM571IDK") 50212f96f6SKipisz, Steven 5174cc8b09SKipisz, Steven #ifdef CONFIG_DRIVER_TI_CPSW 5274cc8b09SKipisz, Steven #include <cpsw.h> 5374cc8b09SKipisz, Steven #endif 5474cc8b09SKipisz, Steven 5574cc8b09SKipisz, Steven DECLARE_GLOBAL_DATA_PTR; 5674cc8b09SKipisz, Steven 5737611052SRoger Quadros #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22) 5874cc8b09SKipisz, Steven /* GPIO 7_11 */ 5974cc8b09SKipisz, Steven #define GPIO_DDR_VTT_EN 203 6074cc8b09SKipisz, Steven 61fcb18524SNishanth Menon /* Touch screen controller to identify the LCD */ 62fcb18524SNishanth Menon #define OSD_TS_FT_BUS_ADDRESS 0 63fcb18524SNishanth Menon #define OSD_TS_FT_CHIP_ADDRESS 0x38 64fcb18524SNishanth Menon #define OSD_TS_FT_REG_ID 0xA3 65fcb18524SNishanth Menon /* 66fcb18524SNishanth Menon * Touchscreen IDs for various OSD panels 67fcb18524SNishanth Menon * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf 68fcb18524SNishanth Menon */ 69fcb18524SNishanth Menon /* Used on newer osd101t2587 Panels */ 70fcb18524SNishanth Menon #define OSD_TS_FT_ID_5x46 0x54 71fcb18524SNishanth Menon /* Used on older osd101t2045 Panels */ 72fcb18524SNishanth Menon #define OSD_TS_FT_ID_5606 0x08 73fcb18524SNishanth Menon 74212f96f6SKipisz, Steven #define SYSINFO_BOARD_NAME_MAX_LEN 45 75212f96f6SKipisz, Steven 76385d3632SKeerthy #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB 77385d3632SKeerthy #define TPS65903X_PAD2_POWERHOLD_MASK 0x20 78385d3632SKeerthy 7974cc8b09SKipisz, Steven const struct omap_sysinfo sysinfo = { 80212f96f6SKipisz, Steven "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n" 8174cc8b09SKipisz, Steven }; 8274cc8b09SKipisz, Steven 8374cc8b09SKipisz, Steven static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { 8474cc8b09SKipisz, Steven .dmm_lisa_map_3 = 0x80740300, 8574cc8b09SKipisz, Steven .is_ma_present = 0x1 8674cc8b09SKipisz, Steven }; 8774cc8b09SKipisz, Steven 884d8397c6SSteve Kipisz static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { 894d8397c6SSteve Kipisz .dmm_lisa_map_3 = 0x80640100, 904d8397c6SSteve Kipisz .is_ma_present = 0x1 914d8397c6SSteve Kipisz }; 924d8397c6SSteve Kipisz 937b16de85SLokesh Vutla static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = { 947b16de85SLokesh Vutla .dmm_lisa_map_2 = 0xc0600200, 957b16de85SLokesh Vutla .dmm_lisa_map_3 = 0x80600100, 967b16de85SLokesh Vutla .is_ma_present = 0x1 977b16de85SLokesh Vutla }; 987b16de85SLokesh Vutla 9974cc8b09SKipisz, Steven void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 10074cc8b09SKipisz, Steven { 1014d8397c6SSteve Kipisz if (board_is_am571x_idk()) 1024d8397c6SSteve Kipisz *dmm_lisa_regs = &am571x_idk_lisa_regs; 1037b16de85SLokesh Vutla else if (board_is_am574x_idk()) 1047b16de85SLokesh Vutla *dmm_lisa_regs = &am574x_idk_lisa_regs; 1054d8397c6SSteve Kipisz else 10674cc8b09SKipisz, Steven *dmm_lisa_regs = &beagle_x15_lisa_regs; 10774cc8b09SKipisz, Steven } 10874cc8b09SKipisz, Steven 10974cc8b09SKipisz, Steven static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { 11074cc8b09SKipisz, Steven .sdram_config_init = 0x61851b32, 11174cc8b09SKipisz, Steven .sdram_config = 0x61851b32, 11211e2b043SLokesh Vutla .sdram_config2 = 0x08000000, 11374cc8b09SKipisz, Steven .ref_ctrl = 0x000040F1, 11474cc8b09SKipisz, Steven .ref_ctrl_final = 0x00001035, 11511e2b043SLokesh Vutla .sdram_tim1 = 0xcccf36ab, 11611e2b043SLokesh Vutla .sdram_tim2 = 0x308f7fda, 11711e2b043SLokesh Vutla .sdram_tim3 = 0x409f88a8, 11874cc8b09SKipisz, Steven .read_idle_ctrl = 0x00050000, 11911e2b043SLokesh Vutla .zq_config = 0x5007190b, 12074cc8b09SKipisz, Steven .temp_alert_config = 0x00000000, 12174cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1_init = 0x0024400b, 12274cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1 = 0x0e24400b, 12374cc8b09SKipisz, Steven .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 12411e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 12511e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 12611e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 12711e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 12874cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_win = 0x00000000, 12974cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 13074cc8b09SKipisz, Steven .emif_rd_wr_lvl_ctl = 0x00000000, 13174cc8b09SKipisz, Steven .emif_rd_wr_exec_thresh = 0x00000305 13274cc8b09SKipisz, Steven }; 13374cc8b09SKipisz, Steven 13474cc8b09SKipisz, Steven /* Ext phy ctrl regs 1-35 */ 13574cc8b09SKipisz, Steven static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 13674cc8b09SKipisz, Steven 0x10040100, 13711e2b043SLokesh Vutla 0x00910091, 13811e2b043SLokesh Vutla 0x00950095, 13911e2b043SLokesh Vutla 0x009B009B, 14011e2b043SLokesh Vutla 0x009E009E, 14111e2b043SLokesh Vutla 0x00980098, 14274cc8b09SKipisz, Steven 0x00340034, 14374cc8b09SKipisz, Steven 0x00350035, 14411e2b043SLokesh Vutla 0x00340034, 14511e2b043SLokesh Vutla 0x00310031, 14611e2b043SLokesh Vutla 0x00340034, 14711e2b043SLokesh Vutla 0x007F007F, 14811e2b043SLokesh Vutla 0x007F007F, 14911e2b043SLokesh Vutla 0x007F007F, 15011e2b043SLokesh Vutla 0x007F007F, 15111e2b043SLokesh Vutla 0x007F007F, 15211e2b043SLokesh Vutla 0x00480048, 15311e2b043SLokesh Vutla 0x004A004A, 15411e2b043SLokesh Vutla 0x00520052, 15511e2b043SLokesh Vutla 0x00550055, 15611e2b043SLokesh Vutla 0x00500050, 15774cc8b09SKipisz, Steven 0x00000000, 15874cc8b09SKipisz, Steven 0x00600020, 15974cc8b09SKipisz, Steven 0x40011080, 16074cc8b09SKipisz, Steven 0x08102040, 16111e2b043SLokesh Vutla 0x0, 16211e2b043SLokesh Vutla 0x0, 16311e2b043SLokesh Vutla 0x0, 16411e2b043SLokesh Vutla 0x0, 16511e2b043SLokesh Vutla 0x0, 16674cc8b09SKipisz, Steven 0x0, 16774cc8b09SKipisz, Steven 0x0, 16874cc8b09SKipisz, Steven 0x0, 16974cc8b09SKipisz, Steven 0x0, 17074cc8b09SKipisz, Steven 0x0 17174cc8b09SKipisz, Steven }; 17274cc8b09SKipisz, Steven 17374cc8b09SKipisz, Steven static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { 17474cc8b09SKipisz, Steven .sdram_config_init = 0x61851b32, 17574cc8b09SKipisz, Steven .sdram_config = 0x61851b32, 17611e2b043SLokesh Vutla .sdram_config2 = 0x08000000, 17774cc8b09SKipisz, Steven .ref_ctrl = 0x000040F1, 17874cc8b09SKipisz, Steven .ref_ctrl_final = 0x00001035, 1795f405e7fSSchuyler Patton .sdram_tim1 = 0xcccf36b3, 18011e2b043SLokesh Vutla .sdram_tim2 = 0x308f7fda, 1815f405e7fSSchuyler Patton .sdram_tim3 = 0x407f88a8, 18274cc8b09SKipisz, Steven .read_idle_ctrl = 0x00050000, 18311e2b043SLokesh Vutla .zq_config = 0x5007190b, 18474cc8b09SKipisz, Steven .temp_alert_config = 0x00000000, 18574cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1_init = 0x0024400b, 18674cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1 = 0x0e24400b, 18774cc8b09SKipisz, Steven .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 18811e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 18911e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 19011e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 19111e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 19274cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_win = 0x00000000, 19374cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 19474cc8b09SKipisz, Steven .emif_rd_wr_lvl_ctl = 0x00000000, 19574cc8b09SKipisz, Steven .emif_rd_wr_exec_thresh = 0x00000305 19674cc8b09SKipisz, Steven }; 19774cc8b09SKipisz, Steven 19874cc8b09SKipisz, Steven static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 19974cc8b09SKipisz, Steven 0x10040100, 20011e2b043SLokesh Vutla 0x00910091, 20111e2b043SLokesh Vutla 0x00950095, 20211e2b043SLokesh Vutla 0x009B009B, 20311e2b043SLokesh Vutla 0x009E009E, 20411e2b043SLokesh Vutla 0x00980098, 20511e2b043SLokesh Vutla 0x00340034, 20674cc8b09SKipisz, Steven 0x00350035, 20711e2b043SLokesh Vutla 0x00340034, 20811e2b043SLokesh Vutla 0x00310031, 20911e2b043SLokesh Vutla 0x00340034, 21011e2b043SLokesh Vutla 0x007F007F, 21111e2b043SLokesh Vutla 0x007F007F, 21211e2b043SLokesh Vutla 0x007F007F, 21311e2b043SLokesh Vutla 0x007F007F, 21411e2b043SLokesh Vutla 0x007F007F, 21511e2b043SLokesh Vutla 0x00480048, 21611e2b043SLokesh Vutla 0x004A004A, 21711e2b043SLokesh Vutla 0x00520052, 21811e2b043SLokesh Vutla 0x00550055, 21911e2b043SLokesh Vutla 0x00500050, 22074cc8b09SKipisz, Steven 0x00000000, 22174cc8b09SKipisz, Steven 0x00600020, 22274cc8b09SKipisz, Steven 0x40011080, 22374cc8b09SKipisz, Steven 0x08102040, 22411e2b043SLokesh Vutla 0x0, 22511e2b043SLokesh Vutla 0x0, 22611e2b043SLokesh Vutla 0x0, 22711e2b043SLokesh Vutla 0x0, 22811e2b043SLokesh Vutla 0x0, 22974cc8b09SKipisz, Steven 0x0, 23074cc8b09SKipisz, Steven 0x0, 23174cc8b09SKipisz, Steven 0x0, 23274cc8b09SKipisz, Steven 0x0, 23374cc8b09SKipisz, Steven 0x0 23474cc8b09SKipisz, Steven }; 23574cc8b09SKipisz, Steven 236209742faSSteve Kipisz static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { 237209742faSSteve Kipisz .sdram_config_init = 0x61863332, 238209742faSSteve Kipisz .sdram_config = 0x61863332, 239209742faSSteve Kipisz .sdram_config2 = 0x08000000, 240209742faSSteve Kipisz .ref_ctrl = 0x0000514d, 241209742faSSteve Kipisz .ref_ctrl_final = 0x0000144a, 242209742faSSteve Kipisz .sdram_tim1 = 0xd333887c, 2437b16de85SLokesh Vutla .sdram_tim2 = 0x30b37fe3, 2447b16de85SLokesh Vutla .sdram_tim3 = 0x409f8ad8, 245209742faSSteve Kipisz .read_idle_ctrl = 0x00050000, 246209742faSSteve Kipisz .zq_config = 0x5007190b, 247209742faSSteve Kipisz .temp_alert_config = 0x00000000, 248209742faSSteve Kipisz .emif_ddr_phy_ctlr_1_init = 0x0024400f, 249209742faSSteve Kipisz .emif_ddr_phy_ctlr_1 = 0x0e24400f, 250209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 251209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 252209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 253209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 254209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 255209742faSSteve Kipisz .emif_rd_wr_lvl_rmp_win = 0x00000000, 256209742faSSteve Kipisz .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 257209742faSSteve Kipisz .emif_rd_wr_lvl_ctl = 0x00000000, 258209742faSSteve Kipisz .emif_rd_wr_exec_thresh = 0x00000305 259209742faSSteve Kipisz }; 260209742faSSteve Kipisz 2617b16de85SLokesh Vutla static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = { 2627b16de85SLokesh Vutla .sdram_config_init = 0x61863332, 2637b16de85SLokesh Vutla .sdram_config = 0x61863332, 2647b16de85SLokesh Vutla .sdram_config2 = 0x08000000, 2657b16de85SLokesh Vutla .ref_ctrl = 0x0000514d, 2667b16de85SLokesh Vutla .ref_ctrl_final = 0x0000144a, 2677b16de85SLokesh Vutla .sdram_tim1 = 0xd333887c, 2687b16de85SLokesh Vutla .sdram_tim2 = 0x30b37fe3, 2697b16de85SLokesh Vutla .sdram_tim3 = 0x409f8ad8, 2707b16de85SLokesh Vutla .read_idle_ctrl = 0x00050000, 2717b16de85SLokesh Vutla .zq_config = 0x5007190b, 2727b16de85SLokesh Vutla .temp_alert_config = 0x00000000, 2737b16de85SLokesh Vutla .emif_ddr_phy_ctlr_1_init = 0x0024400f, 2747b16de85SLokesh Vutla .emif_ddr_phy_ctlr_1 = 0x0e24400f, 2757b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 2767b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 2777b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 2787b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 2797b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 2807b16de85SLokesh Vutla .emif_rd_wr_lvl_rmp_win = 0x00000000, 2817b16de85SLokesh Vutla .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 2827b16de85SLokesh Vutla .emif_rd_wr_lvl_ctl = 0x00000000, 2837b16de85SLokesh Vutla .emif_rd_wr_exec_thresh = 0x00000305, 2847b16de85SLokesh Vutla .emif_ecc_ctrl_reg = 0xD0000001, 2857b16de85SLokesh Vutla .emif_ecc_address_range_1 = 0x3FFF0000, 2867b16de85SLokesh Vutla .emif_ecc_address_range_2 = 0x00000000 2877b16de85SLokesh Vutla }; 2887b16de85SLokesh Vutla 28974cc8b09SKipisz, Steven void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 29074cc8b09SKipisz, Steven { 29174cc8b09SKipisz, Steven switch (emif_nr) { 29274cc8b09SKipisz, Steven case 1: 293209742faSSteve Kipisz if (board_is_am571x_idk()) 294209742faSSteve Kipisz *regs = &am571x_emif1_ddr3_666mhz_emif_regs; 2957b16de85SLokesh Vutla else if (board_is_am574x_idk()) 2967b16de85SLokesh Vutla *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs; 297209742faSSteve Kipisz else 29874cc8b09SKipisz, Steven *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; 29974cc8b09SKipisz, Steven break; 30074cc8b09SKipisz, Steven case 2: 3017b16de85SLokesh Vutla if (board_is_am574x_idk()) 3027b16de85SLokesh Vutla *regs = &am571x_emif1_ddr3_666mhz_emif_regs; 3037b16de85SLokesh Vutla else 30474cc8b09SKipisz, Steven *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; 30574cc8b09SKipisz, Steven break; 30674cc8b09SKipisz, Steven } 30774cc8b09SKipisz, Steven } 30874cc8b09SKipisz, Steven 30974cc8b09SKipisz, Steven void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) 31074cc8b09SKipisz, Steven { 31174cc8b09SKipisz, Steven switch (emif_nr) { 31274cc8b09SKipisz, Steven case 1: 31374cc8b09SKipisz, Steven *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; 31474cc8b09SKipisz, Steven *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); 31574cc8b09SKipisz, Steven break; 31674cc8b09SKipisz, Steven case 2: 31774cc8b09SKipisz, Steven *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; 31874cc8b09SKipisz, Steven *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); 31974cc8b09SKipisz, Steven break; 32074cc8b09SKipisz, Steven } 32174cc8b09SKipisz, Steven } 32274cc8b09SKipisz, Steven 32374cc8b09SKipisz, Steven struct vcores_data beagle_x15_volts = { 324beb71279SLokesh Vutla .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 325beb71279SLokesh Vutla .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 32674cc8b09SKipisz, Steven .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 32774cc8b09SKipisz, Steven .mpu.addr = TPS659038_REG_ADDR_SMPS12, 32874cc8b09SKipisz, Steven .mpu.pmic = &tps659038, 3293708e78cSNishanth Menon .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 33074cc8b09SKipisz, Steven 331beb71279SLokesh Vutla .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 332beb71279SLokesh Vutla .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 333beb71279SLokesh Vutla .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 334beb71279SLokesh Vutla .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 335beb71279SLokesh Vutla .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 336beb71279SLokesh Vutla .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 33774cc8b09SKipisz, Steven .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 33874cc8b09SKipisz, Steven .eve.addr = TPS659038_REG_ADDR_SMPS45, 33974cc8b09SKipisz, Steven .eve.pmic = &tps659038, 340e52e334eSNishanth Menon .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 34174cc8b09SKipisz, Steven 342beb71279SLokesh Vutla .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 343beb71279SLokesh Vutla .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 344beb71279SLokesh Vutla .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 345beb71279SLokesh Vutla .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 346beb71279SLokesh Vutla .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 347beb71279SLokesh Vutla .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 34874cc8b09SKipisz, Steven .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 34974cc8b09SKipisz, Steven .gpu.addr = TPS659038_REG_ADDR_SMPS45, 35074cc8b09SKipisz, Steven .gpu.pmic = &tps659038, 351e52e334eSNishanth Menon .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 35274cc8b09SKipisz, Steven 353beb71279SLokesh Vutla .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 354beb71279SLokesh Vutla .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 35574cc8b09SKipisz, Steven .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 35674cc8b09SKipisz, Steven .core.addr = TPS659038_REG_ADDR_SMPS6, 35774cc8b09SKipisz, Steven .core.pmic = &tps659038, 35874cc8b09SKipisz, Steven 359beb71279SLokesh Vutla .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 360beb71279SLokesh Vutla .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 361beb71279SLokesh Vutla .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 362beb71279SLokesh Vutla .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 363beb71279SLokesh Vutla .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 364beb71279SLokesh Vutla .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 36574cc8b09SKipisz, Steven .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 36674cc8b09SKipisz, Steven .iva.addr = TPS659038_REG_ADDR_SMPS45, 36774cc8b09SKipisz, Steven .iva.pmic = &tps659038, 368e52e334eSNishanth Menon .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 36974cc8b09SKipisz, Steven }; 37074cc8b09SKipisz, Steven 371d60198daSKeerthy struct vcores_data am572x_idk_volts = { 372beb71279SLokesh Vutla .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 373beb71279SLokesh Vutla .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 374d60198daSKeerthy .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 375d60198daSKeerthy .mpu.addr = TPS659038_REG_ADDR_SMPS12, 376d60198daSKeerthy .mpu.pmic = &tps659038, 377d60198daSKeerthy .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 378d60198daSKeerthy 379beb71279SLokesh Vutla .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 380beb71279SLokesh Vutla .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 381beb71279SLokesh Vutla .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 382beb71279SLokesh Vutla .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 383beb71279SLokesh Vutla .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 384beb71279SLokesh Vutla .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 385d60198daSKeerthy .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 386d60198daSKeerthy .eve.addr = TPS659038_REG_ADDR_SMPS45, 387d60198daSKeerthy .eve.pmic = &tps659038, 388d60198daSKeerthy .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 389d60198daSKeerthy 390beb71279SLokesh Vutla .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 391beb71279SLokesh Vutla .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 392beb71279SLokesh Vutla .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 393beb71279SLokesh Vutla .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 394beb71279SLokesh Vutla .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 395beb71279SLokesh Vutla .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 396d60198daSKeerthy .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 397d60198daSKeerthy .gpu.addr = TPS659038_REG_ADDR_SMPS6, 398d60198daSKeerthy .gpu.pmic = &tps659038, 399d60198daSKeerthy .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 400d60198daSKeerthy 401beb71279SLokesh Vutla .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 402beb71279SLokesh Vutla .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 403d60198daSKeerthy .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 404d60198daSKeerthy .core.addr = TPS659038_REG_ADDR_SMPS7, 405d60198daSKeerthy .core.pmic = &tps659038, 406d60198daSKeerthy 407beb71279SLokesh Vutla .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 408beb71279SLokesh Vutla .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 409beb71279SLokesh Vutla .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 410beb71279SLokesh Vutla .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 411beb71279SLokesh Vutla .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 412beb71279SLokesh Vutla .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 413d60198daSKeerthy .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 414d60198daSKeerthy .iva.addr = TPS659038_REG_ADDR_SMPS8, 415d60198daSKeerthy .iva.pmic = &tps659038, 416d60198daSKeerthy .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 417d60198daSKeerthy }; 418d60198daSKeerthy 419b12550ebSKeerthy struct vcores_data am571x_idk_volts = { 420b12550ebSKeerthy .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 421b12550ebSKeerthy .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 422b12550ebSKeerthy .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 423b12550ebSKeerthy .mpu.addr = TPS659038_REG_ADDR_SMPS12, 424b12550ebSKeerthy .mpu.pmic = &tps659038, 425b12550ebSKeerthy .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 426b12550ebSKeerthy 427b12550ebSKeerthy .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 428b12550ebSKeerthy .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 429b12550ebSKeerthy .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 430b12550ebSKeerthy .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 431b12550ebSKeerthy .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 432b12550ebSKeerthy .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 433b12550ebSKeerthy .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 434b12550ebSKeerthy .eve.addr = TPS659038_REG_ADDR_SMPS45, 435b12550ebSKeerthy .eve.pmic = &tps659038, 436b12550ebSKeerthy .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 437b12550ebSKeerthy 438b12550ebSKeerthy .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 439b12550ebSKeerthy .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 440b12550ebSKeerthy .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 441b12550ebSKeerthy .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 442b12550ebSKeerthy .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 443b12550ebSKeerthy .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 444b12550ebSKeerthy .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 445b12550ebSKeerthy .gpu.addr = TPS659038_REG_ADDR_SMPS6, 446b12550ebSKeerthy .gpu.pmic = &tps659038, 447b12550ebSKeerthy .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 448b12550ebSKeerthy 449b12550ebSKeerthy .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 450b12550ebSKeerthy .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 451b12550ebSKeerthy .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 452b12550ebSKeerthy .core.addr = TPS659038_REG_ADDR_SMPS7, 453b12550ebSKeerthy .core.pmic = &tps659038, 454b12550ebSKeerthy 455b12550ebSKeerthy .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 456b12550ebSKeerthy .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 457b12550ebSKeerthy .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 458b12550ebSKeerthy .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 459b12550ebSKeerthy .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 460b12550ebSKeerthy .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 461b12550ebSKeerthy .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 462b12550ebSKeerthy .iva.addr = TPS659038_REG_ADDR_SMPS45, 463b12550ebSKeerthy .iva.pmic = &tps659038, 464b12550ebSKeerthy .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 465b12550ebSKeerthy }; 466b12550ebSKeerthy 467beb71279SLokesh Vutla int get_voltrail_opp(int rail_offset) 468beb71279SLokesh Vutla { 469beb71279SLokesh Vutla int opp; 470beb71279SLokesh Vutla 471beb71279SLokesh Vutla switch (rail_offset) { 472beb71279SLokesh Vutla case VOLT_MPU: 473beb71279SLokesh Vutla opp = DRA7_MPU_OPP; 474beb71279SLokesh Vutla break; 475beb71279SLokesh Vutla case VOLT_CORE: 476beb71279SLokesh Vutla opp = DRA7_CORE_OPP; 477beb71279SLokesh Vutla break; 478beb71279SLokesh Vutla case VOLT_GPU: 479beb71279SLokesh Vutla opp = DRA7_GPU_OPP; 480beb71279SLokesh Vutla break; 481beb71279SLokesh Vutla case VOLT_EVE: 482beb71279SLokesh Vutla opp = DRA7_DSPEVE_OPP; 483beb71279SLokesh Vutla break; 484beb71279SLokesh Vutla case VOLT_IVA: 485beb71279SLokesh Vutla opp = DRA7_IVA_OPP; 486beb71279SLokesh Vutla break; 487beb71279SLokesh Vutla default: 488beb71279SLokesh Vutla opp = OPP_NOM; 489beb71279SLokesh Vutla } 490beb71279SLokesh Vutla 491beb71279SLokesh Vutla return opp; 492beb71279SLokesh Vutla } 493beb71279SLokesh Vutla 494beb71279SLokesh Vutla 495212f96f6SKipisz, Steven #ifdef CONFIG_SPL_BUILD 496212f96f6SKipisz, Steven /* No env to setup for SPL */ 497212f96f6SKipisz, Steven static inline void setup_board_eeprom_env(void) { } 498212f96f6SKipisz, Steven 499212f96f6SKipisz, Steven /* Override function to read eeprom information */ 500212f96f6SKipisz, Steven void do_board_detect(void) 501212f96f6SKipisz, Steven { 502212f96f6SKipisz, Steven int rc; 503212f96f6SKipisz, Steven 504212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 505212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS); 506212f96f6SKipisz, Steven if (rc) 507212f96f6SKipisz, Steven printf("ti_i2c_eeprom_init failed %d\n", rc); 508212f96f6SKipisz, Steven } 509212f96f6SKipisz, Steven 510212f96f6SKipisz, Steven #else /* CONFIG_SPL_BUILD */ 511212f96f6SKipisz, Steven 512212f96f6SKipisz, Steven /* Override function to read eeprom information: actual i2c read done by SPL*/ 513212f96f6SKipisz, Steven void do_board_detect(void) 514212f96f6SKipisz, Steven { 515212f96f6SKipisz, Steven char *bname = NULL; 516212f96f6SKipisz, Steven int rc; 517212f96f6SKipisz, Steven 518212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 519212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS); 520212f96f6SKipisz, Steven if (rc) 521212f96f6SKipisz, Steven printf("ti_i2c_eeprom_init failed %d\n", rc); 522212f96f6SKipisz, Steven 523212f96f6SKipisz, Steven if (board_is_x15()) 524212f96f6SKipisz, Steven bname = "BeagleBoard X15"; 525212f96f6SKipisz, Steven else if (board_is_am572x_evm()) 526212f96f6SKipisz, Steven bname = "AM572x EVM"; 5279646b95fSLokesh Vutla else if (board_is_am574x_idk()) 5289646b95fSLokesh Vutla bname = "AM574x IDK"; 529c020d355SSteve Kipisz else if (board_is_am572x_idk()) 530c020d355SSteve Kipisz bname = "AM572x IDK"; 5314d8397c6SSteve Kipisz else if (board_is_am571x_idk()) 5324d8397c6SSteve Kipisz bname = "AM571x IDK"; 533212f96f6SKipisz, Steven 534212f96f6SKipisz, Steven if (bname) 535212f96f6SKipisz, Steven snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 536212f96f6SKipisz, Steven "Board: %s REV %s\n", bname, board_ti_get_rev()); 537212f96f6SKipisz, Steven } 538212f96f6SKipisz, Steven 539212f96f6SKipisz, Steven static void setup_board_eeprom_env(void) 540212f96f6SKipisz, Steven { 541212f96f6SKipisz, Steven char *name = "beagle_x15"; 542212f96f6SKipisz, Steven int rc; 543212f96f6SKipisz, Steven 544212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 545212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS); 546212f96f6SKipisz, Steven if (rc) 547212f96f6SKipisz, Steven goto invalid_eeprom; 548212f96f6SKipisz, Steven 549bf43ce6cSNishanth Menon if (board_is_x15()) { 550f7f9f6beSLokesh Vutla if (board_is_x15_revb1()) 551f7f9f6beSLokesh Vutla name = "beagle_x15_revb1"; 552f70a4272SLokesh Vutla else if (board_is_x15_revc()) 553f70a4272SLokesh Vutla name = "beagle_x15_revc"; 554f7f9f6beSLokesh Vutla else 555c9891660SNishanth Menon name = "beagle_x15"; 556bf43ce6cSNishanth Menon } else if (board_is_am572x_evm()) { 557bf43ce6cSNishanth Menon if (board_is_am572x_evm_reva3()) 558bf43ce6cSNishanth Menon name = "am57xx_evm_reva3"; 559212f96f6SKipisz, Steven else 560bf43ce6cSNishanth Menon name = "am57xx_evm"; 5619646b95fSLokesh Vutla } else if (board_is_am574x_idk()) { 5629646b95fSLokesh Vutla name = "am574x_idk"; 563bf43ce6cSNishanth Menon } else if (board_is_am572x_idk()) { 564bf43ce6cSNishanth Menon name = "am572x_idk"; 5654d8397c6SSteve Kipisz } else if (board_is_am571x_idk()) { 5664d8397c6SSteve Kipisz name = "am571x_idk"; 567bf43ce6cSNishanth Menon } else { 568212f96f6SKipisz, Steven printf("Unidentified board claims %s in eeprom header\n", 569212f96f6SKipisz, Steven board_ti_get_name()); 570bf43ce6cSNishanth Menon } 571212f96f6SKipisz, Steven 572212f96f6SKipisz, Steven invalid_eeprom: 573212f96f6SKipisz, Steven set_board_info_env(name); 574212f96f6SKipisz, Steven } 575212f96f6SKipisz, Steven 576212f96f6SKipisz, Steven #endif /* CONFIG_SPL_BUILD */ 577212f96f6SKipisz, Steven 578d60198daSKeerthy void vcores_init(void) 579d60198daSKeerthy { 58010f430f3SLokesh Vutla if (board_is_am572x_idk() || board_is_am574x_idk()) 581d60198daSKeerthy *omap_vcores = &am572x_idk_volts; 582b12550ebSKeerthy else if (board_is_am571x_idk()) 583b12550ebSKeerthy *omap_vcores = &am571x_idk_volts; 584d60198daSKeerthy else 585d60198daSKeerthy *omap_vcores = &beagle_x15_volts; 586d60198daSKeerthy } 587d60198daSKeerthy 58874cc8b09SKipisz, Steven void hw_data_init(void) 58974cc8b09SKipisz, Steven { 59074cc8b09SKipisz, Steven *prcm = &dra7xx_prcm; 591209742faSSteve Kipisz if (is_dra72x()) 592209742faSSteve Kipisz *dplls_data = &dra72x_dplls; 59310f430f3SLokesh Vutla else if (is_dra76x()) 59410f430f3SLokesh Vutla *dplls_data = &dra76x_dplls; 595209742faSSteve Kipisz else 59674cc8b09SKipisz, Steven *dplls_data = &dra7xx_dplls; 59774cc8b09SKipisz, Steven *ctrl = &dra7xx_ctrl; 59874cc8b09SKipisz, Steven } 59974cc8b09SKipisz, Steven 60037611052SRoger Quadros bool am571x_idk_needs_lcd(void) 60137611052SRoger Quadros { 60237611052SRoger Quadros bool needs_lcd; 60337611052SRoger Quadros 60437611052SRoger Quadros gpio_request(GPIO_ETH_LCD, "nLCD_Detect"); 60537611052SRoger Quadros if (gpio_get_value(GPIO_ETH_LCD)) 60637611052SRoger Quadros needs_lcd = false; 60737611052SRoger Quadros else 60837611052SRoger Quadros needs_lcd = true; 60937611052SRoger Quadros 61037611052SRoger Quadros gpio_free(GPIO_ETH_LCD); 61137611052SRoger Quadros 61237611052SRoger Quadros return needs_lcd; 61337611052SRoger Quadros } 61437611052SRoger Quadros 61574cc8b09SKipisz, Steven int board_init(void) 61674cc8b09SKipisz, Steven { 61774cc8b09SKipisz, Steven gpmc_init(); 61874cc8b09SKipisz, Steven gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 61974cc8b09SKipisz, Steven 62074cc8b09SKipisz, Steven return 0; 62174cc8b09SKipisz, Steven } 62274cc8b09SKipisz, Steven 623fcb18524SNishanth Menon void am57x_idk_lcd_detect(void) 624fcb18524SNishanth Menon { 625fcb18524SNishanth Menon int r = -ENODEV; 626fcb18524SNishanth Menon char *idk_lcd = "no"; 627fcb18524SNishanth Menon uint8_t buf = 0; 628fcb18524SNishanth Menon 629fcb18524SNishanth Menon /* Only valid for IDKs */ 630fcb18524SNishanth Menon if (board_is_x15() || board_is_am572x_evm()) 631fcb18524SNishanth Menon return; 632fcb18524SNishanth Menon 633fcb18524SNishanth Menon /* Only AM571x IDK has gpio control detect.. so check that */ 634fcb18524SNishanth Menon if (board_is_am571x_idk() && !am571x_idk_needs_lcd()) 635fcb18524SNishanth Menon goto out; 636fcb18524SNishanth Menon 637fcb18524SNishanth Menon r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS); 638fcb18524SNishanth Menon if (r) { 639fcb18524SNishanth Menon printf("%s: Failed to set bus address to %d: %d\n", 640fcb18524SNishanth Menon __func__, OSD_TS_FT_BUS_ADDRESS, r); 641fcb18524SNishanth Menon goto out; 642fcb18524SNishanth Menon } 643fcb18524SNishanth Menon r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS); 644fcb18524SNishanth Menon if (r) { 645fcb18524SNishanth Menon /* AM572x IDK has no explicit settings for optional LCD kit */ 646fcb18524SNishanth Menon if (board_is_am571x_idk()) { 647fcb18524SNishanth Menon printf("%s: Touch screen detect failed: %d!\n", 648fcb18524SNishanth Menon __func__, r); 649fcb18524SNishanth Menon } 650fcb18524SNishanth Menon goto out; 651fcb18524SNishanth Menon } 652fcb18524SNishanth Menon 653fcb18524SNishanth Menon /* Read FT ID */ 654fcb18524SNishanth Menon r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1); 655fcb18524SNishanth Menon if (r) { 656fcb18524SNishanth Menon printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n", 657fcb18524SNishanth Menon __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS, 658fcb18524SNishanth Menon OSD_TS_FT_REG_ID, r); 659fcb18524SNishanth Menon goto out; 660fcb18524SNishanth Menon } 661fcb18524SNishanth Menon 662fcb18524SNishanth Menon switch (buf) { 663fcb18524SNishanth Menon case OSD_TS_FT_ID_5606: 664fcb18524SNishanth Menon idk_lcd = "osd101t2045"; 665fcb18524SNishanth Menon break; 666fcb18524SNishanth Menon case OSD_TS_FT_ID_5x46: 667fcb18524SNishanth Menon idk_lcd = "osd101t2587"; 668fcb18524SNishanth Menon break; 669fcb18524SNishanth Menon default: 670fcb18524SNishanth Menon printf("%s: Unidentifed Touch screen ID 0x%02x\n", 671fcb18524SNishanth Menon __func__, buf); 672fcb18524SNishanth Menon /* we will let default be "no lcd" */ 673fcb18524SNishanth Menon } 674fcb18524SNishanth Menon out: 675382bee57SSimon Glass env_set("idk_lcd", idk_lcd); 676fcb18524SNishanth Menon return; 677fcb18524SNishanth Menon } 678fcb18524SNishanth Menon 67974cc8b09SKipisz, Steven int board_late_init(void) 68074cc8b09SKipisz, Steven { 681212f96f6SKipisz, Steven setup_board_eeprom_env(); 682385d3632SKeerthy u8 val; 683212f96f6SKipisz, Steven 68474cc8b09SKipisz, Steven /* 68574cc8b09SKipisz, Steven * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds 68674cc8b09SKipisz, Steven * This is the POWERHOLD-in-Low behavior. 68774cc8b09SKipisz, Steven */ 68874cc8b09SKipisz, Steven palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); 68982cca5a6SLokesh Vutla 69082cca5a6SLokesh Vutla /* 69182cca5a6SLokesh Vutla * Default FIT boot on HS devices. Non FIT images are not allowed 69282cca5a6SLokesh Vutla * on HS devices. 69382cca5a6SLokesh Vutla */ 69482cca5a6SLokesh Vutla if (get_device_type() == HS_DEVICE) 695382bee57SSimon Glass env_set("boot_fit", "1"); 69682cca5a6SLokesh Vutla 697385d3632SKeerthy /* 698385d3632SKeerthy * Set the GPIO7 Pad to POWERHOLD. This has higher priority 699385d3632SKeerthy * over DEV_CTRL.DEV_ON bit. This can be reset in case of 700385d3632SKeerthy * PMIC Power off. So to be on the safer side set it back 701385d3632SKeerthy * to POWERHOLD mode irrespective of the current state. 702385d3632SKeerthy */ 703385d3632SKeerthy palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2, 704385d3632SKeerthy &val); 705385d3632SKeerthy val = val | TPS65903X_PAD2_POWERHOLD_MASK; 706385d3632SKeerthy palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2, 707385d3632SKeerthy val); 708385d3632SKeerthy 7097a2af751SSemen Protsenko omap_die_id_serial(); 7108bd29623SSemen Protsenko omap_set_fastboot_vars(); 7117a2af751SSemen Protsenko 712fcb18524SNishanth Menon am57x_idk_lcd_detect(); 71337611052SRoger Quadros 71437611052SRoger Quadros #if !defined(CONFIG_SPL_BUILD) 71537611052SRoger Quadros board_ti_set_ethaddr(2); 71637611052SRoger Quadros #endif 71737611052SRoger Quadros 71874cc8b09SKipisz, Steven return 0; 71974cc8b09SKipisz, Steven } 72074cc8b09SKipisz, Steven 7213ef56e61SPaul Kocialkowski void set_muxconf_regs(void) 72274cc8b09SKipisz, Steven { 72374cc8b09SKipisz, Steven do_set_mux32((*ctrl)->control_padconf_core_base, 72474cc8b09SKipisz, Steven early_padconf, ARRAY_SIZE(early_padconf)); 72574cc8b09SKipisz, Steven } 72674cc8b09SKipisz, Steven 72774cc8b09SKipisz, Steven #ifdef CONFIG_IODELAY_RECALIBRATION 72874cc8b09SKipisz, Steven void recalibrate_iodelay(void) 72974cc8b09SKipisz, Steven { 730c020d355SSteve Kipisz const struct pad_conf_entry *pconf; 7312d7e9e9dSLokesh Vutla const struct iodelay_cfg_entry *iod, *delta_iod; 7322d7e9e9dSLokesh Vutla int pconf_sz, iod_sz, delta_iod_sz = 0; 73389a38953SNishanth Menon int ret; 734c020d355SSteve Kipisz 735443b0df3SLokesh Vutla if (board_is_am572x_idk()) { 736c020d355SSteve Kipisz pconf = core_padconf_array_essential_am572x_idk; 737c020d355SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); 738c020d355SSteve Kipisz iod = iodelay_cfg_array_am572x_idk; 739c020d355SSteve Kipisz iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk); 740443b0df3SLokesh Vutla } else if (board_is_am574x_idk()) { 741443b0df3SLokesh Vutla pconf = core_padconf_array_essential_am574x_idk; 742443b0df3SLokesh Vutla pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk); 743443b0df3SLokesh Vutla iod = iodelay_cfg_array_am574x_idk; 744443b0df3SLokesh Vutla iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk); 7454d8397c6SSteve Kipisz } else if (board_is_am571x_idk()) { 7464d8397c6SSteve Kipisz pconf = core_padconf_array_essential_am571x_idk; 7474d8397c6SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk); 7484d8397c6SSteve Kipisz iod = iodelay_cfg_array_am571x_idk; 7494d8397c6SSteve Kipisz iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk); 750c020d355SSteve Kipisz } else { 751c020d355SSteve Kipisz /* Common for X15/GPEVM */ 752c020d355SSteve Kipisz pconf = core_padconf_array_essential_x15; 753c020d355SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15); 75489a38953SNishanth Menon /* There never was an SR1.0 X15.. So.. */ 75589a38953SNishanth Menon if (omap_revision() == DRA752_ES1_1) { 75689a38953SNishanth Menon iod = iodelay_cfg_array_x15_sr1_1; 75789a38953SNishanth Menon iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1); 75889a38953SNishanth Menon } else { 75989a38953SNishanth Menon /* Since full production should switch to SR2.0 */ 76089a38953SNishanth Menon iod = iodelay_cfg_array_x15_sr2_0; 76189a38953SNishanth Menon iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0); 76289a38953SNishanth Menon } 763c020d355SSteve Kipisz } 764c020d355SSteve Kipisz 76589a38953SNishanth Menon /* Setup I/O isolation */ 76689a38953SNishanth Menon ret = __recalibrate_iodelay_start(); 76789a38953SNishanth Menon if (ret) 76889a38953SNishanth Menon goto err; 76989a38953SNishanth Menon 77089a38953SNishanth Menon /* Do the muxing here */ 77189a38953SNishanth Menon do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); 77289a38953SNishanth Menon 77389a38953SNishanth Menon /* Now do the weird minor deltas that should be safe */ 77489a38953SNishanth Menon if (board_is_x15() || board_is_am572x_evm()) { 775f70a4272SLokesh Vutla if (board_is_x15_revb1() || board_is_am572x_evm_reva3() || 776f70a4272SLokesh Vutla board_is_x15_revc()) { 77789a38953SNishanth Menon pconf = core_padconf_array_delta_x15_sr2_0; 77889a38953SNishanth Menon pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0); 77989a38953SNishanth Menon } else { 78089a38953SNishanth Menon pconf = core_padconf_array_delta_x15_sr1_1; 78189a38953SNishanth Menon pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1); 78289a38953SNishanth Menon } 78389a38953SNishanth Menon do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); 78489a38953SNishanth Menon } 78589a38953SNishanth Menon 78637611052SRoger Quadros if (board_is_am571x_idk()) { 78737611052SRoger Quadros if (am571x_idk_needs_lcd()) { 78837611052SRoger Quadros pconf = core_padconf_array_vout_am571x_idk; 78937611052SRoger Quadros pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk); 7902d7e9e9dSLokesh Vutla delta_iod = iodelay_cfg_array_am571x_idk_4port; 7912d7e9e9dSLokesh Vutla delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port); 7922d7e9e9dSLokesh Vutla 79337611052SRoger Quadros } else { 79437611052SRoger Quadros pconf = core_padconf_array_icss1eth_am571x_idk; 79537611052SRoger Quadros pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk); 79637611052SRoger Quadros } 79737611052SRoger Quadros do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); 79837611052SRoger Quadros } 79937611052SRoger Quadros 80089a38953SNishanth Menon /* Setup IOdelay configuration */ 80189a38953SNishanth Menon ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz); 8022d7e9e9dSLokesh Vutla if (delta_iod_sz) 8032d7e9e9dSLokesh Vutla ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod, 8042d7e9e9dSLokesh Vutla delta_iod_sz); 8052d7e9e9dSLokesh Vutla 80689a38953SNishanth Menon err: 80789a38953SNishanth Menon /* Closeup.. remove isolation */ 80889a38953SNishanth Menon __recalibrate_iodelay_end(ret); 80974cc8b09SKipisz, Steven } 81074cc8b09SKipisz, Steven #endif 81174cc8b09SKipisz, Steven 8124aa2ba3aSMasahiro Yamada #if defined(CONFIG_MMC) 81374cc8b09SKipisz, Steven int board_mmc_init(bd_t *bis) 81474cc8b09SKipisz, Steven { 81574cc8b09SKipisz, Steven omap_mmc_init(0, 0, 0, -1, -1); 81674cc8b09SKipisz, Steven omap_mmc_init(1, 0, 0, -1, -1); 81774cc8b09SKipisz, Steven return 0; 81874cc8b09SKipisz, Steven } 819*c413baa9SKishon Vijay Abraham I 820*c413baa9SKishon Vijay Abraham I static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = { 821*c413baa9SKishon Vijay Abraham I .hw_rev = "rev11", 822*c413baa9SKishon Vijay Abraham I .unsupported_caps = MMC_CAP(MMC_HS_200) | 823*c413baa9SKishon Vijay Abraham I MMC_CAP(UHS_SDR104), 824*c413baa9SKishon Vijay Abraham I .max_freq = 96000000, 825*c413baa9SKishon Vijay Abraham I }; 826*c413baa9SKishon Vijay Abraham I 827*c413baa9SKishon Vijay Abraham I static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = { 828*c413baa9SKishon Vijay Abraham I .hw_rev = "rev11", 829*c413baa9SKishon Vijay Abraham I .unsupported_caps = MMC_CAP(MMC_HS_200) | 830*c413baa9SKishon Vijay Abraham I MMC_CAP(UHS_SDR104) | 831*c413baa9SKishon Vijay Abraham I MMC_CAP(UHS_SDR50), 832*c413baa9SKishon Vijay Abraham I .max_freq = 48000000, 833*c413baa9SKishon Vijay Abraham I }; 834*c413baa9SKishon Vijay Abraham I 835*c413baa9SKishon Vijay Abraham I const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) 836*c413baa9SKishon Vijay Abraham I { 837*c413baa9SKishon Vijay Abraham I switch (omap_revision()) { 838*c413baa9SKishon Vijay Abraham I case DRA752_ES1_0: 839*c413baa9SKishon Vijay Abraham I case DRA752_ES1_1: 840*c413baa9SKishon Vijay Abraham I if (addr == OMAP_HSMMC1_BASE) 841*c413baa9SKishon Vijay Abraham I return &am57x_es1_1_mmc1_fixups; 842*c413baa9SKishon Vijay Abraham I else 843*c413baa9SKishon Vijay Abraham I return &am57x_es1_1_mmc23_fixups; 844*c413baa9SKishon Vijay Abraham I default: 845*c413baa9SKishon Vijay Abraham I return NULL; 846*c413baa9SKishon Vijay Abraham I } 847*c413baa9SKishon Vijay Abraham I } 84874cc8b09SKipisz, Steven #endif 84974cc8b09SKipisz, Steven 85074cc8b09SKipisz, Steven #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 85174cc8b09SKipisz, Steven int spl_start_uboot(void) 85274cc8b09SKipisz, Steven { 85374cc8b09SKipisz, Steven /* break into full u-boot on 'c' */ 85474cc8b09SKipisz, Steven if (serial_tstc() && serial_getc() == 'c') 85574cc8b09SKipisz, Steven return 1; 85674cc8b09SKipisz, Steven 85774cc8b09SKipisz, Steven #ifdef CONFIG_SPL_ENV_SUPPORT 85874cc8b09SKipisz, Steven env_init(); 859310fb14bSSimon Glass env_load(); 860bfebc8c9SSimon Glass if (env_get_yesno("boot_os") != 1) 86174cc8b09SKipisz, Steven return 1; 86274cc8b09SKipisz, Steven #endif 86374cc8b09SKipisz, Steven 86474cc8b09SKipisz, Steven return 0; 86574cc8b09SKipisz, Steven } 86674cc8b09SKipisz, Steven #endif 86774cc8b09SKipisz, Steven 86874cc8b09SKipisz, Steven #ifdef CONFIG_USB_DWC3 86974cc8b09SKipisz, Steven static struct dwc3_device usb_otg_ss2 = { 87074cc8b09SKipisz, Steven .maximum_speed = USB_SPEED_HIGH, 87174cc8b09SKipisz, Steven .base = DRA7_USB_OTG_SS2_BASE, 87274cc8b09SKipisz, Steven .tx_fifo_resize = false, 87374cc8b09SKipisz, Steven .index = 1, 87474cc8b09SKipisz, Steven }; 87574cc8b09SKipisz, Steven 87674cc8b09SKipisz, Steven static struct dwc3_omap_device usb_otg_ss2_glue = { 87774cc8b09SKipisz, Steven .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 87874cc8b09SKipisz, Steven .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 87974cc8b09SKipisz, Steven .index = 1, 88074cc8b09SKipisz, Steven }; 88174cc8b09SKipisz, Steven 88274cc8b09SKipisz, Steven static struct ti_usb_phy_device usb_phy2_device = { 88374cc8b09SKipisz, Steven .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 88474cc8b09SKipisz, Steven .index = 1, 88574cc8b09SKipisz, Steven }; 88674cc8b09SKipisz, Steven 88774cc8b09SKipisz, Steven int usb_gadget_handle_interrupts(int index) 88874cc8b09SKipisz, Steven { 88974cc8b09SKipisz, Steven u32 status; 89074cc8b09SKipisz, Steven 89174cc8b09SKipisz, Steven status = dwc3_omap_uboot_interrupt_status(index); 89274cc8b09SKipisz, Steven if (status) 89374cc8b09SKipisz, Steven dwc3_uboot_handle_interrupt(index); 89474cc8b09SKipisz, Steven 89574cc8b09SKipisz, Steven return 0; 89674cc8b09SKipisz, Steven } 89755efaddeSRoger Quadros #endif /* CONFIG_USB_DWC3 */ 89855efaddeSRoger Quadros 89955efaddeSRoger Quadros #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 900b16c129cSFaiz Abbas int board_usb_init(int index, enum usb_init_type init) 90155efaddeSRoger Quadros { 90255efaddeSRoger Quadros enable_usb_clocks(index); 90355efaddeSRoger Quadros switch (index) { 90455efaddeSRoger Quadros case 0: 90555efaddeSRoger Quadros if (init == USB_INIT_DEVICE) { 90655efaddeSRoger Quadros printf("port %d can't be used as device\n", index); 90755efaddeSRoger Quadros disable_usb_clocks(index); 90855efaddeSRoger Quadros return -EINVAL; 90955efaddeSRoger Quadros } 91055efaddeSRoger Quadros break; 91155efaddeSRoger Quadros case 1: 91255efaddeSRoger Quadros if (init == USB_INIT_DEVICE) { 91355efaddeSRoger Quadros #ifdef CONFIG_USB_DWC3 91455efaddeSRoger Quadros usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 91555efaddeSRoger Quadros usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 91655efaddeSRoger Quadros ti_usb_phy_uboot_init(&usb_phy2_device); 91755efaddeSRoger Quadros dwc3_omap_uboot_init(&usb_otg_ss2_glue); 91855efaddeSRoger Quadros dwc3_uboot_init(&usb_otg_ss2); 91974cc8b09SKipisz, Steven #endif 92055efaddeSRoger Quadros } else { 92155efaddeSRoger Quadros printf("port %d can't be used as host\n", index); 92255efaddeSRoger Quadros disable_usb_clocks(index); 92355efaddeSRoger Quadros return -EINVAL; 92455efaddeSRoger Quadros } 92555efaddeSRoger Quadros 92655efaddeSRoger Quadros break; 92755efaddeSRoger Quadros default: 92855efaddeSRoger Quadros printf("Invalid Controller Index\n"); 92955efaddeSRoger Quadros } 93055efaddeSRoger Quadros 93155efaddeSRoger Quadros return 0; 93255efaddeSRoger Quadros } 93355efaddeSRoger Quadros 934b16c129cSFaiz Abbas int board_usb_cleanup(int index, enum usb_init_type init) 93555efaddeSRoger Quadros { 93655efaddeSRoger Quadros #ifdef CONFIG_USB_DWC3 93755efaddeSRoger Quadros switch (index) { 93855efaddeSRoger Quadros case 0: 93955efaddeSRoger Quadros case 1: 94055efaddeSRoger Quadros if (init == USB_INIT_DEVICE) { 94155efaddeSRoger Quadros ti_usb_phy_uboot_exit(index); 94255efaddeSRoger Quadros dwc3_uboot_exit(index); 94355efaddeSRoger Quadros dwc3_omap_uboot_exit(index); 94455efaddeSRoger Quadros } 94555efaddeSRoger Quadros break; 94655efaddeSRoger Quadros default: 94755efaddeSRoger Quadros printf("Invalid Controller Index\n"); 94855efaddeSRoger Quadros } 94955efaddeSRoger Quadros #endif 95055efaddeSRoger Quadros disable_usb_clocks(index); 95155efaddeSRoger Quadros return 0; 95255efaddeSRoger Quadros } 95355efaddeSRoger Quadros #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 95474cc8b09SKipisz, Steven 95574cc8b09SKipisz, Steven #ifdef CONFIG_DRIVER_TI_CPSW 95674cc8b09SKipisz, Steven 95774cc8b09SKipisz, Steven /* Delay value to add to calibrated value */ 95874cc8b09SKipisz, Steven #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 95974cc8b09SKipisz, Steven #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 96074cc8b09SKipisz, Steven #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 96174cc8b09SKipisz, Steven #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 96274cc8b09SKipisz, Steven #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 96374cc8b09SKipisz, Steven #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 96474cc8b09SKipisz, Steven #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 96574cc8b09SKipisz, Steven #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 96674cc8b09SKipisz, Steven #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 96774cc8b09SKipisz, Steven #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 96874cc8b09SKipisz, Steven 96974cc8b09SKipisz, Steven static void cpsw_control(int enabled) 97074cc8b09SKipisz, Steven { 97174cc8b09SKipisz, Steven /* VTP can be added here */ 97274cc8b09SKipisz, Steven } 97374cc8b09SKipisz, Steven 97474cc8b09SKipisz, Steven static struct cpsw_slave_data cpsw_slaves[] = { 97574cc8b09SKipisz, Steven { 97674cc8b09SKipisz, Steven .slave_reg_ofs = 0x208, 97774cc8b09SKipisz, Steven .sliver_reg_ofs = 0xd80, 97874cc8b09SKipisz, Steven .phy_addr = 1, 97974cc8b09SKipisz, Steven }, 98074cc8b09SKipisz, Steven { 98174cc8b09SKipisz, Steven .slave_reg_ofs = 0x308, 98274cc8b09SKipisz, Steven .sliver_reg_ofs = 0xdc0, 98374cc8b09SKipisz, Steven .phy_addr = 2, 98474cc8b09SKipisz, Steven }, 98574cc8b09SKipisz, Steven }; 98674cc8b09SKipisz, Steven 98774cc8b09SKipisz, Steven static struct cpsw_platform_data cpsw_data = { 98874cc8b09SKipisz, Steven .mdio_base = CPSW_MDIO_BASE, 98974cc8b09SKipisz, Steven .cpsw_base = CPSW_BASE, 99074cc8b09SKipisz, Steven .mdio_div = 0xff, 99174cc8b09SKipisz, Steven .channels = 8, 99274cc8b09SKipisz, Steven .cpdma_reg_ofs = 0x800, 99374cc8b09SKipisz, Steven .slaves = 1, 99474cc8b09SKipisz, Steven .slave_data = cpsw_slaves, 99574cc8b09SKipisz, Steven .ale_reg_ofs = 0xd00, 99674cc8b09SKipisz, Steven .ale_entries = 1024, 99774cc8b09SKipisz, Steven .host_port_reg_ofs = 0x108, 99874cc8b09SKipisz, Steven .hw_stats_reg_ofs = 0x900, 99974cc8b09SKipisz, Steven .bd_ram_ofs = 0x2000, 100074cc8b09SKipisz, Steven .mac_control = (1 << 5), 100174cc8b09SKipisz, Steven .control = cpsw_control, 100274cc8b09SKipisz, Steven .host_port_num = 0, 100374cc8b09SKipisz, Steven .version = CPSW_CTRL_VERSION_2, 100474cc8b09SKipisz, Steven }; 100574cc8b09SKipisz, Steven 100692667e89SRoger Quadros static u64 mac_to_u64(u8 mac[6]) 100792667e89SRoger Quadros { 100892667e89SRoger Quadros int i; 100992667e89SRoger Quadros u64 addr = 0; 101092667e89SRoger Quadros 101192667e89SRoger Quadros for (i = 0; i < 6; i++) { 101292667e89SRoger Quadros addr <<= 8; 101392667e89SRoger Quadros addr |= mac[i]; 101492667e89SRoger Quadros } 101592667e89SRoger Quadros 101692667e89SRoger Quadros return addr; 101792667e89SRoger Quadros } 101892667e89SRoger Quadros 101992667e89SRoger Quadros static void u64_to_mac(u64 addr, u8 mac[6]) 102092667e89SRoger Quadros { 102192667e89SRoger Quadros mac[5] = addr; 102292667e89SRoger Quadros mac[4] = addr >> 8; 102392667e89SRoger Quadros mac[3] = addr >> 16; 102492667e89SRoger Quadros mac[2] = addr >> 24; 102592667e89SRoger Quadros mac[1] = addr >> 32; 102692667e89SRoger Quadros mac[0] = addr >> 40; 102792667e89SRoger Quadros } 102892667e89SRoger Quadros 102974cc8b09SKipisz, Steven int board_eth_init(bd_t *bis) 103074cc8b09SKipisz, Steven { 103174cc8b09SKipisz, Steven int ret; 103274cc8b09SKipisz, Steven uint8_t mac_addr[6]; 103374cc8b09SKipisz, Steven uint32_t mac_hi, mac_lo; 103474cc8b09SKipisz, Steven uint32_t ctrl_val; 103592667e89SRoger Quadros int i; 103692667e89SRoger Quadros u64 mac1, mac2; 103792667e89SRoger Quadros u8 mac_addr1[6], mac_addr2[6]; 103892667e89SRoger Quadros int num_macs; 103974cc8b09SKipisz, Steven 104074cc8b09SKipisz, Steven /* try reading mac address from efuse */ 104174cc8b09SKipisz, Steven mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 104274cc8b09SKipisz, Steven mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 104374cc8b09SKipisz, Steven mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 104474cc8b09SKipisz, Steven mac_addr[1] = (mac_hi & 0xFF00) >> 8; 104574cc8b09SKipisz, Steven mac_addr[2] = mac_hi & 0xFF; 104674cc8b09SKipisz, Steven mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 104774cc8b09SKipisz, Steven mac_addr[4] = (mac_lo & 0xFF00) >> 8; 104874cc8b09SKipisz, Steven mac_addr[5] = mac_lo & 0xFF; 104974cc8b09SKipisz, Steven 105000caae6dSSimon Glass if (!env_get("ethaddr")) { 105174cc8b09SKipisz, Steven printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 105274cc8b09SKipisz, Steven 105374cc8b09SKipisz, Steven if (is_valid_ethaddr(mac_addr)) 1054fd1e959eSSimon Glass eth_env_set_enetaddr("ethaddr", mac_addr); 105574cc8b09SKipisz, Steven } 105674cc8b09SKipisz, Steven 105774cc8b09SKipisz, Steven mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 105874cc8b09SKipisz, Steven mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 105974cc8b09SKipisz, Steven mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 106074cc8b09SKipisz, Steven mac_addr[1] = (mac_hi & 0xFF00) >> 8; 106174cc8b09SKipisz, Steven mac_addr[2] = mac_hi & 0xFF; 106274cc8b09SKipisz, Steven mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 106374cc8b09SKipisz, Steven mac_addr[4] = (mac_lo & 0xFF00) >> 8; 106474cc8b09SKipisz, Steven mac_addr[5] = mac_lo & 0xFF; 106574cc8b09SKipisz, Steven 106600caae6dSSimon Glass if (!env_get("eth1addr")) { 106774cc8b09SKipisz, Steven if (is_valid_ethaddr(mac_addr)) 1068fd1e959eSSimon Glass eth_env_set_enetaddr("eth1addr", mac_addr); 106974cc8b09SKipisz, Steven } 107074cc8b09SKipisz, Steven 107174cc8b09SKipisz, Steven ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 107274cc8b09SKipisz, Steven ctrl_val |= 0x22; 107374cc8b09SKipisz, Steven writel(ctrl_val, (*ctrl)->control_core_control_io1); 107474cc8b09SKipisz, Steven 10754d8397c6SSteve Kipisz /* The phy address for the AM57xx IDK are different than x15 */ 107610f430f3SLokesh Vutla if (board_is_am572x_idk() || board_is_am571x_idk() || 107710f430f3SLokesh Vutla board_is_am574x_idk()) { 1078c020d355SSteve Kipisz cpsw_data.slave_data[0].phy_addr = 0; 1079c020d355SSteve Kipisz cpsw_data.slave_data[1].phy_addr = 1; 1080c020d355SSteve Kipisz } 1081c020d355SSteve Kipisz 108274cc8b09SKipisz, Steven ret = cpsw_register(&cpsw_data); 108374cc8b09SKipisz, Steven if (ret < 0) 108474cc8b09SKipisz, Steven printf("Error %d registering CPSW switch\n", ret); 108574cc8b09SKipisz, Steven 108692667e89SRoger Quadros /* 108792667e89SRoger Quadros * Export any Ethernet MAC addresses from EEPROM. 108892667e89SRoger Quadros * On AM57xx the 2 MAC addresses define the address range 108992667e89SRoger Quadros */ 109092667e89SRoger Quadros board_ti_get_eth_mac_addr(0, mac_addr1); 109192667e89SRoger Quadros board_ti_get_eth_mac_addr(1, mac_addr2); 109292667e89SRoger Quadros 109392667e89SRoger Quadros if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { 109492667e89SRoger Quadros mac1 = mac_to_u64(mac_addr1); 109592667e89SRoger Quadros mac2 = mac_to_u64(mac_addr2); 109692667e89SRoger Quadros 109792667e89SRoger Quadros /* must contain an address range */ 109892667e89SRoger Quadros num_macs = mac2 - mac1 + 1; 109992667e89SRoger Quadros /* <= 50 to protect against user programming error */ 110092667e89SRoger Quadros if (num_macs > 0 && num_macs <= 50) { 110192667e89SRoger Quadros for (i = 0; i < num_macs; i++) { 110292667e89SRoger Quadros u64_to_mac(mac1 + i, mac_addr); 110392667e89SRoger Quadros if (is_valid_ethaddr(mac_addr)) { 1104fd1e959eSSimon Glass eth_env_set_enetaddr_by_index("eth", 110592667e89SRoger Quadros i + 2, 110692667e89SRoger Quadros mac_addr); 110792667e89SRoger Quadros } 110892667e89SRoger Quadros } 110992667e89SRoger Quadros } 111092667e89SRoger Quadros } 111192667e89SRoger Quadros 111274cc8b09SKipisz, Steven return ret; 111374cc8b09SKipisz, Steven } 111474cc8b09SKipisz, Steven #endif 111574cc8b09SKipisz, Steven 111674cc8b09SKipisz, Steven #ifdef CONFIG_BOARD_EARLY_INIT_F 111774cc8b09SKipisz, Steven /* VTT regulator enable */ 111874cc8b09SKipisz, Steven static inline void vtt_regulator_enable(void) 111974cc8b09SKipisz, Steven { 112074cc8b09SKipisz, Steven if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 112174cc8b09SKipisz, Steven return; 112274cc8b09SKipisz, Steven 112374cc8b09SKipisz, Steven gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 112474cc8b09SKipisz, Steven gpio_direction_output(GPIO_DDR_VTT_EN, 1); 112574cc8b09SKipisz, Steven } 112674cc8b09SKipisz, Steven 112774cc8b09SKipisz, Steven int board_early_init_f(void) 112874cc8b09SKipisz, Steven { 112974cc8b09SKipisz, Steven vtt_regulator_enable(); 113074cc8b09SKipisz, Steven return 0; 113174cc8b09SKipisz, Steven } 113274cc8b09SKipisz, Steven #endif 113362a09f05SDaniel Allred 113462a09f05SDaniel Allred #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 113562a09f05SDaniel Allred int ft_board_setup(void *blob, bd_t *bd) 113662a09f05SDaniel Allred { 113762a09f05SDaniel Allred ft_cpu_setup(blob, bd); 113862a09f05SDaniel Allred 113962a09f05SDaniel Allred return 0; 114062a09f05SDaniel Allred } 114162a09f05SDaniel Allred #endif 11427a0ea589SLokesh Vutla 11437a0ea589SLokesh Vutla #ifdef CONFIG_SPL_LOAD_FIT 11447a0ea589SLokesh Vutla int board_fit_config_name_match(const char *name) 11457a0ea589SLokesh Vutla { 1146f7f9f6beSLokesh Vutla if (board_is_x15()) { 1147f7f9f6beSLokesh Vutla if (board_is_x15_revb1()) { 1148f7f9f6beSLokesh Vutla if (!strcmp(name, "am57xx-beagle-x15-revb1")) 11497a0ea589SLokesh Vutla return 0; 11508b2551a4SLokesh Vutla } else if (board_is_x15_revc()) { 11518b2551a4SLokesh Vutla if (!strcmp(name, "am57xx-beagle-x15-revc")) 11528b2551a4SLokesh Vutla return 0; 1153f7f9f6beSLokesh Vutla } else if (!strcmp(name, "am57xx-beagle-x15")) { 11547a0ea589SLokesh Vutla return 0; 1155f7f9f6beSLokesh Vutla } 1156f7f9f6beSLokesh Vutla } else if (board_is_am572x_evm() && 1157f7f9f6beSLokesh Vutla !strcmp(name, "am57xx-beagle-x15")) { 1158332dddc6SSchuyler Patton return 0; 1159f7f9f6beSLokesh Vutla } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) { 1160f7f9f6beSLokesh Vutla return 0; 1161b4185e4fSLokesh Vutla } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) { 1162b4185e4fSLokesh Vutla return 0; 116345e7f7e7SSchuyler Patton } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) { 116445e7f7e7SSchuyler Patton return 0; 1165f7f9f6beSLokesh Vutla } 1166f7f9f6beSLokesh Vutla 11677a0ea589SLokesh Vutla return -1; 11687a0ea589SLokesh Vutla } 11697a0ea589SLokesh Vutla #endif 117017c29873SAndreas Dannenberg 117117c29873SAndreas Dannenberg #ifdef CONFIG_TI_SECURE_DEVICE 117217c29873SAndreas Dannenberg void board_fit_image_post_process(void **p_image, size_t *p_size) 117317c29873SAndreas Dannenberg { 117417c29873SAndreas Dannenberg secure_boot_verify_image(p_image, p_size); 117517c29873SAndreas Dannenberg } 11761b597adaSAndrew F. Davis 11771b597adaSAndrew F. Davis void board_tee_image_process(ulong tee_image, size_t tee_size) 11781b597adaSAndrew F. Davis { 11791b597adaSAndrew F. Davis secure_tee_install((u32)tee_image); 11801b597adaSAndrew F. Davis } 11811b597adaSAndrew F. Davis 11821b597adaSAndrew F. Davis U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 118317c29873SAndreas Dannenberg #endif 1184