174cc8b09SKipisz, Steven /* 274cc8b09SKipisz, Steven * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com 374cc8b09SKipisz, Steven * 474cc8b09SKipisz, Steven * Author: Felipe Balbi <balbi@ti.com> 574cc8b09SKipisz, Steven * 674cc8b09SKipisz, Steven * Based on board/ti/dra7xx/evm.c 774cc8b09SKipisz, Steven * 874cc8b09SKipisz, Steven * SPDX-License-Identifier: GPL-2.0+ 974cc8b09SKipisz, Steven */ 1074cc8b09SKipisz, Steven 1174cc8b09SKipisz, Steven #include <common.h> 1274cc8b09SKipisz, Steven #include <palmas.h> 1374cc8b09SKipisz, Steven #include <sata.h> 1474cc8b09SKipisz, Steven #include <usb.h> 1574cc8b09SKipisz, Steven #include <asm/omap_common.h> 1617c29873SAndreas Dannenberg #include <asm/omap_sec_common.h> 1774cc8b09SKipisz, Steven #include <asm/emif.h> 1874cc8b09SKipisz, Steven #include <asm/gpio.h> 1974cc8b09SKipisz, Steven #include <asm/arch/gpio.h> 2074cc8b09SKipisz, Steven #include <asm/arch/clock.h> 2174cc8b09SKipisz, Steven #include <asm/arch/dra7xx_iodelay.h> 2274cc8b09SKipisz, Steven #include <asm/arch/sys_proto.h> 2374cc8b09SKipisz, Steven #include <asm/arch/mmc_host_def.h> 2474cc8b09SKipisz, Steven #include <asm/arch/sata.h> 2574cc8b09SKipisz, Steven #include <asm/arch/gpio.h> 2674cc8b09SKipisz, Steven #include <asm/arch/omap.h> 2774cc8b09SKipisz, Steven #include <environment.h> 2874cc8b09SKipisz, Steven #include <usb.h> 2974cc8b09SKipisz, Steven #include <linux/usb/gadget.h> 3074cc8b09SKipisz, Steven #include <dwc3-uboot.h> 3174cc8b09SKipisz, Steven #include <dwc3-omap-uboot.h> 3274cc8b09SKipisz, Steven #include <ti-usb-phy-uboot.h> 3374cc8b09SKipisz, Steven 34212f96f6SKipisz, Steven #include "../common/board_detect.h" 3574cc8b09SKipisz, Steven #include "mux_data.h" 3674cc8b09SKipisz, Steven 37212f96f6SKipisz, Steven #define board_is_x15() board_ti_is("BBRDX15_") 38f7f9f6beSLokesh Vutla #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \ 3970879224SLokesh Vutla !strncmp("B.10", board_ti_get_rev(), 3)) 40f70a4272SLokesh Vutla #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \ 41f70a4272SLokesh Vutla !strncmp("C.00", board_ti_get_rev(), 3)) 42212f96f6SKipisz, Steven #define board_is_am572x_evm() board_ti_is("AM572PM_") 43bf43ce6cSNishanth Menon #define board_is_am572x_evm_reva3() \ 44bf43ce6cSNishanth Menon (board_ti_is("AM572PM_") && \ 4570879224SLokesh Vutla !strncmp("A.30", board_ti_get_rev(), 3)) 469646b95fSLokesh Vutla #define board_is_am574x_idk() board_ti_is("AM574IDK") 47c020d355SSteve Kipisz #define board_is_am572x_idk() board_ti_is("AM572IDK") 484d8397c6SSteve Kipisz #define board_is_am571x_idk() board_ti_is("AM571IDK") 49212f96f6SKipisz, Steven 5074cc8b09SKipisz, Steven #ifdef CONFIG_DRIVER_TI_CPSW 5174cc8b09SKipisz, Steven #include <cpsw.h> 5274cc8b09SKipisz, Steven #endif 5374cc8b09SKipisz, Steven 5474cc8b09SKipisz, Steven DECLARE_GLOBAL_DATA_PTR; 5574cc8b09SKipisz, Steven 5637611052SRoger Quadros #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22) 5774cc8b09SKipisz, Steven /* GPIO 7_11 */ 5874cc8b09SKipisz, Steven #define GPIO_DDR_VTT_EN 203 5974cc8b09SKipisz, Steven 60fcb18524SNishanth Menon /* Touch screen controller to identify the LCD */ 61fcb18524SNishanth Menon #define OSD_TS_FT_BUS_ADDRESS 0 62fcb18524SNishanth Menon #define OSD_TS_FT_CHIP_ADDRESS 0x38 63fcb18524SNishanth Menon #define OSD_TS_FT_REG_ID 0xA3 64fcb18524SNishanth Menon /* 65fcb18524SNishanth Menon * Touchscreen IDs for various OSD panels 66fcb18524SNishanth Menon * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf 67fcb18524SNishanth Menon */ 68fcb18524SNishanth Menon /* Used on newer osd101t2587 Panels */ 69fcb18524SNishanth Menon #define OSD_TS_FT_ID_5x46 0x54 70fcb18524SNishanth Menon /* Used on older osd101t2045 Panels */ 71fcb18524SNishanth Menon #define OSD_TS_FT_ID_5606 0x08 72fcb18524SNishanth Menon 73212f96f6SKipisz, Steven #define SYSINFO_BOARD_NAME_MAX_LEN 45 74212f96f6SKipisz, Steven 75385d3632SKeerthy #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB 76385d3632SKeerthy #define TPS65903X_PAD2_POWERHOLD_MASK 0x20 77385d3632SKeerthy 7874cc8b09SKipisz, Steven const struct omap_sysinfo sysinfo = { 79212f96f6SKipisz, Steven "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n" 8074cc8b09SKipisz, Steven }; 8174cc8b09SKipisz, Steven 8274cc8b09SKipisz, Steven static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { 8374cc8b09SKipisz, Steven .dmm_lisa_map_3 = 0x80740300, 8474cc8b09SKipisz, Steven .is_ma_present = 0x1 8574cc8b09SKipisz, Steven }; 8674cc8b09SKipisz, Steven 874d8397c6SSteve Kipisz static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { 884d8397c6SSteve Kipisz .dmm_lisa_map_3 = 0x80640100, 894d8397c6SSteve Kipisz .is_ma_present = 0x1 904d8397c6SSteve Kipisz }; 914d8397c6SSteve Kipisz 927b16de85SLokesh Vutla static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = { 937b16de85SLokesh Vutla .dmm_lisa_map_2 = 0xc0600200, 947b16de85SLokesh Vutla .dmm_lisa_map_3 = 0x80600100, 957b16de85SLokesh Vutla .is_ma_present = 0x1 967b16de85SLokesh Vutla }; 977b16de85SLokesh Vutla 9874cc8b09SKipisz, Steven void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 9974cc8b09SKipisz, Steven { 1004d8397c6SSteve Kipisz if (board_is_am571x_idk()) 1014d8397c6SSteve Kipisz *dmm_lisa_regs = &am571x_idk_lisa_regs; 1027b16de85SLokesh Vutla else if (board_is_am574x_idk()) 1037b16de85SLokesh Vutla *dmm_lisa_regs = &am574x_idk_lisa_regs; 1044d8397c6SSteve Kipisz else 10574cc8b09SKipisz, Steven *dmm_lisa_regs = &beagle_x15_lisa_regs; 10674cc8b09SKipisz, Steven } 10774cc8b09SKipisz, Steven 10874cc8b09SKipisz, Steven static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { 10974cc8b09SKipisz, Steven .sdram_config_init = 0x61851b32, 11074cc8b09SKipisz, Steven .sdram_config = 0x61851b32, 11111e2b043SLokesh Vutla .sdram_config2 = 0x08000000, 11274cc8b09SKipisz, Steven .ref_ctrl = 0x000040F1, 11374cc8b09SKipisz, Steven .ref_ctrl_final = 0x00001035, 11411e2b043SLokesh Vutla .sdram_tim1 = 0xcccf36ab, 11511e2b043SLokesh Vutla .sdram_tim2 = 0x308f7fda, 11611e2b043SLokesh Vutla .sdram_tim3 = 0x409f88a8, 11774cc8b09SKipisz, Steven .read_idle_ctrl = 0x00050000, 11811e2b043SLokesh Vutla .zq_config = 0x5007190b, 11974cc8b09SKipisz, Steven .temp_alert_config = 0x00000000, 12074cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1_init = 0x0024400b, 12174cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1 = 0x0e24400b, 12274cc8b09SKipisz, Steven .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 12311e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 12411e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 12511e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 12611e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 12774cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_win = 0x00000000, 12874cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 12974cc8b09SKipisz, Steven .emif_rd_wr_lvl_ctl = 0x00000000, 13074cc8b09SKipisz, Steven .emif_rd_wr_exec_thresh = 0x00000305 13174cc8b09SKipisz, Steven }; 13274cc8b09SKipisz, Steven 13374cc8b09SKipisz, Steven /* Ext phy ctrl regs 1-35 */ 13474cc8b09SKipisz, Steven static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 13574cc8b09SKipisz, Steven 0x10040100, 13611e2b043SLokesh Vutla 0x00910091, 13711e2b043SLokesh Vutla 0x00950095, 13811e2b043SLokesh Vutla 0x009B009B, 13911e2b043SLokesh Vutla 0x009E009E, 14011e2b043SLokesh Vutla 0x00980098, 14174cc8b09SKipisz, Steven 0x00340034, 14274cc8b09SKipisz, Steven 0x00350035, 14311e2b043SLokesh Vutla 0x00340034, 14411e2b043SLokesh Vutla 0x00310031, 14511e2b043SLokesh Vutla 0x00340034, 14611e2b043SLokesh Vutla 0x007F007F, 14711e2b043SLokesh Vutla 0x007F007F, 14811e2b043SLokesh Vutla 0x007F007F, 14911e2b043SLokesh Vutla 0x007F007F, 15011e2b043SLokesh Vutla 0x007F007F, 15111e2b043SLokesh Vutla 0x00480048, 15211e2b043SLokesh Vutla 0x004A004A, 15311e2b043SLokesh Vutla 0x00520052, 15411e2b043SLokesh Vutla 0x00550055, 15511e2b043SLokesh Vutla 0x00500050, 15674cc8b09SKipisz, Steven 0x00000000, 15774cc8b09SKipisz, Steven 0x00600020, 15874cc8b09SKipisz, Steven 0x40011080, 15974cc8b09SKipisz, Steven 0x08102040, 16011e2b043SLokesh Vutla 0x0, 16111e2b043SLokesh Vutla 0x0, 16211e2b043SLokesh Vutla 0x0, 16311e2b043SLokesh Vutla 0x0, 16411e2b043SLokesh Vutla 0x0, 16574cc8b09SKipisz, Steven 0x0, 16674cc8b09SKipisz, Steven 0x0, 16774cc8b09SKipisz, Steven 0x0, 16874cc8b09SKipisz, Steven 0x0, 16974cc8b09SKipisz, Steven 0x0 17074cc8b09SKipisz, Steven }; 17174cc8b09SKipisz, Steven 17274cc8b09SKipisz, Steven static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { 17374cc8b09SKipisz, Steven .sdram_config_init = 0x61851b32, 17474cc8b09SKipisz, Steven .sdram_config = 0x61851b32, 17511e2b043SLokesh Vutla .sdram_config2 = 0x08000000, 17674cc8b09SKipisz, Steven .ref_ctrl = 0x000040F1, 17774cc8b09SKipisz, Steven .ref_ctrl_final = 0x00001035, 1785f405e7fSSchuyler Patton .sdram_tim1 = 0xcccf36b3, 17911e2b043SLokesh Vutla .sdram_tim2 = 0x308f7fda, 1805f405e7fSSchuyler Patton .sdram_tim3 = 0x407f88a8, 18174cc8b09SKipisz, Steven .read_idle_ctrl = 0x00050000, 18211e2b043SLokesh Vutla .zq_config = 0x5007190b, 18374cc8b09SKipisz, Steven .temp_alert_config = 0x00000000, 18474cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1_init = 0x0024400b, 18574cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1 = 0x0e24400b, 18674cc8b09SKipisz, Steven .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 18711e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 18811e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 18911e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 19011e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 19174cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_win = 0x00000000, 19274cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 19374cc8b09SKipisz, Steven .emif_rd_wr_lvl_ctl = 0x00000000, 19474cc8b09SKipisz, Steven .emif_rd_wr_exec_thresh = 0x00000305 19574cc8b09SKipisz, Steven }; 19674cc8b09SKipisz, Steven 19774cc8b09SKipisz, Steven static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 19874cc8b09SKipisz, Steven 0x10040100, 19911e2b043SLokesh Vutla 0x00910091, 20011e2b043SLokesh Vutla 0x00950095, 20111e2b043SLokesh Vutla 0x009B009B, 20211e2b043SLokesh Vutla 0x009E009E, 20311e2b043SLokesh Vutla 0x00980098, 20411e2b043SLokesh Vutla 0x00340034, 20574cc8b09SKipisz, Steven 0x00350035, 20611e2b043SLokesh Vutla 0x00340034, 20711e2b043SLokesh Vutla 0x00310031, 20811e2b043SLokesh Vutla 0x00340034, 20911e2b043SLokesh Vutla 0x007F007F, 21011e2b043SLokesh Vutla 0x007F007F, 21111e2b043SLokesh Vutla 0x007F007F, 21211e2b043SLokesh Vutla 0x007F007F, 21311e2b043SLokesh Vutla 0x007F007F, 21411e2b043SLokesh Vutla 0x00480048, 21511e2b043SLokesh Vutla 0x004A004A, 21611e2b043SLokesh Vutla 0x00520052, 21711e2b043SLokesh Vutla 0x00550055, 21811e2b043SLokesh Vutla 0x00500050, 21974cc8b09SKipisz, Steven 0x00000000, 22074cc8b09SKipisz, Steven 0x00600020, 22174cc8b09SKipisz, Steven 0x40011080, 22274cc8b09SKipisz, Steven 0x08102040, 22311e2b043SLokesh Vutla 0x0, 22411e2b043SLokesh Vutla 0x0, 22511e2b043SLokesh Vutla 0x0, 22611e2b043SLokesh Vutla 0x0, 22711e2b043SLokesh Vutla 0x0, 22874cc8b09SKipisz, Steven 0x0, 22974cc8b09SKipisz, Steven 0x0, 23074cc8b09SKipisz, Steven 0x0, 23174cc8b09SKipisz, Steven 0x0, 23274cc8b09SKipisz, Steven 0x0 23374cc8b09SKipisz, Steven }; 23474cc8b09SKipisz, Steven 235209742faSSteve Kipisz static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { 236209742faSSteve Kipisz .sdram_config_init = 0x61863332, 237209742faSSteve Kipisz .sdram_config = 0x61863332, 238209742faSSteve Kipisz .sdram_config2 = 0x08000000, 239209742faSSteve Kipisz .ref_ctrl = 0x0000514d, 240209742faSSteve Kipisz .ref_ctrl_final = 0x0000144a, 241209742faSSteve Kipisz .sdram_tim1 = 0xd333887c, 2427b16de85SLokesh Vutla .sdram_tim2 = 0x30b37fe3, 2437b16de85SLokesh Vutla .sdram_tim3 = 0x409f8ad8, 244209742faSSteve Kipisz .read_idle_ctrl = 0x00050000, 245209742faSSteve Kipisz .zq_config = 0x5007190b, 246209742faSSteve Kipisz .temp_alert_config = 0x00000000, 247209742faSSteve Kipisz .emif_ddr_phy_ctlr_1_init = 0x0024400f, 248209742faSSteve Kipisz .emif_ddr_phy_ctlr_1 = 0x0e24400f, 249209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 250209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 251209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 252209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 253209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 254209742faSSteve Kipisz .emif_rd_wr_lvl_rmp_win = 0x00000000, 255209742faSSteve Kipisz .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 256209742faSSteve Kipisz .emif_rd_wr_lvl_ctl = 0x00000000, 257209742faSSteve Kipisz .emif_rd_wr_exec_thresh = 0x00000305 258209742faSSteve Kipisz }; 259209742faSSteve Kipisz 2607b16de85SLokesh Vutla static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = { 2617b16de85SLokesh Vutla .sdram_config_init = 0x61863332, 2627b16de85SLokesh Vutla .sdram_config = 0x61863332, 2637b16de85SLokesh Vutla .sdram_config2 = 0x08000000, 2647b16de85SLokesh Vutla .ref_ctrl = 0x0000514d, 2657b16de85SLokesh Vutla .ref_ctrl_final = 0x0000144a, 2667b16de85SLokesh Vutla .sdram_tim1 = 0xd333887c, 2677b16de85SLokesh Vutla .sdram_tim2 = 0x30b37fe3, 2687b16de85SLokesh Vutla .sdram_tim3 = 0x409f8ad8, 2697b16de85SLokesh Vutla .read_idle_ctrl = 0x00050000, 2707b16de85SLokesh Vutla .zq_config = 0x5007190b, 2717b16de85SLokesh Vutla .temp_alert_config = 0x00000000, 2727b16de85SLokesh Vutla .emif_ddr_phy_ctlr_1_init = 0x0024400f, 2737b16de85SLokesh Vutla .emif_ddr_phy_ctlr_1 = 0x0e24400f, 2747b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 2757b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 2767b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 2777b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, 2787b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, 2797b16de85SLokesh Vutla .emif_rd_wr_lvl_rmp_win = 0x00000000, 2807b16de85SLokesh Vutla .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 2817b16de85SLokesh Vutla .emif_rd_wr_lvl_ctl = 0x00000000, 2827b16de85SLokesh Vutla .emif_rd_wr_exec_thresh = 0x00000305, 2837b16de85SLokesh Vutla .emif_ecc_ctrl_reg = 0xD0000001, 2847b16de85SLokesh Vutla .emif_ecc_address_range_1 = 0x3FFF0000, 2857b16de85SLokesh Vutla .emif_ecc_address_range_2 = 0x00000000 2867b16de85SLokesh Vutla }; 2877b16de85SLokesh Vutla 28874cc8b09SKipisz, Steven void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 28974cc8b09SKipisz, Steven { 29074cc8b09SKipisz, Steven switch (emif_nr) { 29174cc8b09SKipisz, Steven case 1: 292209742faSSteve Kipisz if (board_is_am571x_idk()) 293209742faSSteve Kipisz *regs = &am571x_emif1_ddr3_666mhz_emif_regs; 2947b16de85SLokesh Vutla else if (board_is_am574x_idk()) 2957b16de85SLokesh Vutla *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs; 296209742faSSteve Kipisz else 29774cc8b09SKipisz, Steven *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; 29874cc8b09SKipisz, Steven break; 29974cc8b09SKipisz, Steven case 2: 3007b16de85SLokesh Vutla if (board_is_am574x_idk()) 3017b16de85SLokesh Vutla *regs = &am571x_emif1_ddr3_666mhz_emif_regs; 3027b16de85SLokesh Vutla else 30374cc8b09SKipisz, Steven *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; 30474cc8b09SKipisz, Steven break; 30574cc8b09SKipisz, Steven } 30674cc8b09SKipisz, Steven } 30774cc8b09SKipisz, Steven 30874cc8b09SKipisz, Steven void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) 30974cc8b09SKipisz, Steven { 31074cc8b09SKipisz, Steven switch (emif_nr) { 31174cc8b09SKipisz, Steven case 1: 31274cc8b09SKipisz, Steven *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; 31374cc8b09SKipisz, Steven *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); 31474cc8b09SKipisz, Steven break; 31574cc8b09SKipisz, Steven case 2: 31674cc8b09SKipisz, Steven *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; 31774cc8b09SKipisz, Steven *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); 31874cc8b09SKipisz, Steven break; 31974cc8b09SKipisz, Steven } 32074cc8b09SKipisz, Steven } 32174cc8b09SKipisz, Steven 32274cc8b09SKipisz, Steven struct vcores_data beagle_x15_volts = { 323beb71279SLokesh Vutla .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 324beb71279SLokesh Vutla .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 32574cc8b09SKipisz, Steven .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 32674cc8b09SKipisz, Steven .mpu.addr = TPS659038_REG_ADDR_SMPS12, 32774cc8b09SKipisz, Steven .mpu.pmic = &tps659038, 3283708e78cSNishanth Menon .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 32974cc8b09SKipisz, Steven 330beb71279SLokesh Vutla .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 331beb71279SLokesh Vutla .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 332beb71279SLokesh Vutla .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 333beb71279SLokesh Vutla .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 334beb71279SLokesh Vutla .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 335beb71279SLokesh Vutla .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 33674cc8b09SKipisz, Steven .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 33774cc8b09SKipisz, Steven .eve.addr = TPS659038_REG_ADDR_SMPS45, 33874cc8b09SKipisz, Steven .eve.pmic = &tps659038, 339e52e334eSNishanth Menon .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 34074cc8b09SKipisz, Steven 341beb71279SLokesh Vutla .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 342beb71279SLokesh Vutla .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 343beb71279SLokesh Vutla .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 344beb71279SLokesh Vutla .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 345beb71279SLokesh Vutla .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 346beb71279SLokesh Vutla .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 34774cc8b09SKipisz, Steven .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 34874cc8b09SKipisz, Steven .gpu.addr = TPS659038_REG_ADDR_SMPS45, 34974cc8b09SKipisz, Steven .gpu.pmic = &tps659038, 350e52e334eSNishanth Menon .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 35174cc8b09SKipisz, Steven 352beb71279SLokesh Vutla .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 353beb71279SLokesh Vutla .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 35474cc8b09SKipisz, Steven .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 35574cc8b09SKipisz, Steven .core.addr = TPS659038_REG_ADDR_SMPS6, 35674cc8b09SKipisz, Steven .core.pmic = &tps659038, 35774cc8b09SKipisz, Steven 358beb71279SLokesh Vutla .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 359beb71279SLokesh Vutla .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 360beb71279SLokesh Vutla .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 361beb71279SLokesh Vutla .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 362beb71279SLokesh Vutla .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 363beb71279SLokesh Vutla .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 36474cc8b09SKipisz, Steven .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 36574cc8b09SKipisz, Steven .iva.addr = TPS659038_REG_ADDR_SMPS45, 36674cc8b09SKipisz, Steven .iva.pmic = &tps659038, 367e52e334eSNishanth Menon .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 36874cc8b09SKipisz, Steven }; 36974cc8b09SKipisz, Steven 370d60198daSKeerthy struct vcores_data am572x_idk_volts = { 371beb71279SLokesh Vutla .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 372beb71279SLokesh Vutla .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 373d60198daSKeerthy .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 374d60198daSKeerthy .mpu.addr = TPS659038_REG_ADDR_SMPS12, 375d60198daSKeerthy .mpu.pmic = &tps659038, 376d60198daSKeerthy .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 377d60198daSKeerthy 378beb71279SLokesh Vutla .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 379beb71279SLokesh Vutla .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 380beb71279SLokesh Vutla .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 381beb71279SLokesh Vutla .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 382beb71279SLokesh Vutla .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 383beb71279SLokesh Vutla .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 384d60198daSKeerthy .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 385d60198daSKeerthy .eve.addr = TPS659038_REG_ADDR_SMPS45, 386d60198daSKeerthy .eve.pmic = &tps659038, 387d60198daSKeerthy .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 388d60198daSKeerthy 389beb71279SLokesh Vutla .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 390beb71279SLokesh Vutla .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 391beb71279SLokesh Vutla .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 392beb71279SLokesh Vutla .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 393beb71279SLokesh Vutla .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 394beb71279SLokesh Vutla .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 395d60198daSKeerthy .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 396d60198daSKeerthy .gpu.addr = TPS659038_REG_ADDR_SMPS6, 397d60198daSKeerthy .gpu.pmic = &tps659038, 398d60198daSKeerthy .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 399d60198daSKeerthy 400beb71279SLokesh Vutla .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 401beb71279SLokesh Vutla .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 402d60198daSKeerthy .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 403d60198daSKeerthy .core.addr = TPS659038_REG_ADDR_SMPS7, 404d60198daSKeerthy .core.pmic = &tps659038, 405d60198daSKeerthy 406beb71279SLokesh Vutla .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 407beb71279SLokesh Vutla .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 408beb71279SLokesh Vutla .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 409beb71279SLokesh Vutla .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 410beb71279SLokesh Vutla .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 411beb71279SLokesh Vutla .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 412d60198daSKeerthy .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 413d60198daSKeerthy .iva.addr = TPS659038_REG_ADDR_SMPS8, 414d60198daSKeerthy .iva.pmic = &tps659038, 415d60198daSKeerthy .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 416d60198daSKeerthy }; 417d60198daSKeerthy 418b12550ebSKeerthy struct vcores_data am571x_idk_volts = { 419b12550ebSKeerthy .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 420b12550ebSKeerthy .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 421b12550ebSKeerthy .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 422b12550ebSKeerthy .mpu.addr = TPS659038_REG_ADDR_SMPS12, 423b12550ebSKeerthy .mpu.pmic = &tps659038, 424b12550ebSKeerthy .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 425b12550ebSKeerthy 426b12550ebSKeerthy .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 427b12550ebSKeerthy .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 428b12550ebSKeerthy .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 429b12550ebSKeerthy .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 430b12550ebSKeerthy .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 431b12550ebSKeerthy .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 432b12550ebSKeerthy .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 433b12550ebSKeerthy .eve.addr = TPS659038_REG_ADDR_SMPS45, 434b12550ebSKeerthy .eve.pmic = &tps659038, 435b12550ebSKeerthy .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 436b12550ebSKeerthy 437b12550ebSKeerthy .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 438b12550ebSKeerthy .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 439b12550ebSKeerthy .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 440b12550ebSKeerthy .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 441b12550ebSKeerthy .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 442b12550ebSKeerthy .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 443b12550ebSKeerthy .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 444b12550ebSKeerthy .gpu.addr = TPS659038_REG_ADDR_SMPS6, 445b12550ebSKeerthy .gpu.pmic = &tps659038, 446b12550ebSKeerthy .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 447b12550ebSKeerthy 448b12550ebSKeerthy .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 449b12550ebSKeerthy .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 450b12550ebSKeerthy .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 451b12550ebSKeerthy .core.addr = TPS659038_REG_ADDR_SMPS7, 452b12550ebSKeerthy .core.pmic = &tps659038, 453b12550ebSKeerthy 454b12550ebSKeerthy .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 455b12550ebSKeerthy .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 456b12550ebSKeerthy .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 457b12550ebSKeerthy .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 458b12550ebSKeerthy .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 459b12550ebSKeerthy .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 460b12550ebSKeerthy .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 461b12550ebSKeerthy .iva.addr = TPS659038_REG_ADDR_SMPS45, 462b12550ebSKeerthy .iva.pmic = &tps659038, 463b12550ebSKeerthy .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 464b12550ebSKeerthy }; 465b12550ebSKeerthy 466beb71279SLokesh Vutla int get_voltrail_opp(int rail_offset) 467beb71279SLokesh Vutla { 468beb71279SLokesh Vutla int opp; 469beb71279SLokesh Vutla 470beb71279SLokesh Vutla switch (rail_offset) { 471beb71279SLokesh Vutla case VOLT_MPU: 472beb71279SLokesh Vutla opp = DRA7_MPU_OPP; 473beb71279SLokesh Vutla break; 474beb71279SLokesh Vutla case VOLT_CORE: 475beb71279SLokesh Vutla opp = DRA7_CORE_OPP; 476beb71279SLokesh Vutla break; 477beb71279SLokesh Vutla case VOLT_GPU: 478beb71279SLokesh Vutla opp = DRA7_GPU_OPP; 479beb71279SLokesh Vutla break; 480beb71279SLokesh Vutla case VOLT_EVE: 481beb71279SLokesh Vutla opp = DRA7_DSPEVE_OPP; 482beb71279SLokesh Vutla break; 483beb71279SLokesh Vutla case VOLT_IVA: 484beb71279SLokesh Vutla opp = DRA7_IVA_OPP; 485beb71279SLokesh Vutla break; 486beb71279SLokesh Vutla default: 487beb71279SLokesh Vutla opp = OPP_NOM; 488beb71279SLokesh Vutla } 489beb71279SLokesh Vutla 490beb71279SLokesh Vutla return opp; 491beb71279SLokesh Vutla } 492beb71279SLokesh Vutla 493beb71279SLokesh Vutla 494212f96f6SKipisz, Steven #ifdef CONFIG_SPL_BUILD 495212f96f6SKipisz, Steven /* No env to setup for SPL */ 496212f96f6SKipisz, Steven static inline void setup_board_eeprom_env(void) { } 497212f96f6SKipisz, Steven 498212f96f6SKipisz, Steven /* Override function to read eeprom information */ 499212f96f6SKipisz, Steven void do_board_detect(void) 500212f96f6SKipisz, Steven { 501212f96f6SKipisz, Steven int rc; 502212f96f6SKipisz, Steven 503212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 504212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS); 505212f96f6SKipisz, Steven if (rc) 506212f96f6SKipisz, Steven printf("ti_i2c_eeprom_init failed %d\n", rc); 507212f96f6SKipisz, Steven } 508212f96f6SKipisz, Steven 509212f96f6SKipisz, Steven #else /* CONFIG_SPL_BUILD */ 510212f96f6SKipisz, Steven 511212f96f6SKipisz, Steven /* Override function to read eeprom information: actual i2c read done by SPL*/ 512212f96f6SKipisz, Steven void do_board_detect(void) 513212f96f6SKipisz, Steven { 514212f96f6SKipisz, Steven char *bname = NULL; 515212f96f6SKipisz, Steven int rc; 516212f96f6SKipisz, Steven 517212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 518212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS); 519212f96f6SKipisz, Steven if (rc) 520212f96f6SKipisz, Steven printf("ti_i2c_eeprom_init failed %d\n", rc); 521212f96f6SKipisz, Steven 522212f96f6SKipisz, Steven if (board_is_x15()) 523212f96f6SKipisz, Steven bname = "BeagleBoard X15"; 524212f96f6SKipisz, Steven else if (board_is_am572x_evm()) 525212f96f6SKipisz, Steven bname = "AM572x EVM"; 5269646b95fSLokesh Vutla else if (board_is_am574x_idk()) 5279646b95fSLokesh Vutla bname = "AM574x IDK"; 528c020d355SSteve Kipisz else if (board_is_am572x_idk()) 529c020d355SSteve Kipisz bname = "AM572x IDK"; 5304d8397c6SSteve Kipisz else if (board_is_am571x_idk()) 5314d8397c6SSteve Kipisz bname = "AM571x IDK"; 532212f96f6SKipisz, Steven 533212f96f6SKipisz, Steven if (bname) 534212f96f6SKipisz, Steven snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 535212f96f6SKipisz, Steven "Board: %s REV %s\n", bname, board_ti_get_rev()); 536212f96f6SKipisz, Steven } 537212f96f6SKipisz, Steven 538212f96f6SKipisz, Steven static void setup_board_eeprom_env(void) 539212f96f6SKipisz, Steven { 540212f96f6SKipisz, Steven char *name = "beagle_x15"; 541212f96f6SKipisz, Steven int rc; 542212f96f6SKipisz, Steven 543212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 544212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS); 545212f96f6SKipisz, Steven if (rc) 546212f96f6SKipisz, Steven goto invalid_eeprom; 547212f96f6SKipisz, Steven 548bf43ce6cSNishanth Menon if (board_is_x15()) { 549f7f9f6beSLokesh Vutla if (board_is_x15_revb1()) 550f7f9f6beSLokesh Vutla name = "beagle_x15_revb1"; 551f70a4272SLokesh Vutla else if (board_is_x15_revc()) 552f70a4272SLokesh Vutla name = "beagle_x15_revc"; 553f7f9f6beSLokesh Vutla else 554c9891660SNishanth Menon name = "beagle_x15"; 555bf43ce6cSNishanth Menon } else if (board_is_am572x_evm()) { 556bf43ce6cSNishanth Menon if (board_is_am572x_evm_reva3()) 557bf43ce6cSNishanth Menon name = "am57xx_evm_reva3"; 558212f96f6SKipisz, Steven else 559bf43ce6cSNishanth Menon name = "am57xx_evm"; 5609646b95fSLokesh Vutla } else if (board_is_am574x_idk()) { 5619646b95fSLokesh Vutla name = "am574x_idk"; 562bf43ce6cSNishanth Menon } else if (board_is_am572x_idk()) { 563bf43ce6cSNishanth Menon name = "am572x_idk"; 5644d8397c6SSteve Kipisz } else if (board_is_am571x_idk()) { 5654d8397c6SSteve Kipisz name = "am571x_idk"; 566bf43ce6cSNishanth Menon } else { 567212f96f6SKipisz, Steven printf("Unidentified board claims %s in eeprom header\n", 568212f96f6SKipisz, Steven board_ti_get_name()); 569bf43ce6cSNishanth Menon } 570212f96f6SKipisz, Steven 571212f96f6SKipisz, Steven invalid_eeprom: 572212f96f6SKipisz, Steven set_board_info_env(name); 573212f96f6SKipisz, Steven } 574212f96f6SKipisz, Steven 575212f96f6SKipisz, Steven #endif /* CONFIG_SPL_BUILD */ 576212f96f6SKipisz, Steven 577d60198daSKeerthy void vcores_init(void) 578d60198daSKeerthy { 57910f430f3SLokesh Vutla if (board_is_am572x_idk() || board_is_am574x_idk()) 580d60198daSKeerthy *omap_vcores = &am572x_idk_volts; 581b12550ebSKeerthy else if (board_is_am571x_idk()) 582b12550ebSKeerthy *omap_vcores = &am571x_idk_volts; 583d60198daSKeerthy else 584d60198daSKeerthy *omap_vcores = &beagle_x15_volts; 585d60198daSKeerthy } 586d60198daSKeerthy 58774cc8b09SKipisz, Steven void hw_data_init(void) 58874cc8b09SKipisz, Steven { 58974cc8b09SKipisz, Steven *prcm = &dra7xx_prcm; 590209742faSSteve Kipisz if (is_dra72x()) 591209742faSSteve Kipisz *dplls_data = &dra72x_dplls; 59210f430f3SLokesh Vutla else if (is_dra76x()) 59310f430f3SLokesh Vutla *dplls_data = &dra76x_dplls; 594209742faSSteve Kipisz else 59574cc8b09SKipisz, Steven *dplls_data = &dra7xx_dplls; 59674cc8b09SKipisz, Steven *ctrl = &dra7xx_ctrl; 59774cc8b09SKipisz, Steven } 59874cc8b09SKipisz, Steven 59937611052SRoger Quadros bool am571x_idk_needs_lcd(void) 60037611052SRoger Quadros { 60137611052SRoger Quadros bool needs_lcd; 60237611052SRoger Quadros 60337611052SRoger Quadros gpio_request(GPIO_ETH_LCD, "nLCD_Detect"); 60437611052SRoger Quadros if (gpio_get_value(GPIO_ETH_LCD)) 60537611052SRoger Quadros needs_lcd = false; 60637611052SRoger Quadros else 60737611052SRoger Quadros needs_lcd = true; 60837611052SRoger Quadros 60937611052SRoger Quadros gpio_free(GPIO_ETH_LCD); 61037611052SRoger Quadros 61137611052SRoger Quadros return needs_lcd; 61237611052SRoger Quadros } 61337611052SRoger Quadros 61474cc8b09SKipisz, Steven int board_init(void) 61574cc8b09SKipisz, Steven { 61674cc8b09SKipisz, Steven gpmc_init(); 61774cc8b09SKipisz, Steven gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 61874cc8b09SKipisz, Steven 61974cc8b09SKipisz, Steven return 0; 62074cc8b09SKipisz, Steven } 62174cc8b09SKipisz, Steven 622fcb18524SNishanth Menon void am57x_idk_lcd_detect(void) 623fcb18524SNishanth Menon { 624fcb18524SNishanth Menon int r = -ENODEV; 625fcb18524SNishanth Menon char *idk_lcd = "no"; 626fcb18524SNishanth Menon uint8_t buf = 0; 627fcb18524SNishanth Menon 628fcb18524SNishanth Menon /* Only valid for IDKs */ 629fcb18524SNishanth Menon if (board_is_x15() || board_is_am572x_evm()) 630fcb18524SNishanth Menon return; 631fcb18524SNishanth Menon 632fcb18524SNishanth Menon /* Only AM571x IDK has gpio control detect.. so check that */ 633fcb18524SNishanth Menon if (board_is_am571x_idk() && !am571x_idk_needs_lcd()) 634fcb18524SNishanth Menon goto out; 635fcb18524SNishanth Menon 636fcb18524SNishanth Menon r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS); 637fcb18524SNishanth Menon if (r) { 638fcb18524SNishanth Menon printf("%s: Failed to set bus address to %d: %d\n", 639fcb18524SNishanth Menon __func__, OSD_TS_FT_BUS_ADDRESS, r); 640fcb18524SNishanth Menon goto out; 641fcb18524SNishanth Menon } 642fcb18524SNishanth Menon r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS); 643fcb18524SNishanth Menon if (r) { 644fcb18524SNishanth Menon /* AM572x IDK has no explicit settings for optional LCD kit */ 645fcb18524SNishanth Menon if (board_is_am571x_idk()) { 646fcb18524SNishanth Menon printf("%s: Touch screen detect failed: %d!\n", 647fcb18524SNishanth Menon __func__, r); 648fcb18524SNishanth Menon } 649fcb18524SNishanth Menon goto out; 650fcb18524SNishanth Menon } 651fcb18524SNishanth Menon 652fcb18524SNishanth Menon /* Read FT ID */ 653fcb18524SNishanth Menon r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1); 654fcb18524SNishanth Menon if (r) { 655fcb18524SNishanth Menon printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n", 656fcb18524SNishanth Menon __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS, 657fcb18524SNishanth Menon OSD_TS_FT_REG_ID, r); 658fcb18524SNishanth Menon goto out; 659fcb18524SNishanth Menon } 660fcb18524SNishanth Menon 661fcb18524SNishanth Menon switch (buf) { 662fcb18524SNishanth Menon case OSD_TS_FT_ID_5606: 663fcb18524SNishanth Menon idk_lcd = "osd101t2045"; 664fcb18524SNishanth Menon break; 665fcb18524SNishanth Menon case OSD_TS_FT_ID_5x46: 666fcb18524SNishanth Menon idk_lcd = "osd101t2587"; 667fcb18524SNishanth Menon break; 668fcb18524SNishanth Menon default: 669fcb18524SNishanth Menon printf("%s: Unidentifed Touch screen ID 0x%02x\n", 670fcb18524SNishanth Menon __func__, buf); 671fcb18524SNishanth Menon /* we will let default be "no lcd" */ 672fcb18524SNishanth Menon } 673fcb18524SNishanth Menon out: 674382bee57SSimon Glass env_set("idk_lcd", idk_lcd); 675fcb18524SNishanth Menon return; 676fcb18524SNishanth Menon } 677fcb18524SNishanth Menon 67874cc8b09SKipisz, Steven int board_late_init(void) 67974cc8b09SKipisz, Steven { 680212f96f6SKipisz, Steven setup_board_eeprom_env(); 681385d3632SKeerthy u8 val; 682212f96f6SKipisz, Steven 68374cc8b09SKipisz, Steven /* 68474cc8b09SKipisz, Steven * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds 68574cc8b09SKipisz, Steven * This is the POWERHOLD-in-Low behavior. 68674cc8b09SKipisz, Steven */ 68774cc8b09SKipisz, Steven palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); 68882cca5a6SLokesh Vutla 68982cca5a6SLokesh Vutla /* 69082cca5a6SLokesh Vutla * Default FIT boot on HS devices. Non FIT images are not allowed 69182cca5a6SLokesh Vutla * on HS devices. 69282cca5a6SLokesh Vutla */ 69382cca5a6SLokesh Vutla if (get_device_type() == HS_DEVICE) 694382bee57SSimon Glass env_set("boot_fit", "1"); 69582cca5a6SLokesh Vutla 696385d3632SKeerthy /* 697385d3632SKeerthy * Set the GPIO7 Pad to POWERHOLD. This has higher priority 698385d3632SKeerthy * over DEV_CTRL.DEV_ON bit. This can be reset in case of 699385d3632SKeerthy * PMIC Power off. So to be on the safer side set it back 700385d3632SKeerthy * to POWERHOLD mode irrespective of the current state. 701385d3632SKeerthy */ 702385d3632SKeerthy palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2, 703385d3632SKeerthy &val); 704385d3632SKeerthy val = val | TPS65903X_PAD2_POWERHOLD_MASK; 705385d3632SKeerthy palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2, 706385d3632SKeerthy val); 707385d3632SKeerthy 7087a2af751SSemen Protsenko omap_die_id_serial(); 7098bd29623SSemen Protsenko omap_set_fastboot_vars(); 7107a2af751SSemen Protsenko 711fcb18524SNishanth Menon am57x_idk_lcd_detect(); 71237611052SRoger Quadros 71337611052SRoger Quadros #if !defined(CONFIG_SPL_BUILD) 71437611052SRoger Quadros board_ti_set_ethaddr(2); 71537611052SRoger Quadros #endif 71637611052SRoger Quadros 71774cc8b09SKipisz, Steven return 0; 71874cc8b09SKipisz, Steven } 71974cc8b09SKipisz, Steven 7203ef56e61SPaul Kocialkowski void set_muxconf_regs(void) 72174cc8b09SKipisz, Steven { 72274cc8b09SKipisz, Steven do_set_mux32((*ctrl)->control_padconf_core_base, 72374cc8b09SKipisz, Steven early_padconf, ARRAY_SIZE(early_padconf)); 72474cc8b09SKipisz, Steven } 72574cc8b09SKipisz, Steven 72674cc8b09SKipisz, Steven #ifdef CONFIG_IODELAY_RECALIBRATION 72774cc8b09SKipisz, Steven void recalibrate_iodelay(void) 72874cc8b09SKipisz, Steven { 729c020d355SSteve Kipisz const struct pad_conf_entry *pconf; 7302d7e9e9dSLokesh Vutla const struct iodelay_cfg_entry *iod, *delta_iod; 7312d7e9e9dSLokesh Vutla int pconf_sz, iod_sz, delta_iod_sz = 0; 73289a38953SNishanth Menon int ret; 733c020d355SSteve Kipisz 734443b0df3SLokesh Vutla if (board_is_am572x_idk()) { 735c020d355SSteve Kipisz pconf = core_padconf_array_essential_am572x_idk; 736c020d355SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); 737c020d355SSteve Kipisz iod = iodelay_cfg_array_am572x_idk; 738c020d355SSteve Kipisz iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk); 739443b0df3SLokesh Vutla } else if (board_is_am574x_idk()) { 740443b0df3SLokesh Vutla pconf = core_padconf_array_essential_am574x_idk; 741443b0df3SLokesh Vutla pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk); 742443b0df3SLokesh Vutla iod = iodelay_cfg_array_am574x_idk; 743443b0df3SLokesh Vutla iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk); 7444d8397c6SSteve Kipisz } else if (board_is_am571x_idk()) { 7454d8397c6SSteve Kipisz pconf = core_padconf_array_essential_am571x_idk; 7464d8397c6SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk); 7474d8397c6SSteve Kipisz iod = iodelay_cfg_array_am571x_idk; 7484d8397c6SSteve Kipisz iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk); 749c020d355SSteve Kipisz } else { 750c020d355SSteve Kipisz /* Common for X15/GPEVM */ 751c020d355SSteve Kipisz pconf = core_padconf_array_essential_x15; 752c020d355SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15); 75389a38953SNishanth Menon /* There never was an SR1.0 X15.. So.. */ 75489a38953SNishanth Menon if (omap_revision() == DRA752_ES1_1) { 75589a38953SNishanth Menon iod = iodelay_cfg_array_x15_sr1_1; 75689a38953SNishanth Menon iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1); 75789a38953SNishanth Menon } else { 75889a38953SNishanth Menon /* Since full production should switch to SR2.0 */ 75989a38953SNishanth Menon iod = iodelay_cfg_array_x15_sr2_0; 76089a38953SNishanth Menon iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0); 76189a38953SNishanth Menon } 762c020d355SSteve Kipisz } 763c020d355SSteve Kipisz 76489a38953SNishanth Menon /* Setup I/O isolation */ 76589a38953SNishanth Menon ret = __recalibrate_iodelay_start(); 76689a38953SNishanth Menon if (ret) 76789a38953SNishanth Menon goto err; 76889a38953SNishanth Menon 76989a38953SNishanth Menon /* Do the muxing here */ 77089a38953SNishanth Menon do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); 77189a38953SNishanth Menon 77289a38953SNishanth Menon /* Now do the weird minor deltas that should be safe */ 77389a38953SNishanth Menon if (board_is_x15() || board_is_am572x_evm()) { 774f70a4272SLokesh Vutla if (board_is_x15_revb1() || board_is_am572x_evm_reva3() || 775f70a4272SLokesh Vutla board_is_x15_revc()) { 77689a38953SNishanth Menon pconf = core_padconf_array_delta_x15_sr2_0; 77789a38953SNishanth Menon pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0); 77889a38953SNishanth Menon } else { 77989a38953SNishanth Menon pconf = core_padconf_array_delta_x15_sr1_1; 78089a38953SNishanth Menon pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1); 78189a38953SNishanth Menon } 78289a38953SNishanth Menon do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); 78389a38953SNishanth Menon } 78489a38953SNishanth Menon 78537611052SRoger Quadros if (board_is_am571x_idk()) { 78637611052SRoger Quadros if (am571x_idk_needs_lcd()) { 78737611052SRoger Quadros pconf = core_padconf_array_vout_am571x_idk; 78837611052SRoger Quadros pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk); 7892d7e9e9dSLokesh Vutla delta_iod = iodelay_cfg_array_am571x_idk_4port; 7902d7e9e9dSLokesh Vutla delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port); 7912d7e9e9dSLokesh Vutla 79237611052SRoger Quadros } else { 79337611052SRoger Quadros pconf = core_padconf_array_icss1eth_am571x_idk; 79437611052SRoger Quadros pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk); 79537611052SRoger Quadros } 79637611052SRoger Quadros do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz); 79737611052SRoger Quadros } 79837611052SRoger Quadros 79989a38953SNishanth Menon /* Setup IOdelay configuration */ 80089a38953SNishanth Menon ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz); 8012d7e9e9dSLokesh Vutla if (delta_iod_sz) 8022d7e9e9dSLokesh Vutla ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod, 8032d7e9e9dSLokesh Vutla delta_iod_sz); 8042d7e9e9dSLokesh Vutla 80589a38953SNishanth Menon err: 80689a38953SNishanth Menon /* Closeup.. remove isolation */ 80789a38953SNishanth Menon __recalibrate_iodelay_end(ret); 80874cc8b09SKipisz, Steven } 80974cc8b09SKipisz, Steven #endif 81074cc8b09SKipisz, Steven 8114aa2ba3aSMasahiro Yamada #if defined(CONFIG_MMC) 81274cc8b09SKipisz, Steven int board_mmc_init(bd_t *bis) 81374cc8b09SKipisz, Steven { 81474cc8b09SKipisz, Steven omap_mmc_init(0, 0, 0, -1, -1); 81574cc8b09SKipisz, Steven omap_mmc_init(1, 0, 0, -1, -1); 81674cc8b09SKipisz, Steven return 0; 81774cc8b09SKipisz, Steven } 81874cc8b09SKipisz, Steven #endif 81974cc8b09SKipisz, Steven 82074cc8b09SKipisz, Steven #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 82174cc8b09SKipisz, Steven int spl_start_uboot(void) 82274cc8b09SKipisz, Steven { 82374cc8b09SKipisz, Steven /* break into full u-boot on 'c' */ 82474cc8b09SKipisz, Steven if (serial_tstc() && serial_getc() == 'c') 82574cc8b09SKipisz, Steven return 1; 82674cc8b09SKipisz, Steven 82774cc8b09SKipisz, Steven #ifdef CONFIG_SPL_ENV_SUPPORT 82874cc8b09SKipisz, Steven env_init(); 829310fb14bSSimon Glass env_load(); 830bfebc8c9SSimon Glass if (env_get_yesno("boot_os") != 1) 83174cc8b09SKipisz, Steven return 1; 83274cc8b09SKipisz, Steven #endif 83374cc8b09SKipisz, Steven 83474cc8b09SKipisz, Steven return 0; 83574cc8b09SKipisz, Steven } 83674cc8b09SKipisz, Steven #endif 83774cc8b09SKipisz, Steven 83874cc8b09SKipisz, Steven #ifdef CONFIG_USB_DWC3 83974cc8b09SKipisz, Steven static struct dwc3_device usb_otg_ss2 = { 84074cc8b09SKipisz, Steven .maximum_speed = USB_SPEED_HIGH, 84174cc8b09SKipisz, Steven .base = DRA7_USB_OTG_SS2_BASE, 84274cc8b09SKipisz, Steven .tx_fifo_resize = false, 84374cc8b09SKipisz, Steven .index = 1, 84474cc8b09SKipisz, Steven }; 84574cc8b09SKipisz, Steven 84674cc8b09SKipisz, Steven static struct dwc3_omap_device usb_otg_ss2_glue = { 84774cc8b09SKipisz, Steven .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 84874cc8b09SKipisz, Steven .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 84974cc8b09SKipisz, Steven .index = 1, 85074cc8b09SKipisz, Steven }; 85174cc8b09SKipisz, Steven 85274cc8b09SKipisz, Steven static struct ti_usb_phy_device usb_phy2_device = { 85374cc8b09SKipisz, Steven .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 85474cc8b09SKipisz, Steven .index = 1, 85574cc8b09SKipisz, Steven }; 85674cc8b09SKipisz, Steven 85774cc8b09SKipisz, Steven int usb_gadget_handle_interrupts(int index) 85874cc8b09SKipisz, Steven { 85974cc8b09SKipisz, Steven u32 status; 86074cc8b09SKipisz, Steven 86174cc8b09SKipisz, Steven status = dwc3_omap_uboot_interrupt_status(index); 86274cc8b09SKipisz, Steven if (status) 86374cc8b09SKipisz, Steven dwc3_uboot_handle_interrupt(index); 86474cc8b09SKipisz, Steven 86574cc8b09SKipisz, Steven return 0; 86674cc8b09SKipisz, Steven } 86755efaddeSRoger Quadros #endif /* CONFIG_USB_DWC3 */ 86855efaddeSRoger Quadros 86955efaddeSRoger Quadros #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 8701a9a5f7aSUri Mashiach int omap_xhci_board_usb_init(int index, enum usb_init_type init) 87155efaddeSRoger Quadros { 87255efaddeSRoger Quadros enable_usb_clocks(index); 87355efaddeSRoger Quadros switch (index) { 87455efaddeSRoger Quadros case 0: 87555efaddeSRoger Quadros if (init == USB_INIT_DEVICE) { 87655efaddeSRoger Quadros printf("port %d can't be used as device\n", index); 87755efaddeSRoger Quadros disable_usb_clocks(index); 87855efaddeSRoger Quadros return -EINVAL; 87955efaddeSRoger Quadros } 88055efaddeSRoger Quadros break; 88155efaddeSRoger Quadros case 1: 88255efaddeSRoger Quadros if (init == USB_INIT_DEVICE) { 88355efaddeSRoger Quadros #ifdef CONFIG_USB_DWC3 88455efaddeSRoger Quadros usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 88555efaddeSRoger Quadros usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 88655efaddeSRoger Quadros ti_usb_phy_uboot_init(&usb_phy2_device); 88755efaddeSRoger Quadros dwc3_omap_uboot_init(&usb_otg_ss2_glue); 88855efaddeSRoger Quadros dwc3_uboot_init(&usb_otg_ss2); 88974cc8b09SKipisz, Steven #endif 89055efaddeSRoger Quadros } else { 89155efaddeSRoger Quadros printf("port %d can't be used as host\n", index); 89255efaddeSRoger Quadros disable_usb_clocks(index); 89355efaddeSRoger Quadros return -EINVAL; 89455efaddeSRoger Quadros } 89555efaddeSRoger Quadros 89655efaddeSRoger Quadros break; 89755efaddeSRoger Quadros default: 89855efaddeSRoger Quadros printf("Invalid Controller Index\n"); 89955efaddeSRoger Quadros } 90055efaddeSRoger Quadros 90155efaddeSRoger Quadros return 0; 90255efaddeSRoger Quadros } 90355efaddeSRoger Quadros 9041a9a5f7aSUri Mashiach int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init) 90555efaddeSRoger Quadros { 90655efaddeSRoger Quadros #ifdef CONFIG_USB_DWC3 90755efaddeSRoger Quadros switch (index) { 90855efaddeSRoger Quadros case 0: 90955efaddeSRoger Quadros case 1: 91055efaddeSRoger Quadros if (init == USB_INIT_DEVICE) { 91155efaddeSRoger Quadros ti_usb_phy_uboot_exit(index); 91255efaddeSRoger Quadros dwc3_uboot_exit(index); 91355efaddeSRoger Quadros dwc3_omap_uboot_exit(index); 91455efaddeSRoger Quadros } 91555efaddeSRoger Quadros break; 91655efaddeSRoger Quadros default: 91755efaddeSRoger Quadros printf("Invalid Controller Index\n"); 91855efaddeSRoger Quadros } 91955efaddeSRoger Quadros #endif 92055efaddeSRoger Quadros disable_usb_clocks(index); 92155efaddeSRoger Quadros return 0; 92255efaddeSRoger Quadros } 92355efaddeSRoger Quadros #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 92474cc8b09SKipisz, Steven 92574cc8b09SKipisz, Steven #ifdef CONFIG_DRIVER_TI_CPSW 92674cc8b09SKipisz, Steven 92774cc8b09SKipisz, Steven /* Delay value to add to calibrated value */ 92874cc8b09SKipisz, Steven #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 92974cc8b09SKipisz, Steven #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 93074cc8b09SKipisz, Steven #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 93174cc8b09SKipisz, Steven #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 93274cc8b09SKipisz, Steven #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 93374cc8b09SKipisz, Steven #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 93474cc8b09SKipisz, Steven #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 93574cc8b09SKipisz, Steven #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 93674cc8b09SKipisz, Steven #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 93774cc8b09SKipisz, Steven #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 93874cc8b09SKipisz, Steven 93974cc8b09SKipisz, Steven static void cpsw_control(int enabled) 94074cc8b09SKipisz, Steven { 94174cc8b09SKipisz, Steven /* VTP can be added here */ 94274cc8b09SKipisz, Steven } 94374cc8b09SKipisz, Steven 94474cc8b09SKipisz, Steven static struct cpsw_slave_data cpsw_slaves[] = { 94574cc8b09SKipisz, Steven { 94674cc8b09SKipisz, Steven .slave_reg_ofs = 0x208, 94774cc8b09SKipisz, Steven .sliver_reg_ofs = 0xd80, 94874cc8b09SKipisz, Steven .phy_addr = 1, 94974cc8b09SKipisz, Steven }, 95074cc8b09SKipisz, Steven { 95174cc8b09SKipisz, Steven .slave_reg_ofs = 0x308, 95274cc8b09SKipisz, Steven .sliver_reg_ofs = 0xdc0, 95374cc8b09SKipisz, Steven .phy_addr = 2, 95474cc8b09SKipisz, Steven }, 95574cc8b09SKipisz, Steven }; 95674cc8b09SKipisz, Steven 95774cc8b09SKipisz, Steven static struct cpsw_platform_data cpsw_data = { 95874cc8b09SKipisz, Steven .mdio_base = CPSW_MDIO_BASE, 95974cc8b09SKipisz, Steven .cpsw_base = CPSW_BASE, 96074cc8b09SKipisz, Steven .mdio_div = 0xff, 96174cc8b09SKipisz, Steven .channels = 8, 96274cc8b09SKipisz, Steven .cpdma_reg_ofs = 0x800, 96374cc8b09SKipisz, Steven .slaves = 1, 96474cc8b09SKipisz, Steven .slave_data = cpsw_slaves, 96574cc8b09SKipisz, Steven .ale_reg_ofs = 0xd00, 96674cc8b09SKipisz, Steven .ale_entries = 1024, 96774cc8b09SKipisz, Steven .host_port_reg_ofs = 0x108, 96874cc8b09SKipisz, Steven .hw_stats_reg_ofs = 0x900, 96974cc8b09SKipisz, Steven .bd_ram_ofs = 0x2000, 97074cc8b09SKipisz, Steven .mac_control = (1 << 5), 97174cc8b09SKipisz, Steven .control = cpsw_control, 97274cc8b09SKipisz, Steven .host_port_num = 0, 97374cc8b09SKipisz, Steven .version = CPSW_CTRL_VERSION_2, 97474cc8b09SKipisz, Steven }; 97574cc8b09SKipisz, Steven 97692667e89SRoger Quadros static u64 mac_to_u64(u8 mac[6]) 97792667e89SRoger Quadros { 97892667e89SRoger Quadros int i; 97992667e89SRoger Quadros u64 addr = 0; 98092667e89SRoger Quadros 98192667e89SRoger Quadros for (i = 0; i < 6; i++) { 98292667e89SRoger Quadros addr <<= 8; 98392667e89SRoger Quadros addr |= mac[i]; 98492667e89SRoger Quadros } 98592667e89SRoger Quadros 98692667e89SRoger Quadros return addr; 98792667e89SRoger Quadros } 98892667e89SRoger Quadros 98992667e89SRoger Quadros static void u64_to_mac(u64 addr, u8 mac[6]) 99092667e89SRoger Quadros { 99192667e89SRoger Quadros mac[5] = addr; 99292667e89SRoger Quadros mac[4] = addr >> 8; 99392667e89SRoger Quadros mac[3] = addr >> 16; 99492667e89SRoger Quadros mac[2] = addr >> 24; 99592667e89SRoger Quadros mac[1] = addr >> 32; 99692667e89SRoger Quadros mac[0] = addr >> 40; 99792667e89SRoger Quadros } 99892667e89SRoger Quadros 99974cc8b09SKipisz, Steven int board_eth_init(bd_t *bis) 100074cc8b09SKipisz, Steven { 100174cc8b09SKipisz, Steven int ret; 100274cc8b09SKipisz, Steven uint8_t mac_addr[6]; 100374cc8b09SKipisz, Steven uint32_t mac_hi, mac_lo; 100474cc8b09SKipisz, Steven uint32_t ctrl_val; 100592667e89SRoger Quadros int i; 100692667e89SRoger Quadros u64 mac1, mac2; 100792667e89SRoger Quadros u8 mac_addr1[6], mac_addr2[6]; 100892667e89SRoger Quadros int num_macs; 100974cc8b09SKipisz, Steven 101074cc8b09SKipisz, Steven /* try reading mac address from efuse */ 101174cc8b09SKipisz, Steven mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 101274cc8b09SKipisz, Steven mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 101374cc8b09SKipisz, Steven mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 101474cc8b09SKipisz, Steven mac_addr[1] = (mac_hi & 0xFF00) >> 8; 101574cc8b09SKipisz, Steven mac_addr[2] = mac_hi & 0xFF; 101674cc8b09SKipisz, Steven mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 101774cc8b09SKipisz, Steven mac_addr[4] = (mac_lo & 0xFF00) >> 8; 101874cc8b09SKipisz, Steven mac_addr[5] = mac_lo & 0xFF; 101974cc8b09SKipisz, Steven 102000caae6dSSimon Glass if (!env_get("ethaddr")) { 102174cc8b09SKipisz, Steven printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 102274cc8b09SKipisz, Steven 102374cc8b09SKipisz, Steven if (is_valid_ethaddr(mac_addr)) 1024fd1e959eSSimon Glass eth_env_set_enetaddr("ethaddr", mac_addr); 102574cc8b09SKipisz, Steven } 102674cc8b09SKipisz, Steven 102774cc8b09SKipisz, Steven mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 102874cc8b09SKipisz, Steven mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 102974cc8b09SKipisz, Steven mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 103074cc8b09SKipisz, Steven mac_addr[1] = (mac_hi & 0xFF00) >> 8; 103174cc8b09SKipisz, Steven mac_addr[2] = mac_hi & 0xFF; 103274cc8b09SKipisz, Steven mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 103374cc8b09SKipisz, Steven mac_addr[4] = (mac_lo & 0xFF00) >> 8; 103474cc8b09SKipisz, Steven mac_addr[5] = mac_lo & 0xFF; 103574cc8b09SKipisz, Steven 103600caae6dSSimon Glass if (!env_get("eth1addr")) { 103774cc8b09SKipisz, Steven if (is_valid_ethaddr(mac_addr)) 1038fd1e959eSSimon Glass eth_env_set_enetaddr("eth1addr", mac_addr); 103974cc8b09SKipisz, Steven } 104074cc8b09SKipisz, Steven 104174cc8b09SKipisz, Steven ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 104274cc8b09SKipisz, Steven ctrl_val |= 0x22; 104374cc8b09SKipisz, Steven writel(ctrl_val, (*ctrl)->control_core_control_io1); 104474cc8b09SKipisz, Steven 10454d8397c6SSteve Kipisz /* The phy address for the AM57xx IDK are different than x15 */ 104610f430f3SLokesh Vutla if (board_is_am572x_idk() || board_is_am571x_idk() || 104710f430f3SLokesh Vutla board_is_am574x_idk()) { 1048c020d355SSteve Kipisz cpsw_data.slave_data[0].phy_addr = 0; 1049c020d355SSteve Kipisz cpsw_data.slave_data[1].phy_addr = 1; 1050c020d355SSteve Kipisz } 1051c020d355SSteve Kipisz 105274cc8b09SKipisz, Steven ret = cpsw_register(&cpsw_data); 105374cc8b09SKipisz, Steven if (ret < 0) 105474cc8b09SKipisz, Steven printf("Error %d registering CPSW switch\n", ret); 105574cc8b09SKipisz, Steven 105692667e89SRoger Quadros /* 105792667e89SRoger Quadros * Export any Ethernet MAC addresses from EEPROM. 105892667e89SRoger Quadros * On AM57xx the 2 MAC addresses define the address range 105992667e89SRoger Quadros */ 106092667e89SRoger Quadros board_ti_get_eth_mac_addr(0, mac_addr1); 106192667e89SRoger Quadros board_ti_get_eth_mac_addr(1, mac_addr2); 106292667e89SRoger Quadros 106392667e89SRoger Quadros if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { 106492667e89SRoger Quadros mac1 = mac_to_u64(mac_addr1); 106592667e89SRoger Quadros mac2 = mac_to_u64(mac_addr2); 106692667e89SRoger Quadros 106792667e89SRoger Quadros /* must contain an address range */ 106892667e89SRoger Quadros num_macs = mac2 - mac1 + 1; 106992667e89SRoger Quadros /* <= 50 to protect against user programming error */ 107092667e89SRoger Quadros if (num_macs > 0 && num_macs <= 50) { 107192667e89SRoger Quadros for (i = 0; i < num_macs; i++) { 107292667e89SRoger Quadros u64_to_mac(mac1 + i, mac_addr); 107392667e89SRoger Quadros if (is_valid_ethaddr(mac_addr)) { 1074fd1e959eSSimon Glass eth_env_set_enetaddr_by_index("eth", 107592667e89SRoger Quadros i + 2, 107692667e89SRoger Quadros mac_addr); 107792667e89SRoger Quadros } 107892667e89SRoger Quadros } 107992667e89SRoger Quadros } 108092667e89SRoger Quadros } 108192667e89SRoger Quadros 108274cc8b09SKipisz, Steven return ret; 108374cc8b09SKipisz, Steven } 108474cc8b09SKipisz, Steven #endif 108574cc8b09SKipisz, Steven 108674cc8b09SKipisz, Steven #ifdef CONFIG_BOARD_EARLY_INIT_F 108774cc8b09SKipisz, Steven /* VTT regulator enable */ 108874cc8b09SKipisz, Steven static inline void vtt_regulator_enable(void) 108974cc8b09SKipisz, Steven { 109074cc8b09SKipisz, Steven if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 109174cc8b09SKipisz, Steven return; 109274cc8b09SKipisz, Steven 109374cc8b09SKipisz, Steven gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 109474cc8b09SKipisz, Steven gpio_direction_output(GPIO_DDR_VTT_EN, 1); 109574cc8b09SKipisz, Steven } 109674cc8b09SKipisz, Steven 109774cc8b09SKipisz, Steven int board_early_init_f(void) 109874cc8b09SKipisz, Steven { 109974cc8b09SKipisz, Steven vtt_regulator_enable(); 110074cc8b09SKipisz, Steven return 0; 110174cc8b09SKipisz, Steven } 110274cc8b09SKipisz, Steven #endif 110362a09f05SDaniel Allred 110462a09f05SDaniel Allred #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 110562a09f05SDaniel Allred int ft_board_setup(void *blob, bd_t *bd) 110662a09f05SDaniel Allred { 110762a09f05SDaniel Allred ft_cpu_setup(blob, bd); 110862a09f05SDaniel Allred 110962a09f05SDaniel Allred return 0; 111062a09f05SDaniel Allred } 111162a09f05SDaniel Allred #endif 11127a0ea589SLokesh Vutla 11137a0ea589SLokesh Vutla #ifdef CONFIG_SPL_LOAD_FIT 11147a0ea589SLokesh Vutla int board_fit_config_name_match(const char *name) 11157a0ea589SLokesh Vutla { 1116f7f9f6beSLokesh Vutla if (board_is_x15()) { 1117f7f9f6beSLokesh Vutla if (board_is_x15_revb1()) { 1118f7f9f6beSLokesh Vutla if (!strcmp(name, "am57xx-beagle-x15-revb1")) 11197a0ea589SLokesh Vutla return 0; 11208b2551a4SLokesh Vutla } else if (board_is_x15_revc()) { 11218b2551a4SLokesh Vutla if (!strcmp(name, "am57xx-beagle-x15-revc")) 11228b2551a4SLokesh Vutla return 0; 1123f7f9f6beSLokesh Vutla } else if (!strcmp(name, "am57xx-beagle-x15")) { 11247a0ea589SLokesh Vutla return 0; 1125f7f9f6beSLokesh Vutla } 1126f7f9f6beSLokesh Vutla } else if (board_is_am572x_evm() && 1127f7f9f6beSLokesh Vutla !strcmp(name, "am57xx-beagle-x15")) { 1128332dddc6SSchuyler Patton return 0; 1129f7f9f6beSLokesh Vutla } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) { 1130f7f9f6beSLokesh Vutla return 0; 1131*b4185e4fSLokesh Vutla } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) { 1132*b4185e4fSLokesh Vutla return 0; 113345e7f7e7SSchuyler Patton } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) { 113445e7f7e7SSchuyler Patton return 0; 1135f7f9f6beSLokesh Vutla } 1136f7f9f6beSLokesh Vutla 11377a0ea589SLokesh Vutla return -1; 11387a0ea589SLokesh Vutla } 11397a0ea589SLokesh Vutla #endif 114017c29873SAndreas Dannenberg 114117c29873SAndreas Dannenberg #ifdef CONFIG_TI_SECURE_DEVICE 114217c29873SAndreas Dannenberg void board_fit_image_post_process(void **p_image, size_t *p_size) 114317c29873SAndreas Dannenberg { 114417c29873SAndreas Dannenberg secure_boot_verify_image(p_image, p_size); 114517c29873SAndreas Dannenberg } 11461b597adaSAndrew F. Davis 11471b597adaSAndrew F. Davis void board_tee_image_process(ulong tee_image, size_t tee_size) 11481b597adaSAndrew F. Davis { 11491b597adaSAndrew F. Davis secure_tee_install((u32)tee_image); 11501b597adaSAndrew F. Davis } 11511b597adaSAndrew F. Davis 11521b597adaSAndrew F. Davis U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 115317c29873SAndreas Dannenberg #endif 1154