1 /* 2 * mux.c 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/mux.h> 12 #include "board.h" 13 14 static struct module_pin_mux rmii1_pin_mux[] = { 15 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ 16 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */ 17 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */ 18 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */ 19 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */ 20 {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */ 21 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */ 22 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ 23 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */ 24 {-1}, 25 }; 26 27 static struct module_pin_mux rgmii1_pin_mux[] = { 28 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ 29 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 30 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ 31 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ 32 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ 33 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ 34 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ 35 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 36 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 37 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 38 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 39 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 40 {-1}, 41 }; 42 43 static struct module_pin_mux mdio_pin_mux[] = { 44 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 45 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 46 {-1}, 47 }; 48 49 static struct module_pin_mux uart0_pin_mux[] = { 50 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, 51 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)}, 52 {-1}, 53 }; 54 55 static struct module_pin_mux mmc0_pin_mux[] = { 56 {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */ 57 {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */ 58 {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */ 59 {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */ 60 {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */ 61 {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */ 62 {-1}, 63 }; 64 65 static struct module_pin_mux i2c0_pin_mux[] = { 66 {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, 67 {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)}, 68 {-1}, 69 }; 70 71 static struct module_pin_mux gpio5_7_pin_mux[] = { 72 {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */ 73 {-1}, 74 }; 75 76 #ifdef CONFIG_NAND 77 static struct module_pin_mux nand_pin_mux[] = { 78 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ 79 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ 80 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ 81 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ 82 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ 83 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ 84 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ 85 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ 86 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT 87 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ 88 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ 89 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ 90 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ 91 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ 92 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ 93 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ 94 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ 95 #endif 96 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */ 97 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */ 98 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */ 99 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */ 100 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */ 101 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/ 102 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */ 103 {-1}, 104 }; 105 #endif 106 107 static __maybe_unused struct module_pin_mux qspi_pin_mux[] = { 108 {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ 109 {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ 110 {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ 111 {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */ 112 {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */ 113 {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */ 114 {-1}, 115 }; 116 117 void enable_uart0_pin_mux(void) 118 { 119 configure_module_pin_mux(uart0_pin_mux); 120 } 121 122 void enable_board_pin_mux(void) 123 { 124 configure_module_pin_mux(mmc0_pin_mux); 125 configure_module_pin_mux(i2c0_pin_mux); 126 configure_module_pin_mux(mdio_pin_mux); 127 128 if (board_is_gpevm()) { 129 configure_module_pin_mux(gpio5_7_pin_mux); 130 configure_module_pin_mux(rgmii1_pin_mux); 131 #if defined(CONFIG_NAND) 132 configure_module_pin_mux(nand_pin_mux); 133 #endif 134 } else if (board_is_sk() || board_is_idk()) { 135 configure_module_pin_mux(rgmii1_pin_mux); 136 #if defined(CONFIG_NAND) 137 printf("Error: NAND flash not present on this board\n"); 138 #endif 139 configure_module_pin_mux(qspi_pin_mux); 140 } else if (board_is_eposevm()) { 141 configure_module_pin_mux(rmii1_pin_mux); 142 #if defined(CONFIG_NAND) 143 configure_module_pin_mux(nand_pin_mux); 144 #else 145 configure_module_pin_mux(qspi_pin_mux); 146 #endif 147 } 148 } 149 150 void enable_i2c0_pin_mux(void) 151 { 152 configure_module_pin_mux(i2c0_pin_mux); 153 } 154