1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <linux/errno.h> 14 #include <spl.h> 15 #include <usb.h> 16 #include <asm/omap_sec_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/mux.h> 20 #include <asm/arch/ddr_defs.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/emif.h> 23 #include "../common/board_detect.h" 24 #include "board.h" 25 #include <power/pmic.h> 26 #include <power/tps65218.h> 27 #include <power/tps62362.h> 28 #include <miiphy.h> 29 #include <cpsw.h> 30 #include <linux/usb/gadget.h> 31 #include <dwc3-uboot.h> 32 #include <dwc3-omap-uboot.h> 33 #include <ti-usb-phy-uboot.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 38 39 /* 40 * Read header information from EEPROM into global structure. 41 */ 42 #ifdef CONFIG_TI_I2C_BOARD_DETECT 43 void do_board_detect(void) 44 { 45 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 46 CONFIG_EEPROM_CHIP_ADDRESS)) 47 printf("ti_i2c_eeprom_init failed\n"); 48 } 49 #endif 50 51 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 52 53 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 54 { /* 19.2 MHz */ 55 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ 56 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 57 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ 58 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ 59 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ 60 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ 61 }, 62 { /* 24 MHz */ 63 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 64 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 65 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 66 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 67 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 68 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 69 }, 70 { /* 25 MHz */ 71 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 72 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 73 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 74 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 75 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 76 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 77 }, 78 { /* 26 MHz */ 79 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 80 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 81 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 82 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 83 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 84 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 85 }, 86 }; 87 88 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 89 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ 90 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 91 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 92 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 93 }; 94 95 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 96 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 97 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ 98 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ 99 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ 100 }; 101 102 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { 103 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ 104 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ 105 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ 106 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ 107 }; 108 109 const struct dpll_params gp_evm_dpll_ddr = { 110 50, 2, 1, -1, 2, -1, -1}; 111 112 static const struct dpll_params idk_dpll_ddr = { 113 400, 23, 1, -1, 2, -1, -1 114 }; 115 116 static const u32 ext_phy_ctrl_const_base_lpddr2[] = { 117 0x00500050, 118 0x00350035, 119 0x00350035, 120 0x00350035, 121 0x00350035, 122 0x00350035, 123 0x00000000, 124 0x00000000, 125 0x00000000, 126 0x00000000, 127 0x00000000, 128 0x00000000, 129 0x00000000, 130 0x00000000, 131 0x00000000, 132 0x00000000, 133 0x00000000, 134 0x00000000, 135 0x40001000, 136 0x08102040 137 }; 138 139 const struct ctrl_ioregs ioregs_lpddr2 = { 140 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 141 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 142 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 143 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 144 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 145 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 146 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 147 .emif_sdram_config_ext = 0x1, 148 }; 149 150 const struct emif_regs emif_regs_lpddr2 = { 151 .sdram_config = 0x808012BA, 152 .ref_ctrl = 0x0000040D, 153 .sdram_tim1 = 0xEA86B411, 154 .sdram_tim2 = 0x103A094A, 155 .sdram_tim3 = 0x0F6BA37F, 156 .read_idle_ctrl = 0x00050000, 157 .zq_config = 0x50074BE4, 158 .temp_alert_config = 0x0, 159 .emif_rd_wr_lvl_rmp_win = 0x0, 160 .emif_rd_wr_lvl_rmp_ctl = 0x0, 161 .emif_rd_wr_lvl_ctl = 0x0, 162 .emif_ddr_phy_ctlr_1 = 0x0E284006, 163 .emif_rd_wr_exec_thresh = 0x80000405, 164 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 165 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 166 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 167 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 168 .emif_ddr_ext_phy_ctrl_5 = 0x00500050, 169 .emif_prio_class_serv_map = 0x80000001, 170 .emif_connect_id_serv_1_map = 0x80000094, 171 .emif_connect_id_serv_2_map = 0x00000000, 172 .emif_cos_config = 0x000FFFFF 173 }; 174 175 const struct ctrl_ioregs ioregs_ddr3 = { 176 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 177 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 178 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 179 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 180 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 181 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 182 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 183 .emif_sdram_config_ext = 0xc163, 184 }; 185 186 const struct emif_regs ddr3_emif_regs_400Mhz = { 187 .sdram_config = 0x638413B2, 188 .ref_ctrl = 0x00000C30, 189 .sdram_tim1 = 0xEAAAD4DB, 190 .sdram_tim2 = 0x266B7FDA, 191 .sdram_tim3 = 0x107F8678, 192 .read_idle_ctrl = 0x00050000, 193 .zq_config = 0x50074BE4, 194 .temp_alert_config = 0x0, 195 .emif_ddr_phy_ctlr_1 = 0x0E004008, 196 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 197 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 198 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 199 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 200 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 201 .emif_rd_wr_lvl_rmp_win = 0x0, 202 .emif_rd_wr_lvl_rmp_ctl = 0x0, 203 .emif_rd_wr_lvl_ctl = 0x0, 204 .emif_rd_wr_exec_thresh = 0x80000405, 205 .emif_prio_class_serv_map = 0x80000001, 206 .emif_connect_id_serv_1_map = 0x80000094, 207 .emif_connect_id_serv_2_map = 0x00000000, 208 .emif_cos_config = 0x000FFFFF 209 }; 210 211 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ 212 const struct emif_regs ddr3_emif_regs_400Mhz_beta = { 213 .sdram_config = 0x638413B2, 214 .ref_ctrl = 0x00000C30, 215 .sdram_tim1 = 0xEAAAD4DB, 216 .sdram_tim2 = 0x266B7FDA, 217 .sdram_tim3 = 0x107F8678, 218 .read_idle_ctrl = 0x00050000, 219 .zq_config = 0x50074BE4, 220 .temp_alert_config = 0x0, 221 .emif_ddr_phy_ctlr_1 = 0x0E004008, 222 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 223 .emif_ddr_ext_phy_ctrl_2 = 0x00000065, 224 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 225 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, 226 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, 227 .emif_rd_wr_exec_thresh = 0x80000405, 228 .emif_prio_class_serv_map = 0x80000001, 229 .emif_connect_id_serv_1_map = 0x80000094, 230 .emif_connect_id_serv_2_map = 0x00000000, 231 .emif_cos_config = 0x000FFFFF 232 }; 233 234 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 235 const struct emif_regs ddr3_emif_regs_400Mhz_production = { 236 .sdram_config = 0x638413B2, 237 .ref_ctrl = 0x00000C30, 238 .sdram_tim1 = 0xEAAAD4DB, 239 .sdram_tim2 = 0x266B7FDA, 240 .sdram_tim3 = 0x107F8678, 241 .read_idle_ctrl = 0x00050000, 242 .zq_config = 0x50074BE4, 243 .temp_alert_config = 0x0, 244 .emif_ddr_phy_ctlr_1 = 0x0E004008, 245 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 246 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 247 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 248 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 249 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 250 .emif_rd_wr_exec_thresh = 0x80000405, 251 .emif_prio_class_serv_map = 0x80000001, 252 .emif_connect_id_serv_1_map = 0x80000094, 253 .emif_connect_id_serv_2_map = 0x00000000, 254 .emif_cos_config = 0x000FFFFF 255 }; 256 257 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { 258 .sdram_config = 0x638413b2, 259 .sdram_config2 = 0x00000000, 260 .ref_ctrl = 0x00000c30, 261 .sdram_tim1 = 0xeaaad4db, 262 .sdram_tim2 = 0x266b7fda, 263 .sdram_tim3 = 0x107f8678, 264 .read_idle_ctrl = 0x00050000, 265 .zq_config = 0x50074be4, 266 .temp_alert_config = 0x0, 267 .emif_ddr_phy_ctlr_1 = 0x0e084008, 268 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 269 .emif_ddr_ext_phy_ctrl_2 = 0x89, 270 .emif_ddr_ext_phy_ctrl_3 = 0x90, 271 .emif_ddr_ext_phy_ctrl_4 = 0x8e, 272 .emif_ddr_ext_phy_ctrl_5 = 0x8d, 273 .emif_rd_wr_lvl_rmp_win = 0x0, 274 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 275 .emif_rd_wr_lvl_ctl = 0x00000000, 276 .emif_rd_wr_exec_thresh = 0x80000000, 277 .emif_prio_class_serv_map = 0x80000001, 278 .emif_connect_id_serv_1_map = 0x80000094, 279 .emif_connect_id_serv_2_map = 0x00000000, 280 .emif_cos_config = 0x000FFFFF 281 }; 282 283 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { 284 .sdram_config = 0x61a11b32, 285 .sdram_config2 = 0x00000000, 286 .ref_ctrl = 0x00000c30, 287 .sdram_tim1 = 0xeaaad4db, 288 .sdram_tim2 = 0x266b7fda, 289 .sdram_tim3 = 0x107f8678, 290 .read_idle_ctrl = 0x00050000, 291 .zq_config = 0x50074be4, 292 .temp_alert_config = 0x00000000, 293 .emif_ddr_phy_ctlr_1 = 0x00008009, 294 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 295 .emif_ddr_ext_phy_ctrl_2 = 0x00000040, 296 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, 297 .emif_ddr_ext_phy_ctrl_4 = 0x00000051, 298 .emif_ddr_ext_phy_ctrl_5 = 0x00000051, 299 .emif_rd_wr_lvl_rmp_win = 0x00000000, 300 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 301 .emif_rd_wr_lvl_ctl = 0x00000000, 302 .emif_rd_wr_exec_thresh = 0x00000405, 303 .emif_prio_class_serv_map = 0x00000000, 304 .emif_connect_id_serv_1_map = 0x00000000, 305 .emif_connect_id_serv_2_map = 0x00000000, 306 .emif_cos_config = 0x00ffffff 307 }; 308 309 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 310 { 311 if (board_is_eposevm()) { 312 *regs = ext_phy_ctrl_const_base_lpddr2; 313 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 314 } 315 316 return; 317 } 318 319 const struct dpll_params *get_dpll_ddr_params(void) 320 { 321 int ind = get_sys_clk_index(); 322 323 if (board_is_eposevm()) 324 return &epos_evm_dpll_ddr[ind]; 325 else if (board_is_evm() || board_is_sk()) 326 return &gp_evm_dpll_ddr; 327 else if (board_is_idk()) 328 return &idk_dpll_ddr; 329 330 printf(" Board '%s' not supported\n", board_ti_get_name()); 331 return NULL; 332 } 333 334 335 /* 336 * get_opp_offset: 337 * Returns the index for safest OPP of the device to boot. 338 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 339 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 340 * This data is read from dev_attribute register which is e-fused. 341 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 342 * OPP available. Lowest OPP starts with min_off. So returning the 343 * bit with rightmost '0'. 344 */ 345 static int get_opp_offset(int max_off, int min_off) 346 { 347 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 348 int opp, offset, i; 349 350 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 351 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 352 353 for (i = max_off; i >= min_off; i--) { 354 offset = opp & (1 << i); 355 if (!offset) 356 return i; 357 } 358 359 return min_off; 360 } 361 362 const struct dpll_params *get_dpll_mpu_params(void) 363 { 364 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 365 u32 ind = get_sys_clk_index(); 366 367 return &dpll_mpu[ind][opp]; 368 } 369 370 const struct dpll_params *get_dpll_core_params(void) 371 { 372 int ind = get_sys_clk_index(); 373 374 return &dpll_core[ind]; 375 } 376 377 const struct dpll_params *get_dpll_per_params(void) 378 { 379 int ind = get_sys_clk_index(); 380 381 return &dpll_per[ind]; 382 } 383 384 void scale_vcores_generic(u32 m) 385 { 386 int mpu_vdd; 387 388 if (i2c_probe(TPS65218_CHIP_PM)) 389 return; 390 391 switch (m) { 392 case 1000: 393 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 394 break; 395 case 800: 396 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; 397 break; 398 case 720: 399 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; 400 break; 401 case 600: 402 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 403 break; 404 case 300: 405 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; 406 break; 407 default: 408 puts("Unknown MPU clock, not scaling\n"); 409 return; 410 } 411 412 /* Set DCDC1 (CORE) voltage to 1.1V */ 413 if (tps65218_voltage_update(TPS65218_DCDC1, 414 TPS65218_DCDC_VOLT_SEL_1100MV)) { 415 printf("%s failure\n", __func__); 416 return; 417 } 418 419 /* Set DCDC2 (MPU) voltage */ 420 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 421 printf("%s failure\n", __func__); 422 return; 423 } 424 425 /* Set DCDC3 (DDR) voltage */ 426 if (tps65218_voltage_update(TPS65218_DCDC3, 427 TPS65218_DCDC3_VOLT_SEL_1350MV)) { 428 printf("%s failure\n", __func__); 429 return; 430 } 431 } 432 433 void scale_vcores_idk(u32 m) 434 { 435 int mpu_vdd; 436 437 if (i2c_probe(TPS62362_I2C_ADDR)) 438 return; 439 440 switch (m) { 441 case 1000: 442 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 443 break; 444 case 800: 445 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; 446 break; 447 case 720: 448 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; 449 break; 450 case 600: 451 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; 452 break; 453 case 300: 454 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 455 break; 456 default: 457 puts("Unknown MPU clock, not scaling\n"); 458 return; 459 } 460 461 /* Set VDD_MPU voltage */ 462 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { 463 printf("%s failure\n", __func__); 464 return; 465 } 466 } 467 468 void gpi2c_init(void) 469 { 470 /* When needed to be invoked prior to BSS initialization */ 471 static bool first_time = true; 472 473 if (first_time) { 474 enable_i2c0_pin_mux(); 475 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 476 CONFIG_SYS_OMAP24_I2C_SLAVE); 477 first_time = false; 478 } 479 } 480 481 void scale_vcores(void) 482 { 483 const struct dpll_params *mpu_params; 484 485 /* Ensure I2C is initialized for PMIC configuration */ 486 gpi2c_init(); 487 488 /* Get the frequency */ 489 mpu_params = get_dpll_mpu_params(); 490 491 if (board_is_idk()) 492 scale_vcores_idk(mpu_params->m); 493 else 494 scale_vcores_generic(mpu_params->m); 495 } 496 497 void set_uart_mux_conf(void) 498 { 499 enable_uart0_pin_mux(); 500 } 501 502 void set_mux_conf_regs(void) 503 { 504 enable_board_pin_mux(); 505 } 506 507 static void enable_vtt_regulator(void) 508 { 509 u32 temp; 510 511 /* enable module */ 512 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 513 514 /* enable output for GPIO5_7 */ 515 writel(GPIO_SETDATAOUT(7), 516 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 517 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 518 temp = temp & ~(GPIO_OE_ENABLE(7)); 519 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 520 } 521 522 void sdram_init(void) 523 { 524 /* 525 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 526 * GP EMV has 1GB DDR3 connected to EMIF 527 * along with VTT regulator. 528 */ 529 if (board_is_eposevm()) { 530 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 531 } else if (board_is_evm_14_or_later()) { 532 enable_vtt_regulator(); 533 config_ddr(0, &ioregs_ddr3, NULL, NULL, 534 &ddr3_emif_regs_400Mhz_production, 0); 535 } else if (board_is_evm_12_or_later()) { 536 enable_vtt_regulator(); 537 config_ddr(0, &ioregs_ddr3, NULL, NULL, 538 &ddr3_emif_regs_400Mhz_beta, 0); 539 } else if (board_is_evm()) { 540 enable_vtt_regulator(); 541 config_ddr(0, &ioregs_ddr3, NULL, NULL, 542 &ddr3_emif_regs_400Mhz, 0); 543 } else if (board_is_sk()) { 544 config_ddr(400, &ioregs_ddr3, NULL, NULL, 545 &ddr3_sk_emif_regs_400Mhz, 0); 546 } else if (board_is_idk()) { 547 config_ddr(400, &ioregs_ddr3, NULL, NULL, 548 &ddr3_idk_emif_regs_400Mhz, 0); 549 } 550 } 551 #endif 552 553 /* setup board specific PMIC */ 554 int power_init_board(void) 555 { 556 struct pmic *p; 557 558 if (board_is_idk()) { 559 power_tps62362_init(I2C_PMIC); 560 p = pmic_get("TPS62362"); 561 if (p && !pmic_probe(p)) 562 puts("PMIC: TPS62362\n"); 563 } else { 564 power_tps65218_init(I2C_PMIC); 565 p = pmic_get("TPS65218_PMIC"); 566 if (p && !pmic_probe(p)) 567 puts("PMIC: TPS65218\n"); 568 } 569 570 return 0; 571 } 572 573 int board_init(void) 574 { 575 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; 576 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, 577 modena_init0_bw_integer, modena_init0_watermark_0; 578 579 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 580 gpmc_init(); 581 582 /* Clear all important bits for DSS errata that may need to be tweaked*/ 583 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & 584 MREQPRIO_0_SAB_INIT0_MASK; 585 586 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; 587 588 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & 589 BW_LIMITER_BW_FRAC_MASK; 590 591 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & 592 BW_LIMITER_BW_INT_MASK; 593 594 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & 595 BW_LIMITER_BW_WATERMARK_MASK; 596 597 /* Setting MReq Priority of the DSS*/ 598 mreqprio_0 |= 0x77; 599 600 /* 601 * Set L3 Fast Configuration Register 602 * Limiting bandwith for ARM core to 700 MBPS 603 */ 604 modena_init0_bw_fractional |= 0x10; 605 modena_init0_bw_integer |= 0x3; 606 607 writel(mreqprio_0, &cdev->mreqprio_0); 608 writel(mreqprio_1, &cdev->mreqprio_1); 609 610 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); 611 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); 612 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); 613 614 return 0; 615 } 616 617 #ifdef CONFIG_BOARD_LATE_INIT 618 int board_late_init(void) 619 { 620 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 621 set_board_info_env(NULL); 622 623 /* 624 * Default FIT boot on HS devices. Non FIT images are not allowed 625 * on HS devices. 626 */ 627 if (get_device_type() == HS_DEVICE) 628 setenv("boot_fit", "1"); 629 #endif 630 return 0; 631 } 632 #endif 633 634 #ifdef CONFIG_USB_DWC3 635 static struct dwc3_device usb_otg_ss1 = { 636 .maximum_speed = USB_SPEED_HIGH, 637 .base = USB_OTG_SS1_BASE, 638 .tx_fifo_resize = false, 639 .index = 0, 640 }; 641 642 static struct dwc3_omap_device usb_otg_ss1_glue = { 643 .base = (void *)USB_OTG_SS1_GLUE_BASE, 644 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 645 .index = 0, 646 }; 647 648 static struct ti_usb_phy_device usb_phy1_device = { 649 .usb2_phy_power = (void *)USB2_PHY1_POWER, 650 .index = 0, 651 }; 652 653 static struct dwc3_device usb_otg_ss2 = { 654 .maximum_speed = USB_SPEED_HIGH, 655 .base = USB_OTG_SS2_BASE, 656 .tx_fifo_resize = false, 657 .index = 1, 658 }; 659 660 static struct dwc3_omap_device usb_otg_ss2_glue = { 661 .base = (void *)USB_OTG_SS2_GLUE_BASE, 662 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 663 .index = 1, 664 }; 665 666 static struct ti_usb_phy_device usb_phy2_device = { 667 .usb2_phy_power = (void *)USB2_PHY2_POWER, 668 .index = 1, 669 }; 670 671 int usb_gadget_handle_interrupts(int index) 672 { 673 u32 status; 674 675 status = dwc3_omap_uboot_interrupt_status(index); 676 if (status) 677 dwc3_uboot_handle_interrupt(index); 678 679 return 0; 680 } 681 #endif /* CONFIG_USB_DWC3 */ 682 683 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 684 int omap_xhci_board_usb_init(int index, enum usb_init_type init) 685 { 686 enable_usb_clocks(index); 687 #ifdef CONFIG_USB_DWC3 688 switch (index) { 689 case 0: 690 if (init == USB_INIT_DEVICE) { 691 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 692 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 693 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 694 ti_usb_phy_uboot_init(&usb_phy1_device); 695 dwc3_uboot_init(&usb_otg_ss1); 696 } 697 break; 698 case 1: 699 if (init == USB_INIT_DEVICE) { 700 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 701 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 702 ti_usb_phy_uboot_init(&usb_phy2_device); 703 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 704 dwc3_uboot_init(&usb_otg_ss2); 705 } 706 break; 707 default: 708 printf("Invalid Controller Index\n"); 709 } 710 #endif 711 712 return 0; 713 } 714 715 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init) 716 { 717 #ifdef CONFIG_USB_DWC3 718 switch (index) { 719 case 0: 720 case 1: 721 if (init == USB_INIT_DEVICE) { 722 ti_usb_phy_uboot_exit(index); 723 dwc3_uboot_exit(index); 724 dwc3_omap_uboot_exit(index); 725 } 726 break; 727 default: 728 printf("Invalid Controller Index\n"); 729 } 730 #endif 731 disable_usb_clocks(index); 732 733 return 0; 734 } 735 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 736 737 #ifdef CONFIG_DRIVER_TI_CPSW 738 739 static void cpsw_control(int enabled) 740 { 741 /* Additional controls can be added here */ 742 return; 743 } 744 745 static struct cpsw_slave_data cpsw_slaves[] = { 746 { 747 .slave_reg_ofs = 0x208, 748 .sliver_reg_ofs = 0xd80, 749 .phy_addr = 16, 750 }, 751 { 752 .slave_reg_ofs = 0x308, 753 .sliver_reg_ofs = 0xdc0, 754 .phy_addr = 1, 755 }, 756 }; 757 758 static struct cpsw_platform_data cpsw_data = { 759 .mdio_base = CPSW_MDIO_BASE, 760 .cpsw_base = CPSW_BASE, 761 .mdio_div = 0xff, 762 .channels = 8, 763 .cpdma_reg_ofs = 0x800, 764 .slaves = 1, 765 .slave_data = cpsw_slaves, 766 .ale_reg_ofs = 0xd00, 767 .ale_entries = 1024, 768 .host_port_reg_ofs = 0x108, 769 .hw_stats_reg_ofs = 0x900, 770 .bd_ram_ofs = 0x2000, 771 .mac_control = (1 << 5), 772 .control = cpsw_control, 773 .host_port_num = 0, 774 .version = CPSW_CTRL_VERSION_2, 775 }; 776 777 int board_eth_init(bd_t *bis) 778 { 779 int rv; 780 uint8_t mac_addr[6]; 781 uint32_t mac_hi, mac_lo; 782 783 /* try reading mac address from efuse */ 784 mac_lo = readl(&cdev->macid0l); 785 mac_hi = readl(&cdev->macid0h); 786 mac_addr[0] = mac_hi & 0xFF; 787 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 788 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 789 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 790 mac_addr[4] = mac_lo & 0xFF; 791 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 792 793 if (!getenv("ethaddr")) { 794 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 795 if (is_valid_ethaddr(mac_addr)) 796 eth_setenv_enetaddr("ethaddr", mac_addr); 797 } 798 799 mac_lo = readl(&cdev->macid1l); 800 mac_hi = readl(&cdev->macid1h); 801 mac_addr[0] = mac_hi & 0xFF; 802 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 803 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 804 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 805 mac_addr[4] = mac_lo & 0xFF; 806 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 807 808 if (!getenv("eth1addr")) { 809 if (is_valid_ethaddr(mac_addr)) 810 eth_setenv_enetaddr("eth1addr", mac_addr); 811 } 812 813 if (board_is_eposevm()) { 814 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 815 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 816 cpsw_slaves[0].phy_addr = 16; 817 } else if (board_is_sk()) { 818 writel(RGMII_MODE_ENABLE, &cdev->miisel); 819 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 820 cpsw_slaves[0].phy_addr = 4; 821 cpsw_slaves[1].phy_addr = 5; 822 } else if (board_is_idk()) { 823 writel(RGMII_MODE_ENABLE, &cdev->miisel); 824 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 825 cpsw_slaves[0].phy_addr = 0; 826 } else { 827 writel(RGMII_MODE_ENABLE, &cdev->miisel); 828 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 829 cpsw_slaves[0].phy_addr = 0; 830 } 831 832 rv = cpsw_register(&cpsw_data); 833 if (rv < 0) 834 printf("Error %d registering CPSW switch\n", rv); 835 836 return rv; 837 } 838 #endif 839 840 #ifdef CONFIG_SPL_LOAD_FIT 841 int board_fit_config_name_match(const char *name) 842 { 843 if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) 844 return 0; 845 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) 846 return 0; 847 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) 848 return 0; 849 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) 850 return 0; 851 else 852 return -1; 853 } 854 #endif 855 856 #ifdef CONFIG_TI_SECURE_DEVICE 857 void board_fit_image_post_process(void **p_image, size_t *p_size) 858 { 859 secure_boot_verify_image(p_image, p_size); 860 } 861 #endif 862