1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <spl.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/mux.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/emif.h> 21 #include "board.h" 22 #include <power/tps65218.h> 23 #include <miiphy.h> 24 #include <cpsw.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 29 30 /* 31 * Read header information from EEPROM into global structure. 32 */ 33 static int read_eeprom(struct am43xx_board_id *header) 34 { 35 /* Check if baseboard eeprom is available */ 36 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 37 printf("Could not probe the EEPROM at 0x%x\n", 38 CONFIG_SYS_I2C_EEPROM_ADDR); 39 return -ENODEV; 40 } 41 42 /* read the eeprom using i2c */ 43 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 44 sizeof(struct am43xx_board_id))) { 45 printf("Could not read the EEPROM\n"); 46 return -EIO; 47 } 48 49 if (header->magic != 0xEE3355AA) { 50 /* 51 * read the eeprom using i2c again, 52 * but use only a 1 byte address 53 */ 54 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 55 sizeof(struct am43xx_board_id))) { 56 printf("Could not read the EEPROM at 0x%x\n", 57 CONFIG_SYS_I2C_EEPROM_ADDR); 58 return -EIO; 59 } 60 61 if (header->magic != 0xEE3355AA) { 62 printf("Incorrect magic number (0x%x) in EEPROM\n", 63 header->magic); 64 return -EINVAL; 65 } 66 } 67 68 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); 69 am43xx_board_name[sizeof(header->name)] = 0; 70 71 strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); 72 am43xx_board_rev[sizeof(header->version)] = 0; 73 74 return 0; 75 } 76 77 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 78 79 #define NUM_OPPS 6 80 81 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 82 { /* 19.2 MHz */ 83 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ 84 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 85 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ 86 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ 87 {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ 88 {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ 89 }, 90 { /* 24 MHz */ 91 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 92 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 93 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 94 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 95 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 96 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 97 }, 98 { /* 25 MHz */ 99 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 100 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 101 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 102 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 103 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 104 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 105 }, 106 { /* 26 MHz */ 107 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 108 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 109 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 110 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 111 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 112 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 113 }, 114 }; 115 116 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 117 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 118 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 119 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 120 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 121 }; 122 123 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 124 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 125 {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ 126 {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ 127 {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ 128 }; 129 130 const struct dpll_params epos_evm_dpll_ddr = { 131 266, 24, 1, -1, 1, -1, -1}; 132 133 const struct dpll_params gp_evm_dpll_ddr = { 134 400, 23, 1, -1, 1, -1, -1}; 135 136 const struct ctrl_ioregs ioregs_lpddr2 = { 137 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 138 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 139 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 140 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 141 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 142 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 143 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 144 .emif_sdram_config_ext = 0x1, 145 }; 146 147 const struct emif_regs emif_regs_lpddr2 = { 148 .sdram_config = 0x808012BA, 149 .ref_ctrl = 0x0000040D, 150 .sdram_tim1 = 0xEA86B411, 151 .sdram_tim2 = 0x103A094A, 152 .sdram_tim3 = 0x0F6BA37F, 153 .read_idle_ctrl = 0x00050000, 154 .zq_config = 0x50074BE4, 155 .temp_alert_config = 0x0, 156 .emif_rd_wr_lvl_rmp_win = 0x0, 157 .emif_rd_wr_lvl_rmp_ctl = 0x0, 158 .emif_rd_wr_lvl_ctl = 0x0, 159 .emif_ddr_phy_ctlr_1 = 0x0E084006, 160 .emif_rd_wr_exec_thresh = 0x80000405, 161 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 162 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 163 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 164 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 165 .emif_ddr_ext_phy_ctrl_5 = 0x00500050, 166 .emif_prio_class_serv_map = 0x80000001, 167 .emif_connect_id_serv_1_map = 0x80000094, 168 .emif_connect_id_serv_2_map = 0x00000000, 169 .emif_cos_config = 0x000FFFFF 170 }; 171 172 const u32 ext_phy_ctrl_const_base_lpddr2[] = { 173 0x00500050, 174 0x00350035, 175 0x00350035, 176 0x00350035, 177 0x00350035, 178 0x00350035, 179 0x00000000, 180 0x00000000, 181 0x00000000, 182 0x00000000, 183 0x00000000, 184 0x00000000, 185 0x00000000, 186 0x00000000, 187 0x00000000, 188 0x00000000, 189 0x00000000, 190 0x00000000, 191 0x40001000, 192 0x08102040 193 }; 194 195 const struct ctrl_ioregs ioregs_ddr3 = { 196 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 197 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 198 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 199 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 200 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 201 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 202 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 203 .emif_sdram_config_ext = 0x0143, 204 }; 205 206 const struct emif_regs ddr3_emif_regs_400Mhz = { 207 .sdram_config = 0x638413B2, 208 .ref_ctrl = 0x00000C30, 209 .sdram_tim1 = 0xEAAAD4DB, 210 .sdram_tim2 = 0x266B7FDA, 211 .sdram_tim3 = 0x107F8678, 212 .read_idle_ctrl = 0x00050000, 213 .zq_config = 0x50074BE4, 214 .temp_alert_config = 0x0, 215 .emif_ddr_phy_ctlr_1 = 0x0E004008, 216 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 217 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 218 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 219 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 220 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 221 .emif_rd_wr_lvl_rmp_win = 0x0, 222 .emif_rd_wr_lvl_rmp_ctl = 0x0, 223 .emif_rd_wr_lvl_ctl = 0x0, 224 .emif_rd_wr_exec_thresh = 0x80000405, 225 .emif_prio_class_serv_map = 0x80000001, 226 .emif_connect_id_serv_1_map = 0x80000094, 227 .emif_connect_id_serv_2_map = 0x00000000, 228 .emif_cos_config = 0x000FFFFF 229 }; 230 231 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ 232 const struct emif_regs ddr3_emif_regs_400Mhz_beta = { 233 .sdram_config = 0x638413B2, 234 .ref_ctrl = 0x00000C30, 235 .sdram_tim1 = 0xEAAAD4DB, 236 .sdram_tim2 = 0x266B7FDA, 237 .sdram_tim3 = 0x107F8678, 238 .read_idle_ctrl = 0x00050000, 239 .zq_config = 0x50074BE4, 240 .temp_alert_config = 0x0, 241 .emif_ddr_phy_ctlr_1 = 0x0E004008, 242 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 243 .emif_ddr_ext_phy_ctrl_2 = 0x00000065, 244 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 245 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, 246 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, 247 .emif_rd_wr_exec_thresh = 0x80000405, 248 .emif_prio_class_serv_map = 0x80000001, 249 .emif_connect_id_serv_1_map = 0x80000094, 250 .emif_connect_id_serv_2_map = 0x00000000, 251 .emif_cos_config = 0x000FFFFF 252 }; 253 254 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 255 const struct emif_regs ddr3_emif_regs_400Mhz_production = { 256 .sdram_config = 0x638413B2, 257 .ref_ctrl = 0x00000C30, 258 .sdram_tim1 = 0xEAAAD4DB, 259 .sdram_tim2 = 0x266B7FDA, 260 .sdram_tim3 = 0x107F8678, 261 .read_idle_ctrl = 0x00050000, 262 .zq_config = 0x50074BE4, 263 .temp_alert_config = 0x0, 264 .emif_ddr_phy_ctlr_1 = 0x0E004008, 265 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 266 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 267 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 268 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 269 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 270 .emif_rd_wr_exec_thresh = 0x80000405, 271 .emif_prio_class_serv_map = 0x80000001, 272 .emif_connect_id_serv_1_map = 0x80000094, 273 .emif_connect_id_serv_2_map = 0x00000000, 274 .emif_cos_config = 0x000FFFFF 275 }; 276 277 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { 278 .sdram_config = 0x638413b2, 279 .sdram_config2 = 0x00000000, 280 .ref_ctrl = 0x00000c30, 281 .sdram_tim1 = 0xeaaad4db, 282 .sdram_tim2 = 0x266b7fda, 283 .sdram_tim3 = 0x107f8678, 284 .read_idle_ctrl = 0x00050000, 285 .zq_config = 0x50074be4, 286 .temp_alert_config = 0x0, 287 .emif_ddr_phy_ctlr_1 = 0x0e084008, 288 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 289 .emif_ddr_ext_phy_ctrl_2 = 0x89, 290 .emif_ddr_ext_phy_ctrl_3 = 0x90, 291 .emif_ddr_ext_phy_ctrl_4 = 0x8e, 292 .emif_ddr_ext_phy_ctrl_5 = 0x8d, 293 .emif_rd_wr_lvl_rmp_win = 0x0, 294 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 295 .emif_rd_wr_lvl_ctl = 0x00000000, 296 .emif_rd_wr_exec_thresh = 0x80000000, 297 .emif_prio_class_serv_map = 0x80000001, 298 .emif_connect_id_serv_1_map = 0x80000094, 299 .emif_connect_id_serv_2_map = 0x00000000, 300 .emif_cos_config = 0x000FFFFF 301 }; 302 303 const u32 ext_phy_ctrl_const_base_ddr3[] = { 304 0x00400040, 305 0x00350035, 306 0x00350035, 307 0x00350035, 308 0x00350035, 309 0x00350035, 310 0x00000000, 311 0x00000000, 312 0x00000000, 313 0x00000000, 314 0x00000000, 315 0x00340034, 316 0x00340034, 317 0x00340034, 318 0x00340034, 319 0x00340034, 320 0x0, 321 0x0, 322 0x40000000, 323 0x08102040 324 }; 325 326 const u32 ext_phy_ctrl_const_base_ddr3_beta[] = { 327 0x00000000, 328 0x00000045, 329 0x00000046, 330 0x00000048, 331 0x00000047, 332 0x00000000, 333 0x0000004C, 334 0x00000070, 335 0x00000085, 336 0x000000A3, 337 0x00000000, 338 0x0000000C, 339 0x00000030, 340 0x00000045, 341 0x00000063, 342 0x00000000, 343 0x0, 344 0x0, 345 0x40000000, 346 0x08102040 347 }; 348 349 const u32 ext_phy_ctrl_const_base_ddr3_production[] = { 350 0x00000000, 351 0x00000044, 352 0x00000044, 353 0x00000046, 354 0x00000046, 355 0x00000000, 356 0x00000059, 357 0x00000077, 358 0x00000093, 359 0x000000A8, 360 0x00000000, 361 0x00000019, 362 0x00000037, 363 0x00000053, 364 0x00000068, 365 0x00000000, 366 0x0, 367 0x0, 368 0x40000000, 369 0x08102040 370 }; 371 372 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = { 373 /* first 5 are taken care by emif_regs */ 374 0x00700070, 375 376 0x00350035, 377 0x00350035, 378 0x00350035, 379 0x00350035, 380 0x00350035, 381 382 0x00000000, 383 0x00000000, 384 0x00000000, 385 0x00000000, 386 0x00000000, 387 388 0x00150015, 389 0x00150015, 390 0x00150015, 391 0x00150015, 392 0x00150015, 393 394 0x00800080, 395 0x00800080, 396 397 0x40000000, 398 399 0x08102040, 400 401 0x00000000, 402 0x00000000, 403 0x00000000, 404 0x00000000, 405 0x00000000, 406 0x00000000, 407 0x00000000, 408 0x00000000, 409 0x00000000, 410 0x00000000, 411 0x00000000, 412 }; 413 414 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 415 { 416 if (board_is_eposevm()) { 417 *regs = ext_phy_ctrl_const_base_lpddr2; 418 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 419 } else if (board_is_evm_14_or_later()) { 420 *regs = ext_phy_ctrl_const_base_ddr3_production; 421 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); 422 } else if (board_is_evm_12_or_later()) { 423 *regs = ext_phy_ctrl_const_base_ddr3_beta; 424 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); 425 } else if (board_is_gpevm()) { 426 *regs = ext_phy_ctrl_const_base_ddr3; 427 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); 428 } else if (board_is_sk()) { 429 *regs = ext_phy_ctrl_const_base_ddr3_sk; 430 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); 431 } 432 433 return; 434 } 435 436 const struct dpll_params *get_dpll_ddr_params(void) 437 { 438 if (board_is_eposevm()) 439 return &epos_evm_dpll_ddr; 440 else if (board_is_gpevm() || board_is_sk()) 441 return &gp_evm_dpll_ddr; 442 443 printf(" Board '%s' not supported\n", am43xx_board_name); 444 return NULL; 445 } 446 447 /* 448 * get_sys_clk_index : returns the index of the sys_clk read from 449 * ctrl status register. This value is either 450 * read from efuse or sysboot pins. 451 */ 452 static u32 get_sys_clk_index(void) 453 { 454 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 455 u32 ind = readl(&ctrl->statusreg), src; 456 457 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; 458 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ 459 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> 460 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); 461 else /* Value read from SYS BOOT pins */ 462 return ((ind & CTRL_SYSBOOT_15_14_MASK) >> 463 CTRL_SYSBOOT_15_14_SHIFT); 464 } 465 466 /* 467 * get_opp_offset: 468 * Returns the index for safest OPP of the device to boot. 469 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 470 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 471 * This data is read from dev_attribute register which is e-fused. 472 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 473 * OPP available. Lowest OPP starts with min_off. So returning the 474 * bit with rightmost '0'. 475 */ 476 static int get_opp_offset(int max_off, int min_off) 477 { 478 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 479 int opp, offset, i; 480 481 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 482 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 483 484 for (i = max_off; i >= min_off; i--) { 485 offset = opp & (1 << i); 486 if (!offset) 487 return i; 488 } 489 490 return min_off; 491 } 492 493 const struct dpll_params *get_dpll_mpu_params(void) 494 { 495 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 496 u32 ind = get_sys_clk_index(); 497 498 return &dpll_mpu[ind][opp]; 499 } 500 501 const struct dpll_params *get_dpll_core_params(void) 502 { 503 int ind = get_sys_clk_index(); 504 505 return &dpll_core[ind]; 506 } 507 508 const struct dpll_params *get_dpll_per_params(void) 509 { 510 int ind = get_sys_clk_index(); 511 512 return &dpll_per[ind]; 513 } 514 515 void scale_vcores(void) 516 { 517 const struct dpll_params *mpu_params; 518 int mpu_vdd; 519 struct am43xx_board_id header; 520 521 enable_i2c0_pin_mux(); 522 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 523 if (read_eeprom(&header) < 0) 524 puts("Could not get board ID.\n"); 525 526 /* Get the frequency */ 527 mpu_params = get_dpll_mpu_params(); 528 529 if (i2c_probe(TPS65218_CHIP_PM)) 530 return; 531 532 if (mpu_params->m == 1000) { 533 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 534 } else if (mpu_params->m == 600) { 535 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 536 } else { 537 puts("Unknown MPU clock, not scaling\n"); 538 return; 539 } 540 541 /* Set DCDC1 (CORE) voltage to 1.1V */ 542 if (tps65218_voltage_update(TPS65218_DCDC1, 543 TPS65218_DCDC_VOLT_SEL_1100MV)) { 544 puts("tps65218_voltage_update failure\n"); 545 return; 546 } 547 548 /* Set DCDC2 (MPU) voltage */ 549 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 550 puts("tps65218_voltage_update failure\n"); 551 return; 552 } 553 } 554 555 void set_uart_mux_conf(void) 556 { 557 enable_uart0_pin_mux(); 558 } 559 560 void set_mux_conf_regs(void) 561 { 562 enable_board_pin_mux(); 563 } 564 565 static void enable_vtt_regulator(void) 566 { 567 u32 temp; 568 569 /* enable module */ 570 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 571 572 /* enable output for GPIO5_7 */ 573 writel(GPIO_SETDATAOUT(7), 574 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 575 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 576 temp = temp & ~(GPIO_OE_ENABLE(7)); 577 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 578 } 579 580 void sdram_init(void) 581 { 582 /* 583 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 584 * GP EMV has 1GB DDR3 connected to EMIF 585 * along with VTT regulator. 586 */ 587 if (board_is_eposevm()) { 588 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 589 } else if (board_is_evm_14_or_later()) { 590 enable_vtt_regulator(); 591 config_ddr(0, &ioregs_ddr3, NULL, NULL, 592 &ddr3_emif_regs_400Mhz_production, 0); 593 } else if (board_is_evm_12_or_later()) { 594 enable_vtt_regulator(); 595 config_ddr(0, &ioregs_ddr3, NULL, NULL, 596 &ddr3_emif_regs_400Mhz_beta, 0); 597 } else if (board_is_gpevm()) { 598 enable_vtt_regulator(); 599 config_ddr(0, &ioregs_ddr3, NULL, NULL, 600 &ddr3_emif_regs_400Mhz, 0); 601 } else if (board_is_sk()) { 602 config_ddr(400, &ioregs_ddr3, NULL, NULL, 603 &ddr3_sk_emif_regs_400Mhz, 0); 604 } 605 } 606 #endif 607 608 int board_init(void) 609 { 610 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; 611 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, 612 modena_init0_bw_integer, modena_init0_watermark_0; 613 614 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 615 616 /* Clear all important bits for DSS errata that may need to be tweaked*/ 617 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & 618 MREQPRIO_0_SAB_INIT0_MASK; 619 620 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; 621 622 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & 623 BW_LIMITER_BW_FRAC_MASK; 624 625 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & 626 BW_LIMITER_BW_INT_MASK; 627 628 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & 629 BW_LIMITER_BW_WATERMARK_MASK; 630 631 /* Setting MReq Priority of the DSS*/ 632 mreqprio_0 |= 0x77; 633 634 /* 635 * Set L3 Fast Configuration Register 636 * Limiting bandwith for ARM core to 700 MBPS 637 */ 638 modena_init0_bw_fractional |= 0x10; 639 modena_init0_bw_integer |= 0x3; 640 641 writel(mreqprio_0, &cdev->mreqprio_0); 642 writel(mreqprio_1, &cdev->mreqprio_1); 643 644 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); 645 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); 646 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); 647 648 return 0; 649 } 650 651 #ifdef CONFIG_BOARD_LATE_INIT 652 int board_late_init(void) 653 { 654 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 655 char safe_string[HDR_NAME_LEN + 1]; 656 struct am43xx_board_id header; 657 658 if (read_eeprom(&header) < 0) 659 puts("Could not get board ID.\n"); 660 661 /* Now set variables based on the header. */ 662 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 663 safe_string[sizeof(header.name)] = 0; 664 setenv("board_name", safe_string); 665 666 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 667 safe_string[sizeof(header.version)] = 0; 668 setenv("board_rev", safe_string); 669 #endif 670 return 0; 671 } 672 #endif 673 674 #ifdef CONFIG_DRIVER_TI_CPSW 675 676 static void cpsw_control(int enabled) 677 { 678 /* Additional controls can be added here */ 679 return; 680 } 681 682 static struct cpsw_slave_data cpsw_slaves[] = { 683 { 684 .slave_reg_ofs = 0x208, 685 .sliver_reg_ofs = 0xd80, 686 .phy_addr = 16, 687 }, 688 { 689 .slave_reg_ofs = 0x308, 690 .sliver_reg_ofs = 0xdc0, 691 .phy_addr = 1, 692 }, 693 }; 694 695 static struct cpsw_platform_data cpsw_data = { 696 .mdio_base = CPSW_MDIO_BASE, 697 .cpsw_base = CPSW_BASE, 698 .mdio_div = 0xff, 699 .channels = 8, 700 .cpdma_reg_ofs = 0x800, 701 .slaves = 1, 702 .slave_data = cpsw_slaves, 703 .ale_reg_ofs = 0xd00, 704 .ale_entries = 1024, 705 .host_port_reg_ofs = 0x108, 706 .hw_stats_reg_ofs = 0x900, 707 .bd_ram_ofs = 0x2000, 708 .mac_control = (1 << 5), 709 .control = cpsw_control, 710 .host_port_num = 0, 711 .version = CPSW_CTRL_VERSION_2, 712 }; 713 714 int board_eth_init(bd_t *bis) 715 { 716 int rv; 717 uint8_t mac_addr[6]; 718 uint32_t mac_hi, mac_lo; 719 720 /* try reading mac address from efuse */ 721 mac_lo = readl(&cdev->macid0l); 722 mac_hi = readl(&cdev->macid0h); 723 mac_addr[0] = mac_hi & 0xFF; 724 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 725 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 726 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 727 mac_addr[4] = mac_lo & 0xFF; 728 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 729 730 if (!getenv("ethaddr")) { 731 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 732 if (is_valid_ether_addr(mac_addr)) 733 eth_setenv_enetaddr("ethaddr", mac_addr); 734 } 735 736 mac_lo = readl(&cdev->macid1l); 737 mac_hi = readl(&cdev->macid1h); 738 mac_addr[0] = mac_hi & 0xFF; 739 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 740 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 741 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 742 mac_addr[4] = mac_lo & 0xFF; 743 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 744 745 if (!getenv("eth1addr")) { 746 if (is_valid_ether_addr(mac_addr)) 747 eth_setenv_enetaddr("eth1addr", mac_addr); 748 } 749 750 if (board_is_eposevm()) { 751 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 752 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 753 cpsw_slaves[0].phy_addr = 16; 754 } else if (board_is_sk()) { 755 writel(RGMII_MODE_ENABLE, &cdev->miisel); 756 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 757 cpsw_slaves[0].phy_addr = 4; 758 cpsw_slaves[1].phy_addr = 5; 759 } else { 760 writel(RGMII_MODE_ENABLE, &cdev->miisel); 761 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 762 cpsw_slaves[0].phy_addr = 0; 763 } 764 765 rv = cpsw_register(&cpsw_data); 766 if (rv < 0) 767 printf("Error %d registering CPSW switch\n", rv); 768 769 return rv; 770 } 771 #endif 772