1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <linux/errno.h> 14 #include <spl.h> 15 #include <usb.h> 16 #include <asm/omap_sec_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/mux.h> 20 #include <asm/arch/ddr_defs.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/emif.h> 23 #include "../common/board_detect.h" 24 #include "board.h" 25 #include <power/pmic.h> 26 #include <power/tps65218.h> 27 #include <power/tps62362.h> 28 #include <miiphy.h> 29 #include <cpsw.h> 30 #include <linux/usb/gadget.h> 31 #include <dwc3-uboot.h> 32 #include <dwc3-omap-uboot.h> 33 #include <ti-usb-phy-uboot.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 38 39 /* 40 * Read header information from EEPROM into global structure. 41 */ 42 #ifdef CONFIG_TI_I2C_BOARD_DETECT 43 void do_board_detect(void) 44 { 45 if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR)) 46 printf("ti_i2c_eeprom_init failed\n"); 47 } 48 #endif 49 50 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 51 52 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 53 { /* 19.2 MHz */ 54 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ 55 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 56 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ 57 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ 58 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ 59 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ 60 }, 61 { /* 24 MHz */ 62 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 63 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 64 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 65 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 66 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 67 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 68 }, 69 { /* 25 MHz */ 70 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 71 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 72 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 73 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 74 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 75 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 76 }, 77 { /* 26 MHz */ 78 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 79 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 80 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 81 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 82 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 83 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 84 }, 85 }; 86 87 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 88 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ 89 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 90 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 91 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 92 }; 93 94 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 95 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 96 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ 97 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ 98 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ 99 }; 100 101 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { 102 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ 103 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ 104 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ 105 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ 106 }; 107 108 const struct dpll_params gp_evm_dpll_ddr = { 109 50, 2, 1, -1, 2, -1, -1}; 110 111 static const struct dpll_params idk_dpll_ddr = { 112 400, 23, 1, -1, 2, -1, -1 113 }; 114 115 static const u32 ext_phy_ctrl_const_base_lpddr2[] = { 116 0x00500050, 117 0x00350035, 118 0x00350035, 119 0x00350035, 120 0x00350035, 121 0x00350035, 122 0x00000000, 123 0x00000000, 124 0x00000000, 125 0x00000000, 126 0x00000000, 127 0x00000000, 128 0x00000000, 129 0x00000000, 130 0x00000000, 131 0x00000000, 132 0x00000000, 133 0x00000000, 134 0x40001000, 135 0x08102040 136 }; 137 138 const struct ctrl_ioregs ioregs_lpddr2 = { 139 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 140 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 141 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 142 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 143 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 144 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 145 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 146 .emif_sdram_config_ext = 0x1, 147 }; 148 149 const struct emif_regs emif_regs_lpddr2 = { 150 .sdram_config = 0x808012BA, 151 .ref_ctrl = 0x0000040D, 152 .sdram_tim1 = 0xEA86B411, 153 .sdram_tim2 = 0x103A094A, 154 .sdram_tim3 = 0x0F6BA37F, 155 .read_idle_ctrl = 0x00050000, 156 .zq_config = 0x50074BE4, 157 .temp_alert_config = 0x0, 158 .emif_rd_wr_lvl_rmp_win = 0x0, 159 .emif_rd_wr_lvl_rmp_ctl = 0x0, 160 .emif_rd_wr_lvl_ctl = 0x0, 161 .emif_ddr_phy_ctlr_1 = 0x0E284006, 162 .emif_rd_wr_exec_thresh = 0x80000405, 163 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 164 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 165 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 166 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 167 .emif_ddr_ext_phy_ctrl_5 = 0x00500050, 168 .emif_prio_class_serv_map = 0x80000001, 169 .emif_connect_id_serv_1_map = 0x80000094, 170 .emif_connect_id_serv_2_map = 0x00000000, 171 .emif_cos_config = 0x000FFFFF 172 }; 173 174 const struct ctrl_ioregs ioregs_ddr3 = { 175 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 176 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 177 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 178 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 179 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 180 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 181 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 182 .emif_sdram_config_ext = 0xc163, 183 }; 184 185 const struct emif_regs ddr3_emif_regs_400Mhz = { 186 .sdram_config = 0x638413B2, 187 .ref_ctrl = 0x00000C30, 188 .sdram_tim1 = 0xEAAAD4DB, 189 .sdram_tim2 = 0x266B7FDA, 190 .sdram_tim3 = 0x107F8678, 191 .read_idle_ctrl = 0x00050000, 192 .zq_config = 0x50074BE4, 193 .temp_alert_config = 0x0, 194 .emif_ddr_phy_ctlr_1 = 0x0E004008, 195 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 196 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 197 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 198 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 199 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 200 .emif_rd_wr_lvl_rmp_win = 0x0, 201 .emif_rd_wr_lvl_rmp_ctl = 0x0, 202 .emif_rd_wr_lvl_ctl = 0x0, 203 .emif_rd_wr_exec_thresh = 0x80000405, 204 .emif_prio_class_serv_map = 0x80000001, 205 .emif_connect_id_serv_1_map = 0x80000094, 206 .emif_connect_id_serv_2_map = 0x00000000, 207 .emif_cos_config = 0x000FFFFF 208 }; 209 210 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ 211 const struct emif_regs ddr3_emif_regs_400Mhz_beta = { 212 .sdram_config = 0x638413B2, 213 .ref_ctrl = 0x00000C30, 214 .sdram_tim1 = 0xEAAAD4DB, 215 .sdram_tim2 = 0x266B7FDA, 216 .sdram_tim3 = 0x107F8678, 217 .read_idle_ctrl = 0x00050000, 218 .zq_config = 0x50074BE4, 219 .temp_alert_config = 0x0, 220 .emif_ddr_phy_ctlr_1 = 0x0E004008, 221 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 222 .emif_ddr_ext_phy_ctrl_2 = 0x00000065, 223 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 224 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, 225 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, 226 .emif_rd_wr_exec_thresh = 0x80000405, 227 .emif_prio_class_serv_map = 0x80000001, 228 .emif_connect_id_serv_1_map = 0x80000094, 229 .emif_connect_id_serv_2_map = 0x00000000, 230 .emif_cos_config = 0x000FFFFF 231 }; 232 233 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 234 const struct emif_regs ddr3_emif_regs_400Mhz_production = { 235 .sdram_config = 0x638413B2, 236 .ref_ctrl = 0x00000C30, 237 .sdram_tim1 = 0xEAAAD4DB, 238 .sdram_tim2 = 0x266B7FDA, 239 .sdram_tim3 = 0x107F8678, 240 .read_idle_ctrl = 0x00050000, 241 .zq_config = 0x50074BE4, 242 .temp_alert_config = 0x0, 243 .emif_ddr_phy_ctlr_1 = 0x0E004008, 244 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 245 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 246 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 247 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 248 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 249 .emif_rd_wr_exec_thresh = 0x80000405, 250 .emif_prio_class_serv_map = 0x80000001, 251 .emif_connect_id_serv_1_map = 0x80000094, 252 .emif_connect_id_serv_2_map = 0x00000000, 253 .emif_cos_config = 0x000FFFFF 254 }; 255 256 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { 257 .sdram_config = 0x638413b2, 258 .sdram_config2 = 0x00000000, 259 .ref_ctrl = 0x00000c30, 260 .sdram_tim1 = 0xeaaad4db, 261 .sdram_tim2 = 0x266b7fda, 262 .sdram_tim3 = 0x107f8678, 263 .read_idle_ctrl = 0x00050000, 264 .zq_config = 0x50074be4, 265 .temp_alert_config = 0x0, 266 .emif_ddr_phy_ctlr_1 = 0x0e084008, 267 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 268 .emif_ddr_ext_phy_ctrl_2 = 0x89, 269 .emif_ddr_ext_phy_ctrl_3 = 0x90, 270 .emif_ddr_ext_phy_ctrl_4 = 0x8e, 271 .emif_ddr_ext_phy_ctrl_5 = 0x8d, 272 .emif_rd_wr_lvl_rmp_win = 0x0, 273 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 274 .emif_rd_wr_lvl_ctl = 0x00000000, 275 .emif_rd_wr_exec_thresh = 0x80000000, 276 .emif_prio_class_serv_map = 0x80000001, 277 .emif_connect_id_serv_1_map = 0x80000094, 278 .emif_connect_id_serv_2_map = 0x00000000, 279 .emif_cos_config = 0x000FFFFF 280 }; 281 282 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { 283 .sdram_config = 0x61a11b32, 284 .sdram_config2 = 0x00000000, 285 .ref_ctrl = 0x00000c30, 286 .sdram_tim1 = 0xeaaad4db, 287 .sdram_tim2 = 0x266b7fda, 288 .sdram_tim3 = 0x107f8678, 289 .read_idle_ctrl = 0x00050000, 290 .zq_config = 0x50074be4, 291 .temp_alert_config = 0x00000000, 292 .emif_ddr_phy_ctlr_1 = 0x00008009, 293 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 294 .emif_ddr_ext_phy_ctrl_2 = 0x00000040, 295 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, 296 .emif_ddr_ext_phy_ctrl_4 = 0x00000051, 297 .emif_ddr_ext_phy_ctrl_5 = 0x00000051, 298 .emif_rd_wr_lvl_rmp_win = 0x00000000, 299 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 300 .emif_rd_wr_lvl_ctl = 0x00000000, 301 .emif_rd_wr_exec_thresh = 0x00000405, 302 .emif_prio_class_serv_map = 0x00000000, 303 .emif_connect_id_serv_1_map = 0x00000000, 304 .emif_connect_id_serv_2_map = 0x00000000, 305 .emif_cos_config = 0x00ffffff 306 }; 307 308 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 309 { 310 if (board_is_eposevm()) { 311 *regs = ext_phy_ctrl_const_base_lpddr2; 312 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 313 } 314 315 return; 316 } 317 318 const struct dpll_params *get_dpll_ddr_params(void) 319 { 320 int ind = get_sys_clk_index(); 321 322 if (board_is_eposevm()) 323 return &epos_evm_dpll_ddr[ind]; 324 else if (board_is_evm() || board_is_sk()) 325 return &gp_evm_dpll_ddr; 326 else if (board_is_idk()) 327 return &idk_dpll_ddr; 328 329 printf(" Board '%s' not supported\n", board_ti_get_name()); 330 return NULL; 331 } 332 333 334 /* 335 * get_opp_offset: 336 * Returns the index for safest OPP of the device to boot. 337 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 338 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 339 * This data is read from dev_attribute register which is e-fused. 340 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 341 * OPP available. Lowest OPP starts with min_off. So returning the 342 * bit with rightmost '0'. 343 */ 344 static int get_opp_offset(int max_off, int min_off) 345 { 346 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 347 int opp, offset, i; 348 349 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 350 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 351 352 for (i = max_off; i >= min_off; i--) { 353 offset = opp & (1 << i); 354 if (!offset) 355 return i; 356 } 357 358 return min_off; 359 } 360 361 const struct dpll_params *get_dpll_mpu_params(void) 362 { 363 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 364 u32 ind = get_sys_clk_index(); 365 366 return &dpll_mpu[ind][opp]; 367 } 368 369 const struct dpll_params *get_dpll_core_params(void) 370 { 371 int ind = get_sys_clk_index(); 372 373 return &dpll_core[ind]; 374 } 375 376 const struct dpll_params *get_dpll_per_params(void) 377 { 378 int ind = get_sys_clk_index(); 379 380 return &dpll_per[ind]; 381 } 382 383 void scale_vcores_generic(u32 m) 384 { 385 int mpu_vdd; 386 387 if (i2c_probe(TPS65218_CHIP_PM)) 388 return; 389 390 switch (m) { 391 case 1000: 392 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 393 break; 394 case 800: 395 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; 396 break; 397 case 720: 398 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; 399 break; 400 case 600: 401 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 402 break; 403 case 300: 404 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; 405 break; 406 default: 407 puts("Unknown MPU clock, not scaling\n"); 408 return; 409 } 410 411 /* Set DCDC1 (CORE) voltage to 1.1V */ 412 if (tps65218_voltage_update(TPS65218_DCDC1, 413 TPS65218_DCDC_VOLT_SEL_1100MV)) { 414 printf("%s failure\n", __func__); 415 return; 416 } 417 418 /* Set DCDC2 (MPU) voltage */ 419 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 420 printf("%s failure\n", __func__); 421 return; 422 } 423 } 424 425 void scale_vcores_idk(u32 m) 426 { 427 int mpu_vdd; 428 429 if (i2c_probe(TPS62362_I2C_ADDR)) 430 return; 431 432 switch (m) { 433 case 1000: 434 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 435 break; 436 case 800: 437 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; 438 break; 439 case 720: 440 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; 441 break; 442 case 600: 443 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; 444 break; 445 case 300: 446 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 447 break; 448 default: 449 puts("Unknown MPU clock, not scaling\n"); 450 return; 451 } 452 453 /* Set VDD_MPU voltage */ 454 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { 455 printf("%s failure\n", __func__); 456 return; 457 } 458 } 459 460 void gpi2c_init(void) 461 { 462 /* When needed to be invoked prior to BSS initialization */ 463 static bool first_time = true; 464 465 if (first_time) { 466 enable_i2c0_pin_mux(); 467 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 468 CONFIG_SYS_OMAP24_I2C_SLAVE); 469 first_time = false; 470 } 471 } 472 473 void scale_vcores(void) 474 { 475 const struct dpll_params *mpu_params; 476 477 /* Ensure I2C is initialized for PMIC configuration */ 478 gpi2c_init(); 479 480 /* Get the frequency */ 481 mpu_params = get_dpll_mpu_params(); 482 483 if (board_is_idk()) 484 scale_vcores_idk(mpu_params->m); 485 else 486 scale_vcores_generic(mpu_params->m); 487 } 488 489 void set_uart_mux_conf(void) 490 { 491 enable_uart0_pin_mux(); 492 } 493 494 void set_mux_conf_regs(void) 495 { 496 enable_board_pin_mux(); 497 } 498 499 static void enable_vtt_regulator(void) 500 { 501 u32 temp; 502 503 /* enable module */ 504 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 505 506 /* enable output for GPIO5_7 */ 507 writel(GPIO_SETDATAOUT(7), 508 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 509 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 510 temp = temp & ~(GPIO_OE_ENABLE(7)); 511 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 512 } 513 514 void sdram_init(void) 515 { 516 /* 517 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 518 * GP EMV has 1GB DDR3 connected to EMIF 519 * along with VTT regulator. 520 */ 521 if (board_is_eposevm()) { 522 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 523 } else if (board_is_evm_14_or_later()) { 524 enable_vtt_regulator(); 525 config_ddr(0, &ioregs_ddr3, NULL, NULL, 526 &ddr3_emif_regs_400Mhz_production, 0); 527 } else if (board_is_evm_12_or_later()) { 528 enable_vtt_regulator(); 529 config_ddr(0, &ioregs_ddr3, NULL, NULL, 530 &ddr3_emif_regs_400Mhz_beta, 0); 531 } else if (board_is_evm()) { 532 enable_vtt_regulator(); 533 config_ddr(0, &ioregs_ddr3, NULL, NULL, 534 &ddr3_emif_regs_400Mhz, 0); 535 } else if (board_is_sk()) { 536 config_ddr(400, &ioregs_ddr3, NULL, NULL, 537 &ddr3_sk_emif_regs_400Mhz, 0); 538 } else if (board_is_idk()) { 539 config_ddr(400, &ioregs_ddr3, NULL, NULL, 540 &ddr3_idk_emif_regs_400Mhz, 0); 541 } 542 } 543 #endif 544 545 /* setup board specific PMIC */ 546 int power_init_board(void) 547 { 548 struct pmic *p; 549 550 if (board_is_idk()) { 551 power_tps62362_init(I2C_PMIC); 552 p = pmic_get("TPS62362"); 553 if (p && !pmic_probe(p)) 554 puts("PMIC: TPS62362\n"); 555 } else { 556 power_tps65218_init(I2C_PMIC); 557 p = pmic_get("TPS65218_PMIC"); 558 if (p && !pmic_probe(p)) 559 puts("PMIC: TPS65218\n"); 560 } 561 562 return 0; 563 } 564 565 int board_init(void) 566 { 567 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; 568 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, 569 modena_init0_bw_integer, modena_init0_watermark_0; 570 571 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 572 gpmc_init(); 573 574 /* Clear all important bits for DSS errata that may need to be tweaked*/ 575 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & 576 MREQPRIO_0_SAB_INIT0_MASK; 577 578 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; 579 580 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & 581 BW_LIMITER_BW_FRAC_MASK; 582 583 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & 584 BW_LIMITER_BW_INT_MASK; 585 586 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & 587 BW_LIMITER_BW_WATERMARK_MASK; 588 589 /* Setting MReq Priority of the DSS*/ 590 mreqprio_0 |= 0x77; 591 592 /* 593 * Set L3 Fast Configuration Register 594 * Limiting bandwith for ARM core to 700 MBPS 595 */ 596 modena_init0_bw_fractional |= 0x10; 597 modena_init0_bw_integer |= 0x3; 598 599 writel(mreqprio_0, &cdev->mreqprio_0); 600 writel(mreqprio_1, &cdev->mreqprio_1); 601 602 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); 603 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); 604 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); 605 606 return 0; 607 } 608 609 #ifdef CONFIG_BOARD_LATE_INIT 610 int board_late_init(void) 611 { 612 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 613 set_board_info_env(NULL); 614 615 /* 616 * Default FIT boot on HS devices. Non FIT images are not allowed 617 * on HS devices. 618 */ 619 if (get_device_type() == HS_DEVICE) 620 setenv("boot_fit", "1"); 621 #endif 622 return 0; 623 } 624 #endif 625 626 #ifdef CONFIG_USB_DWC3 627 static struct dwc3_device usb_otg_ss1 = { 628 .maximum_speed = USB_SPEED_HIGH, 629 .base = USB_OTG_SS1_BASE, 630 .tx_fifo_resize = false, 631 .index = 0, 632 }; 633 634 static struct dwc3_omap_device usb_otg_ss1_glue = { 635 .base = (void *)USB_OTG_SS1_GLUE_BASE, 636 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 637 .index = 0, 638 }; 639 640 static struct ti_usb_phy_device usb_phy1_device = { 641 .usb2_phy_power = (void *)USB2_PHY1_POWER, 642 .index = 0, 643 }; 644 645 static struct dwc3_device usb_otg_ss2 = { 646 .maximum_speed = USB_SPEED_HIGH, 647 .base = USB_OTG_SS2_BASE, 648 .tx_fifo_resize = false, 649 .index = 1, 650 }; 651 652 static struct dwc3_omap_device usb_otg_ss2_glue = { 653 .base = (void *)USB_OTG_SS2_GLUE_BASE, 654 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 655 .index = 1, 656 }; 657 658 static struct ti_usb_phy_device usb_phy2_device = { 659 .usb2_phy_power = (void *)USB2_PHY2_POWER, 660 .index = 1, 661 }; 662 663 int usb_gadget_handle_interrupts(int index) 664 { 665 u32 status; 666 667 status = dwc3_omap_uboot_interrupt_status(index); 668 if (status) 669 dwc3_uboot_handle_interrupt(index); 670 671 return 0; 672 } 673 #endif /* CONFIG_USB_DWC3 */ 674 675 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 676 int omap_xhci_board_usb_init(int index, enum usb_init_type init) 677 { 678 enable_usb_clocks(index); 679 #ifdef CONFIG_USB_DWC3 680 switch (index) { 681 case 0: 682 if (init == USB_INIT_DEVICE) { 683 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 684 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 685 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 686 ti_usb_phy_uboot_init(&usb_phy1_device); 687 dwc3_uboot_init(&usb_otg_ss1); 688 } 689 break; 690 case 1: 691 if (init == USB_INIT_DEVICE) { 692 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 693 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 694 ti_usb_phy_uboot_init(&usb_phy2_device); 695 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 696 dwc3_uboot_init(&usb_otg_ss2); 697 } 698 break; 699 default: 700 printf("Invalid Controller Index\n"); 701 } 702 #endif 703 704 return 0; 705 } 706 707 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init) 708 { 709 #ifdef CONFIG_USB_DWC3 710 switch (index) { 711 case 0: 712 case 1: 713 if (init == USB_INIT_DEVICE) { 714 ti_usb_phy_uboot_exit(index); 715 dwc3_uboot_exit(index); 716 dwc3_omap_uboot_exit(index); 717 } 718 break; 719 default: 720 printf("Invalid Controller Index\n"); 721 } 722 #endif 723 disable_usb_clocks(index); 724 725 return 0; 726 } 727 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 728 729 #ifdef CONFIG_DRIVER_TI_CPSW 730 731 static void cpsw_control(int enabled) 732 { 733 /* Additional controls can be added here */ 734 return; 735 } 736 737 static struct cpsw_slave_data cpsw_slaves[] = { 738 { 739 .slave_reg_ofs = 0x208, 740 .sliver_reg_ofs = 0xd80, 741 .phy_addr = 16, 742 }, 743 { 744 .slave_reg_ofs = 0x308, 745 .sliver_reg_ofs = 0xdc0, 746 .phy_addr = 1, 747 }, 748 }; 749 750 static struct cpsw_platform_data cpsw_data = { 751 .mdio_base = CPSW_MDIO_BASE, 752 .cpsw_base = CPSW_BASE, 753 .mdio_div = 0xff, 754 .channels = 8, 755 .cpdma_reg_ofs = 0x800, 756 .slaves = 1, 757 .slave_data = cpsw_slaves, 758 .ale_reg_ofs = 0xd00, 759 .ale_entries = 1024, 760 .host_port_reg_ofs = 0x108, 761 .hw_stats_reg_ofs = 0x900, 762 .bd_ram_ofs = 0x2000, 763 .mac_control = (1 << 5), 764 .control = cpsw_control, 765 .host_port_num = 0, 766 .version = CPSW_CTRL_VERSION_2, 767 }; 768 769 int board_eth_init(bd_t *bis) 770 { 771 int rv; 772 uint8_t mac_addr[6]; 773 uint32_t mac_hi, mac_lo; 774 775 /* try reading mac address from efuse */ 776 mac_lo = readl(&cdev->macid0l); 777 mac_hi = readl(&cdev->macid0h); 778 mac_addr[0] = mac_hi & 0xFF; 779 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 780 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 781 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 782 mac_addr[4] = mac_lo & 0xFF; 783 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 784 785 if (!getenv("ethaddr")) { 786 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 787 if (is_valid_ethaddr(mac_addr)) 788 eth_setenv_enetaddr("ethaddr", mac_addr); 789 } 790 791 mac_lo = readl(&cdev->macid1l); 792 mac_hi = readl(&cdev->macid1h); 793 mac_addr[0] = mac_hi & 0xFF; 794 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 795 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 796 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 797 mac_addr[4] = mac_lo & 0xFF; 798 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 799 800 if (!getenv("eth1addr")) { 801 if (is_valid_ethaddr(mac_addr)) 802 eth_setenv_enetaddr("eth1addr", mac_addr); 803 } 804 805 if (board_is_eposevm()) { 806 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 807 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 808 cpsw_slaves[0].phy_addr = 16; 809 } else if (board_is_sk()) { 810 writel(RGMII_MODE_ENABLE, &cdev->miisel); 811 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 812 cpsw_slaves[0].phy_addr = 4; 813 cpsw_slaves[1].phy_addr = 5; 814 } else if (board_is_idk()) { 815 writel(RGMII_MODE_ENABLE, &cdev->miisel); 816 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 817 cpsw_slaves[0].phy_addr = 0; 818 } else { 819 writel(RGMII_MODE_ENABLE, &cdev->miisel); 820 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 821 cpsw_slaves[0].phy_addr = 0; 822 } 823 824 rv = cpsw_register(&cpsw_data); 825 if (rv < 0) 826 printf("Error %d registering CPSW switch\n", rv); 827 828 return rv; 829 } 830 #endif 831 832 #ifdef CONFIG_SPL_LOAD_FIT 833 int board_fit_config_name_match(const char *name) 834 { 835 if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) 836 return 0; 837 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) 838 return 0; 839 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) 840 return 0; 841 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) 842 return 0; 843 else 844 return -1; 845 } 846 #endif 847 848 #ifdef CONFIG_TI_SECURE_DEVICE 849 void board_fit_image_post_process(void **p_image, size_t *p_size) 850 { 851 secure_boot_verify_image(p_image, p_size); 852 } 853 #endif 854