1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * board.c 4 * 5 * Board functions for TI AM43XX based boards 6 * 7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 8 */ 9 10 #include <common.h> 11 #include <environment.h> 12 #include <i2c.h> 13 #include <linux/errno.h> 14 #include <spl.h> 15 #include <usb.h> 16 #include <asm/omap_sec_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/mux.h> 20 #include <asm/arch/ddr_defs.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/emif.h> 23 #include <asm/omap_common.h> 24 #include "../common/board_detect.h" 25 #include "board.h" 26 #include <power/pmic.h> 27 #include <power/tps65218.h> 28 #include <power/tps62362.h> 29 #include <miiphy.h> 30 #include <cpsw.h> 31 #include <linux/usb/gadget.h> 32 #include <dwc3-uboot.h> 33 #include <dwc3-omap-uboot.h> 34 #include <ti-usb-phy-uboot.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 39 40 /* 41 * Read header information from EEPROM into global structure. 42 */ 43 #ifdef CONFIG_TI_I2C_BOARD_DETECT 44 void do_board_detect(void) 45 { 46 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 47 CONFIG_EEPROM_CHIP_ADDRESS)) 48 printf("ti_i2c_eeprom_init failed\n"); 49 } 50 #endif 51 52 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 53 54 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 55 { /* 19.2 MHz */ 56 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ 57 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 58 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ 59 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ 60 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ 61 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ 62 }, 63 { /* 24 MHz */ 64 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 65 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 66 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 67 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 68 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 69 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 70 }, 71 { /* 25 MHz */ 72 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 73 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 74 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 75 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 76 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 77 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 78 }, 79 { /* 26 MHz */ 80 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 81 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 82 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 83 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 84 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 85 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 86 }, 87 }; 88 89 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 90 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ 91 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 92 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 93 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 94 }; 95 96 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 97 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 98 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ 99 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ 100 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ 101 }; 102 103 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { 104 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ 105 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ 106 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ 107 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ 108 }; 109 110 const struct dpll_params gp_evm_dpll_ddr = { 111 50, 2, 1, -1, 2, -1, -1}; 112 113 static const struct dpll_params idk_dpll_ddr = { 114 400, 23, 1, -1, 2, -1, -1 115 }; 116 117 static const u32 ext_phy_ctrl_const_base_lpddr2[] = { 118 0x00500050, 119 0x00350035, 120 0x00350035, 121 0x00350035, 122 0x00350035, 123 0x00350035, 124 0x00000000, 125 0x00000000, 126 0x00000000, 127 0x00000000, 128 0x00000000, 129 0x00000000, 130 0x00000000, 131 0x00000000, 132 0x00000000, 133 0x00000000, 134 0x00000000, 135 0x00000000, 136 0x40001000, 137 0x08102040 138 }; 139 140 const struct ctrl_ioregs ioregs_lpddr2 = { 141 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 142 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 143 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 144 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 145 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 146 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 147 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 148 .emif_sdram_config_ext = 0x1, 149 }; 150 151 const struct emif_regs emif_regs_lpddr2 = { 152 .sdram_config = 0x808012BA, 153 .ref_ctrl = 0x0000040D, 154 .sdram_tim1 = 0xEA86B411, 155 .sdram_tim2 = 0x103A094A, 156 .sdram_tim3 = 0x0F6BA37F, 157 .read_idle_ctrl = 0x00050000, 158 .zq_config = 0x50074BE4, 159 .temp_alert_config = 0x0, 160 .emif_rd_wr_lvl_rmp_win = 0x0, 161 .emif_rd_wr_lvl_rmp_ctl = 0x0, 162 .emif_rd_wr_lvl_ctl = 0x0, 163 .emif_ddr_phy_ctlr_1 = 0x0E284006, 164 .emif_rd_wr_exec_thresh = 0x80000405, 165 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 166 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 167 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 168 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 169 .emif_ddr_ext_phy_ctrl_5 = 0x00500050, 170 .emif_prio_class_serv_map = 0x80000001, 171 .emif_connect_id_serv_1_map = 0x80000094, 172 .emif_connect_id_serv_2_map = 0x00000000, 173 .emif_cos_config = 0x000FFFFF 174 }; 175 176 const struct ctrl_ioregs ioregs_ddr3 = { 177 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 178 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 179 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 180 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 181 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 182 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 183 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 184 .emif_sdram_config_ext = 0xc163, 185 }; 186 187 const struct emif_regs ddr3_emif_regs_400Mhz = { 188 .sdram_config = 0x638413B2, 189 .ref_ctrl = 0x00000C30, 190 .sdram_tim1 = 0xEAAAD4DB, 191 .sdram_tim2 = 0x266B7FDA, 192 .sdram_tim3 = 0x107F8678, 193 .read_idle_ctrl = 0x00050000, 194 .zq_config = 0x50074BE4, 195 .temp_alert_config = 0x0, 196 .emif_ddr_phy_ctlr_1 = 0x0E004008, 197 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 198 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 199 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 200 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 201 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 202 .emif_rd_wr_lvl_rmp_win = 0x0, 203 .emif_rd_wr_lvl_rmp_ctl = 0x0, 204 .emif_rd_wr_lvl_ctl = 0x0, 205 .emif_rd_wr_exec_thresh = 0x80000405, 206 .emif_prio_class_serv_map = 0x80000001, 207 .emif_connect_id_serv_1_map = 0x80000094, 208 .emif_connect_id_serv_2_map = 0x00000000, 209 .emif_cos_config = 0x000FFFFF 210 }; 211 212 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ 213 const struct emif_regs ddr3_emif_regs_400Mhz_beta = { 214 .sdram_config = 0x638413B2, 215 .ref_ctrl = 0x00000C30, 216 .sdram_tim1 = 0xEAAAD4DB, 217 .sdram_tim2 = 0x266B7FDA, 218 .sdram_tim3 = 0x107F8678, 219 .read_idle_ctrl = 0x00050000, 220 .zq_config = 0x50074BE4, 221 .temp_alert_config = 0x0, 222 .emif_ddr_phy_ctlr_1 = 0x0E004008, 223 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 224 .emif_ddr_ext_phy_ctrl_2 = 0x00000065, 225 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 226 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, 227 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, 228 .emif_rd_wr_exec_thresh = 0x80000405, 229 .emif_prio_class_serv_map = 0x80000001, 230 .emif_connect_id_serv_1_map = 0x80000094, 231 .emif_connect_id_serv_2_map = 0x00000000, 232 .emif_cos_config = 0x000FFFFF 233 }; 234 235 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 236 const struct emif_regs ddr3_emif_regs_400Mhz_production = { 237 .sdram_config = 0x638413B2, 238 .ref_ctrl = 0x00000C30, 239 .sdram_tim1 = 0xEAAAD4DB, 240 .sdram_tim2 = 0x266B7FDA, 241 .sdram_tim3 = 0x107F8678, 242 .read_idle_ctrl = 0x00050000, 243 .zq_config = 0x50074BE4, 244 .temp_alert_config = 0x0, 245 .emif_ddr_phy_ctlr_1 = 0x0E004008, 246 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 247 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 248 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 249 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 250 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 251 .emif_rd_wr_exec_thresh = 0x80000405, 252 .emif_prio_class_serv_map = 0x80000001, 253 .emif_connect_id_serv_1_map = 0x80000094, 254 .emif_connect_id_serv_2_map = 0x00000000, 255 .emif_cos_config = 0x000FFFFF 256 }; 257 258 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { 259 .sdram_config = 0x638413b2, 260 .sdram_config2 = 0x00000000, 261 .ref_ctrl = 0x00000c30, 262 .sdram_tim1 = 0xeaaad4db, 263 .sdram_tim2 = 0x266b7fda, 264 .sdram_tim3 = 0x107f8678, 265 .read_idle_ctrl = 0x00050000, 266 .zq_config = 0x50074be4, 267 .temp_alert_config = 0x0, 268 .emif_ddr_phy_ctlr_1 = 0x0e084008, 269 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 270 .emif_ddr_ext_phy_ctrl_2 = 0x89, 271 .emif_ddr_ext_phy_ctrl_3 = 0x90, 272 .emif_ddr_ext_phy_ctrl_4 = 0x8e, 273 .emif_ddr_ext_phy_ctrl_5 = 0x8d, 274 .emif_rd_wr_lvl_rmp_win = 0x0, 275 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 276 .emif_rd_wr_lvl_ctl = 0x00000000, 277 .emif_rd_wr_exec_thresh = 0x80000000, 278 .emif_prio_class_serv_map = 0x80000001, 279 .emif_connect_id_serv_1_map = 0x80000094, 280 .emif_connect_id_serv_2_map = 0x00000000, 281 .emif_cos_config = 0x000FFFFF 282 }; 283 284 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { 285 .sdram_config = 0x61a11b32, 286 .sdram_config2 = 0x00000000, 287 .ref_ctrl = 0x00000c30, 288 .sdram_tim1 = 0xeaaad4db, 289 .sdram_tim2 = 0x266b7fda, 290 .sdram_tim3 = 0x107f8678, 291 .read_idle_ctrl = 0x00050000, 292 .zq_config = 0x50074be4, 293 .temp_alert_config = 0x00000000, 294 .emif_ddr_phy_ctlr_1 = 0x00008009, 295 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 296 .emif_ddr_ext_phy_ctrl_2 = 0x00000040, 297 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, 298 .emif_ddr_ext_phy_ctrl_4 = 0x00000051, 299 .emif_ddr_ext_phy_ctrl_5 = 0x00000051, 300 .emif_rd_wr_lvl_rmp_win = 0x00000000, 301 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 302 .emif_rd_wr_lvl_ctl = 0x00000000, 303 .emif_rd_wr_exec_thresh = 0x00000405, 304 .emif_prio_class_serv_map = 0x00000000, 305 .emif_connect_id_serv_1_map = 0x00000000, 306 .emif_connect_id_serv_2_map = 0x00000000, 307 .emif_cos_config = 0x00ffffff 308 }; 309 310 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 311 { 312 if (board_is_eposevm()) { 313 *regs = ext_phy_ctrl_const_base_lpddr2; 314 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 315 } 316 317 return; 318 } 319 320 const struct dpll_params *get_dpll_ddr_params(void) 321 { 322 int ind = get_sys_clk_index(); 323 324 if (board_is_eposevm()) 325 return &epos_evm_dpll_ddr[ind]; 326 else if (board_is_evm() || board_is_sk()) 327 return &gp_evm_dpll_ddr; 328 else if (board_is_idk()) 329 return &idk_dpll_ddr; 330 331 printf(" Board '%s' not supported\n", board_ti_get_name()); 332 return NULL; 333 } 334 335 336 /* 337 * get_opp_offset: 338 * Returns the index for safest OPP of the device to boot. 339 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 340 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 341 * This data is read from dev_attribute register which is e-fused. 342 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 343 * OPP available. Lowest OPP starts with min_off. So returning the 344 * bit with rightmost '0'. 345 */ 346 static int get_opp_offset(int max_off, int min_off) 347 { 348 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 349 int opp, offset, i; 350 351 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 352 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 353 354 for (i = max_off; i >= min_off; i--) { 355 offset = opp & (1 << i); 356 if (!offset) 357 return i; 358 } 359 360 return min_off; 361 } 362 363 const struct dpll_params *get_dpll_mpu_params(void) 364 { 365 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 366 u32 ind = get_sys_clk_index(); 367 368 return &dpll_mpu[ind][opp]; 369 } 370 371 const struct dpll_params *get_dpll_core_params(void) 372 { 373 int ind = get_sys_clk_index(); 374 375 return &dpll_core[ind]; 376 } 377 378 const struct dpll_params *get_dpll_per_params(void) 379 { 380 int ind = get_sys_clk_index(); 381 382 return &dpll_per[ind]; 383 } 384 385 void scale_vcores_generic(u32 m) 386 { 387 int mpu_vdd, ddr_volt; 388 389 if (i2c_probe(TPS65218_CHIP_PM)) 390 return; 391 392 switch (m) { 393 case 1000: 394 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 395 break; 396 case 800: 397 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; 398 break; 399 case 720: 400 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; 401 break; 402 case 600: 403 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 404 break; 405 case 300: 406 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; 407 break; 408 default: 409 puts("Unknown MPU clock, not scaling\n"); 410 return; 411 } 412 413 /* Set DCDC1 (CORE) voltage to 1.1V */ 414 if (tps65218_voltage_update(TPS65218_DCDC1, 415 TPS65218_DCDC_VOLT_SEL_1100MV)) { 416 printf("%s failure\n", __func__); 417 return; 418 } 419 420 /* Set DCDC2 (MPU) voltage */ 421 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 422 printf("%s failure\n", __func__); 423 return; 424 } 425 426 if (board_is_eposevm()) 427 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV; 428 else 429 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV; 430 431 /* Set DCDC3 (DDR) voltage */ 432 if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) { 433 printf("%s failure\n", __func__); 434 return; 435 } 436 } 437 438 void scale_vcores_idk(u32 m) 439 { 440 int mpu_vdd; 441 442 if (i2c_probe(TPS62362_I2C_ADDR)) 443 return; 444 445 switch (m) { 446 case 1000: 447 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 448 break; 449 case 800: 450 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; 451 break; 452 case 720: 453 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; 454 break; 455 case 600: 456 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; 457 break; 458 case 300: 459 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 460 break; 461 default: 462 puts("Unknown MPU clock, not scaling\n"); 463 return; 464 } 465 466 /* Set VDD_MPU voltage */ 467 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { 468 printf("%s failure\n", __func__); 469 return; 470 } 471 } 472 473 void gpi2c_init(void) 474 { 475 /* When needed to be invoked prior to BSS initialization */ 476 static bool first_time = true; 477 478 if (first_time) { 479 enable_i2c0_pin_mux(); 480 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 481 CONFIG_SYS_OMAP24_I2C_SLAVE); 482 first_time = false; 483 } 484 } 485 486 void scale_vcores(void) 487 { 488 const struct dpll_params *mpu_params; 489 490 /* Ensure I2C is initialized for PMIC configuration */ 491 gpi2c_init(); 492 493 /* Get the frequency */ 494 mpu_params = get_dpll_mpu_params(); 495 496 if (board_is_idk()) 497 scale_vcores_idk(mpu_params->m); 498 else 499 scale_vcores_generic(mpu_params->m); 500 } 501 502 void set_uart_mux_conf(void) 503 { 504 enable_uart0_pin_mux(); 505 } 506 507 void set_mux_conf_regs(void) 508 { 509 enable_board_pin_mux(); 510 } 511 512 static void enable_vtt_regulator(void) 513 { 514 u32 temp; 515 516 /* enable module */ 517 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 518 519 /* enable output for GPIO5_7 */ 520 writel(GPIO_SETDATAOUT(7), 521 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 522 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 523 temp = temp & ~(GPIO_OE_ENABLE(7)); 524 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 525 } 526 527 enum { 528 RTC_BOARD_EPOS = 1, 529 RTC_BOARD_EVM14, 530 RTC_BOARD_EVM12, 531 RTC_BOARD_GPEVM, 532 RTC_BOARD_SK, 533 }; 534 535 /* 536 * In the rtc_only+DRR in self-refresh boot path we have the board type info 537 * in the rtc scratch pad register hence we bypass the costly i2c reads to 538 * eeprom and directly programthe board name string 539 */ 540 void rtc_only_update_board_type(u32 btype) 541 { 542 const char *name = ""; 543 const char *rev = "1.0"; 544 545 switch (btype) { 546 case RTC_BOARD_EPOS: 547 name = "AM43EPOS"; 548 break; 549 case RTC_BOARD_EVM14: 550 name = "AM43__GP"; 551 rev = "1.4"; 552 break; 553 case RTC_BOARD_EVM12: 554 name = "AM43__GP"; 555 rev = "1.2"; 556 break; 557 case RTC_BOARD_GPEVM: 558 name = "AM43__GP"; 559 break; 560 case RTC_BOARD_SK: 561 name = "AM43__SK"; 562 break; 563 } 564 ti_i2c_eeprom_am_set(name, rev); 565 } 566 567 u32 rtc_only_get_board_type(void) 568 { 569 if (board_is_eposevm()) 570 return RTC_BOARD_EPOS; 571 else if (board_is_evm_14_or_later()) 572 return RTC_BOARD_EVM14; 573 else if (board_is_evm_12_or_later()) 574 return RTC_BOARD_EVM12; 575 else if (board_is_gpevm()) 576 return RTC_BOARD_GPEVM; 577 else if (board_is_sk()) 578 return RTC_BOARD_SK; 579 580 return 0; 581 } 582 583 void sdram_init(void) 584 { 585 /* 586 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 587 * GP EMV has 1GB DDR3 connected to EMIF 588 * along with VTT regulator. 589 */ 590 if (board_is_eposevm()) { 591 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 592 } else if (board_is_evm_14_or_later()) { 593 enable_vtt_regulator(); 594 config_ddr(0, &ioregs_ddr3, NULL, NULL, 595 &ddr3_emif_regs_400Mhz_production, 0); 596 } else if (board_is_evm_12_or_later()) { 597 enable_vtt_regulator(); 598 config_ddr(0, &ioregs_ddr3, NULL, NULL, 599 &ddr3_emif_regs_400Mhz_beta, 0); 600 } else if (board_is_evm()) { 601 enable_vtt_regulator(); 602 config_ddr(0, &ioregs_ddr3, NULL, NULL, 603 &ddr3_emif_regs_400Mhz, 0); 604 } else if (board_is_sk()) { 605 config_ddr(400, &ioregs_ddr3, NULL, NULL, 606 &ddr3_sk_emif_regs_400Mhz, 0); 607 } else if (board_is_idk()) { 608 config_ddr(400, &ioregs_ddr3, NULL, NULL, 609 &ddr3_idk_emif_regs_400Mhz, 0); 610 } 611 } 612 #endif 613 614 /* setup board specific PMIC */ 615 int power_init_board(void) 616 { 617 struct pmic *p; 618 619 if (board_is_idk()) { 620 power_tps62362_init(I2C_PMIC); 621 p = pmic_get("TPS62362"); 622 if (p && !pmic_probe(p)) 623 puts("PMIC: TPS62362\n"); 624 } else { 625 power_tps65218_init(I2C_PMIC); 626 p = pmic_get("TPS65218_PMIC"); 627 if (p && !pmic_probe(p)) 628 puts("PMIC: TPS65218\n"); 629 } 630 631 return 0; 632 } 633 634 int board_init(void) 635 { 636 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; 637 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, 638 modena_init0_bw_integer, modena_init0_watermark_0; 639 640 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 641 gpmc_init(); 642 643 /* 644 * Call this to initialize *ctrl again 645 */ 646 hw_data_init(); 647 648 /* Clear all important bits for DSS errata that may need to be tweaked*/ 649 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & 650 MREQPRIO_0_SAB_INIT0_MASK; 651 652 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; 653 654 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & 655 BW_LIMITER_BW_FRAC_MASK; 656 657 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & 658 BW_LIMITER_BW_INT_MASK; 659 660 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & 661 BW_LIMITER_BW_WATERMARK_MASK; 662 663 /* Setting MReq Priority of the DSS*/ 664 mreqprio_0 |= 0x77; 665 666 /* 667 * Set L3 Fast Configuration Register 668 * Limiting bandwith for ARM core to 700 MBPS 669 */ 670 modena_init0_bw_fractional |= 0x10; 671 modena_init0_bw_integer |= 0x3; 672 673 writel(mreqprio_0, &cdev->mreqprio_0); 674 writel(mreqprio_1, &cdev->mreqprio_1); 675 676 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); 677 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); 678 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); 679 680 return 0; 681 } 682 683 #ifdef CONFIG_BOARD_LATE_INIT 684 int board_late_init(void) 685 { 686 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 687 set_board_info_env(NULL); 688 689 /* 690 * Default FIT boot on HS devices. Non FIT images are not allowed 691 * on HS devices. 692 */ 693 if (get_device_type() == HS_DEVICE) 694 env_set("boot_fit", "1"); 695 #endif 696 return 0; 697 } 698 #endif 699 700 #ifdef CONFIG_USB_DWC3 701 static struct dwc3_device usb_otg_ss1 = { 702 .maximum_speed = USB_SPEED_HIGH, 703 .base = USB_OTG_SS1_BASE, 704 .tx_fifo_resize = false, 705 .index = 0, 706 }; 707 708 static struct dwc3_omap_device usb_otg_ss1_glue = { 709 .base = (void *)USB_OTG_SS1_GLUE_BASE, 710 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 711 .index = 0, 712 }; 713 714 static struct ti_usb_phy_device usb_phy1_device = { 715 .usb2_phy_power = (void *)USB2_PHY1_POWER, 716 .index = 0, 717 }; 718 719 static struct dwc3_device usb_otg_ss2 = { 720 .maximum_speed = USB_SPEED_HIGH, 721 .base = USB_OTG_SS2_BASE, 722 .tx_fifo_resize = false, 723 .index = 1, 724 }; 725 726 static struct dwc3_omap_device usb_otg_ss2_glue = { 727 .base = (void *)USB_OTG_SS2_GLUE_BASE, 728 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 729 .index = 1, 730 }; 731 732 static struct ti_usb_phy_device usb_phy2_device = { 733 .usb2_phy_power = (void *)USB2_PHY2_POWER, 734 .index = 1, 735 }; 736 737 int usb_gadget_handle_interrupts(int index) 738 { 739 u32 status; 740 741 status = dwc3_omap_uboot_interrupt_status(index); 742 if (status) 743 dwc3_uboot_handle_interrupt(index); 744 745 return 0; 746 } 747 #endif /* CONFIG_USB_DWC3 */ 748 749 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 750 int board_usb_init(int index, enum usb_init_type init) 751 { 752 enable_usb_clocks(index); 753 #ifdef CONFIG_USB_DWC3 754 switch (index) { 755 case 0: 756 if (init == USB_INIT_DEVICE) { 757 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 758 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 759 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 760 ti_usb_phy_uboot_init(&usb_phy1_device); 761 dwc3_uboot_init(&usb_otg_ss1); 762 } 763 break; 764 case 1: 765 if (init == USB_INIT_DEVICE) { 766 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 767 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 768 ti_usb_phy_uboot_init(&usb_phy2_device); 769 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 770 dwc3_uboot_init(&usb_otg_ss2); 771 } 772 break; 773 default: 774 printf("Invalid Controller Index\n"); 775 } 776 #endif 777 778 return 0; 779 } 780 781 int board_usb_cleanup(int index, enum usb_init_type init) 782 { 783 #ifdef CONFIG_USB_DWC3 784 switch (index) { 785 case 0: 786 case 1: 787 if (init == USB_INIT_DEVICE) { 788 ti_usb_phy_uboot_exit(index); 789 dwc3_uboot_exit(index); 790 dwc3_omap_uboot_exit(index); 791 } 792 break; 793 default: 794 printf("Invalid Controller Index\n"); 795 } 796 #endif 797 disable_usb_clocks(index); 798 799 return 0; 800 } 801 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 802 803 #ifdef CONFIG_DRIVER_TI_CPSW 804 805 static void cpsw_control(int enabled) 806 { 807 /* Additional controls can be added here */ 808 return; 809 } 810 811 static struct cpsw_slave_data cpsw_slaves[] = { 812 { 813 .slave_reg_ofs = 0x208, 814 .sliver_reg_ofs = 0xd80, 815 .phy_addr = 16, 816 }, 817 { 818 .slave_reg_ofs = 0x308, 819 .sliver_reg_ofs = 0xdc0, 820 .phy_addr = 1, 821 }, 822 }; 823 824 static struct cpsw_platform_data cpsw_data = { 825 .mdio_base = CPSW_MDIO_BASE, 826 .cpsw_base = CPSW_BASE, 827 .mdio_div = 0xff, 828 .channels = 8, 829 .cpdma_reg_ofs = 0x800, 830 .slaves = 1, 831 .slave_data = cpsw_slaves, 832 .ale_reg_ofs = 0xd00, 833 .ale_entries = 1024, 834 .host_port_reg_ofs = 0x108, 835 .hw_stats_reg_ofs = 0x900, 836 .bd_ram_ofs = 0x2000, 837 .mac_control = (1 << 5), 838 .control = cpsw_control, 839 .host_port_num = 0, 840 .version = CPSW_CTRL_VERSION_2, 841 }; 842 843 int board_eth_init(bd_t *bis) 844 { 845 int rv; 846 uint8_t mac_addr[6]; 847 uint32_t mac_hi, mac_lo; 848 849 /* try reading mac address from efuse */ 850 mac_lo = readl(&cdev->macid0l); 851 mac_hi = readl(&cdev->macid0h); 852 mac_addr[0] = mac_hi & 0xFF; 853 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 854 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 855 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 856 mac_addr[4] = mac_lo & 0xFF; 857 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 858 859 if (!env_get("ethaddr")) { 860 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 861 if (is_valid_ethaddr(mac_addr)) 862 eth_env_set_enetaddr("ethaddr", mac_addr); 863 } 864 865 mac_lo = readl(&cdev->macid1l); 866 mac_hi = readl(&cdev->macid1h); 867 mac_addr[0] = mac_hi & 0xFF; 868 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 869 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 870 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 871 mac_addr[4] = mac_lo & 0xFF; 872 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 873 874 if (!env_get("eth1addr")) { 875 if (is_valid_ethaddr(mac_addr)) 876 eth_env_set_enetaddr("eth1addr", mac_addr); 877 } 878 879 if (board_is_eposevm()) { 880 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 881 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 882 cpsw_slaves[0].phy_addr = 16; 883 } else if (board_is_sk()) { 884 writel(RGMII_MODE_ENABLE, &cdev->miisel); 885 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 886 cpsw_slaves[0].phy_addr = 4; 887 cpsw_slaves[1].phy_addr = 5; 888 } else if (board_is_idk()) { 889 writel(RGMII_MODE_ENABLE, &cdev->miisel); 890 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 891 cpsw_slaves[0].phy_addr = 0; 892 } else { 893 writel(RGMII_MODE_ENABLE, &cdev->miisel); 894 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 895 cpsw_slaves[0].phy_addr = 0; 896 } 897 898 rv = cpsw_register(&cpsw_data); 899 if (rv < 0) 900 printf("Error %d registering CPSW switch\n", rv); 901 902 return rv; 903 } 904 #endif 905 906 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 907 int ft_board_setup(void *blob, bd_t *bd) 908 { 909 ft_cpu_setup(blob, bd); 910 911 return 0; 912 } 913 #endif 914 915 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT) 916 int board_fit_config_name_match(const char *name) 917 { 918 bool eeprom_read = board_ti_was_eeprom_read(); 919 920 if (!strcmp(name, "am4372-generic") && !eeprom_read) 921 return 0; 922 else if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) 923 return 0; 924 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) 925 return 0; 926 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) 927 return 0; 928 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) 929 return 0; 930 else 931 return -1; 932 } 933 #endif 934 935 #ifdef CONFIG_DTB_RESELECT 936 int embedded_dtb_select(void) 937 { 938 do_board_detect(); 939 fdtdec_setup(); 940 941 return 0; 942 } 943 #endif 944 945 #ifdef CONFIG_TI_SECURE_DEVICE 946 void board_fit_image_post_process(void **p_image, size_t *p_size) 947 { 948 secure_boot_verify_image(p_image, p_size); 949 } 950 951 void board_tee_image_process(ulong tee_image, size_t tee_size) 952 { 953 secure_tee_install((u32)tee_image); 954 } 955 956 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 957 #endif 958