1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <spl.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/mux.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/emif.h> 21 #include "board.h" 22 #include <power/tps65218.h> 23 #include <miiphy.h> 24 #include <cpsw.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 29 30 /* 31 * Read header information from EEPROM into global structure. 32 */ 33 static int read_eeprom(struct am43xx_board_id *header) 34 { 35 /* Check if baseboard eeprom is available */ 36 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 37 printf("Could not probe the EEPROM at 0x%x\n", 38 CONFIG_SYS_I2C_EEPROM_ADDR); 39 return -ENODEV; 40 } 41 42 /* read the eeprom using i2c */ 43 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 44 sizeof(struct am43xx_board_id))) { 45 printf("Could not read the EEPROM\n"); 46 return -EIO; 47 } 48 49 if (header->magic != 0xEE3355AA) { 50 /* 51 * read the eeprom using i2c again, 52 * but use only a 1 byte address 53 */ 54 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 55 sizeof(struct am43xx_board_id))) { 56 printf("Could not read the EEPROM at 0x%x\n", 57 CONFIG_SYS_I2C_EEPROM_ADDR); 58 return -EIO; 59 } 60 61 if (header->magic != 0xEE3355AA) { 62 printf("Incorrect magic number (0x%x) in EEPROM\n", 63 header->magic); 64 return -EINVAL; 65 } 66 } 67 68 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); 69 am43xx_board_name[sizeof(header->name)] = 0; 70 71 return 0; 72 } 73 74 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 75 76 #define NUM_OPPS 6 77 78 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 79 { /* 19.2 MHz */ 80 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ 81 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 82 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ 83 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ 84 {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ 85 {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ 86 }, 87 { /* 24 MHz */ 88 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 89 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 90 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 91 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 92 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 93 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 94 }, 95 { /* 25 MHz */ 96 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 97 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 98 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 99 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 100 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 101 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 102 }, 103 { /* 26 MHz */ 104 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 105 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 106 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 107 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 108 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 109 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 110 }, 111 }; 112 113 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 114 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 115 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 116 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 117 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 118 }; 119 120 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 121 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 122 {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ 123 {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ 124 {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ 125 }; 126 127 const struct dpll_params epos_evm_dpll_ddr = { 128 266, 24, 1, -1, 1, -1, -1}; 129 130 const struct dpll_params gp_evm_dpll_ddr = { 131 400, 23, 1, -1, 1, -1, -1}; 132 133 const struct ctrl_ioregs ioregs_lpddr2 = { 134 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 135 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 136 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 137 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 138 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 139 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 140 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 141 .emif_sdram_config_ext = 0x1, 142 }; 143 144 const struct emif_regs emif_regs_lpddr2 = { 145 .sdram_config = 0x808012BA, 146 .ref_ctrl = 0x0000040D, 147 .sdram_tim1 = 0xEA86B411, 148 .sdram_tim2 = 0x103A094A, 149 .sdram_tim3 = 0x0F6BA37F, 150 .read_idle_ctrl = 0x00050000, 151 .zq_config = 0x50074BE4, 152 .temp_alert_config = 0x0, 153 .emif_rd_wr_lvl_rmp_win = 0x0, 154 .emif_rd_wr_lvl_rmp_ctl = 0x0, 155 .emif_rd_wr_lvl_ctl = 0x0, 156 .emif_ddr_phy_ctlr_1 = 0x0E084006, 157 .emif_rd_wr_exec_thresh = 0x00000405, 158 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 159 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 160 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 161 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 162 .emif_ddr_ext_phy_ctrl_5 = 0x00500050 163 }; 164 165 const u32 ext_phy_ctrl_const_base_lpddr2[] = { 166 0x00500050, 167 0x00350035, 168 0x00350035, 169 0x00350035, 170 0x00350035, 171 0x00350035, 172 0x00000000, 173 0x00000000, 174 0x00000000, 175 0x00000000, 176 0x00000000, 177 0x00000000, 178 0x00000000, 179 0x00000000, 180 0x00000000, 181 0x00000000, 182 0x00000000, 183 0x00000000, 184 0x40001000, 185 0x08102040 186 }; 187 188 const struct ctrl_ioregs ioregs_ddr3 = { 189 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 190 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 191 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 192 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 193 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 194 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 195 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 196 .emif_sdram_config_ext = 0x0143, 197 }; 198 199 const struct emif_regs ddr3_emif_regs_400Mhz = { 200 .sdram_config = 0x638413B2, 201 .ref_ctrl = 0x00000C30, 202 .sdram_tim1 = 0xEAAAD4DB, 203 .sdram_tim2 = 0x266B7FDA, 204 .sdram_tim3 = 0x107F8678, 205 .read_idle_ctrl = 0x00050000, 206 .zq_config = 0x50074BE4, 207 .temp_alert_config = 0x0, 208 .emif_ddr_phy_ctlr_1 = 0x0E004008, 209 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 210 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 211 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 212 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 213 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 214 .emif_rd_wr_lvl_rmp_win = 0x0, 215 .emif_rd_wr_lvl_rmp_ctl = 0x0, 216 .emif_rd_wr_lvl_ctl = 0x0, 217 .emif_rd_wr_exec_thresh = 0x00000405 218 }; 219 220 const u32 ext_phy_ctrl_const_base_ddr3[] = { 221 0x00400040, 222 0x00350035, 223 0x00350035, 224 0x00350035, 225 0x00350035, 226 0x00350035, 227 0x00000000, 228 0x00000000, 229 0x00000000, 230 0x00000000, 231 0x00000000, 232 0x00340034, 233 0x00340034, 234 0x00340034, 235 0x00340034, 236 0x00340034, 237 0x0, 238 0x0, 239 0x40000000, 240 0x08102040 241 }; 242 243 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 244 { 245 if (board_is_eposevm()) { 246 *regs = ext_phy_ctrl_const_base_lpddr2; 247 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 248 } else if (board_is_gpevm()) { 249 *regs = ext_phy_ctrl_const_base_ddr3; 250 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); 251 } 252 253 return; 254 } 255 256 const struct dpll_params *get_dpll_ddr_params(void) 257 { 258 if (board_is_eposevm()) 259 return &epos_evm_dpll_ddr; 260 else if (board_is_gpevm()) 261 return &gp_evm_dpll_ddr; 262 263 puts(" Board not supported\n"); 264 return NULL; 265 } 266 267 /* 268 * get_sys_clk_index : returns the index of the sys_clk read from 269 * ctrl status register. This value is either 270 * read from efuse or sysboot pins. 271 */ 272 static u32 get_sys_clk_index(void) 273 { 274 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 275 u32 ind = readl(&ctrl->statusreg), src; 276 277 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; 278 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ 279 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> 280 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); 281 else /* Value read from SYS BOOT pins */ 282 return ((ind & CTRL_SYSBOOT_15_14_MASK) >> 283 CTRL_SYSBOOT_15_14_SHIFT); 284 } 285 286 /* 287 * get_opp_offset: 288 * Returns the index for safest OPP of the device to boot. 289 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 290 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 291 * This data is read from dev_attribute register which is e-fused. 292 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 293 * OPP available. Lowest OPP starts with min_off. So returning the 294 * bit with rightmost '0'. 295 */ 296 static int get_opp_offset(int max_off, int min_off) 297 { 298 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 299 int opp, offset, i; 300 301 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 302 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 303 304 for (i = max_off; i >= min_off; i--) { 305 offset = opp & (1 << i); 306 if (!offset) 307 return i; 308 } 309 310 return min_off; 311 } 312 313 const struct dpll_params *get_dpll_mpu_params(void) 314 { 315 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 316 u32 ind = get_sys_clk_index(); 317 318 return &dpll_mpu[ind][opp]; 319 } 320 321 const struct dpll_params *get_dpll_core_params(void) 322 { 323 int ind = get_sys_clk_index(); 324 325 return &dpll_core[ind]; 326 } 327 328 const struct dpll_params *get_dpll_per_params(void) 329 { 330 int ind = get_sys_clk_index(); 331 332 return &dpll_per[ind]; 333 } 334 335 void scale_vcores(void) 336 { 337 const struct dpll_params *mpu_params; 338 int mpu_vdd; 339 struct am43xx_board_id header; 340 341 enable_i2c0_pin_mux(); 342 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 343 if (read_eeprom(&header) < 0) 344 puts("Could not get board ID.\n"); 345 346 /* Get the frequency */ 347 mpu_params = get_dpll_mpu_params(); 348 349 if (i2c_probe(TPS65218_CHIP_PM)) 350 return; 351 352 if (mpu_params->m == 1000) { 353 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 354 } else if (mpu_params->m == 600) { 355 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 356 } else { 357 puts("Unknown MPU clock, not scaling\n"); 358 return; 359 } 360 361 /* Set DCDC1 (CORE) voltage to 1.1V */ 362 if (tps65218_voltage_update(TPS65218_DCDC1, 363 TPS65218_DCDC_VOLT_SEL_1100MV)) { 364 puts("tps65218_voltage_update failure\n"); 365 return; 366 } 367 368 /* Set DCDC2 (MPU) voltage */ 369 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 370 puts("tps65218_voltage_update failure\n"); 371 return; 372 } 373 } 374 375 void set_uart_mux_conf(void) 376 { 377 enable_uart0_pin_mux(); 378 } 379 380 void set_mux_conf_regs(void) 381 { 382 enable_board_pin_mux(); 383 } 384 385 static void enable_vtt_regulator(void) 386 { 387 u32 temp; 388 389 /* enable module */ 390 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 391 392 /* enable output for GPIO5_7 */ 393 writel(GPIO_SETDATAOUT(7), 394 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 395 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 396 temp = temp & ~(GPIO_OE_ENABLE(7)); 397 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 398 } 399 400 void sdram_init(void) 401 { 402 /* 403 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 404 * GP EMV has 1GB DDR3 connected to EMIF 405 * along with VTT regulator. 406 */ 407 if (board_is_eposevm()) { 408 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 409 } else if (board_is_gpevm()) { 410 enable_vtt_regulator(); 411 config_ddr(0, &ioregs_ddr3, NULL, NULL, 412 &ddr3_emif_regs_400Mhz, 0); 413 } 414 } 415 #endif 416 417 int board_init(void) 418 { 419 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 420 421 return 0; 422 } 423 424 #ifdef CONFIG_BOARD_LATE_INIT 425 int board_late_init(void) 426 { 427 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 428 char safe_string[HDR_NAME_LEN + 1]; 429 struct am43xx_board_id header; 430 431 if (read_eeprom(&header) < 0) 432 puts("Could not get board ID.\n"); 433 434 /* Now set variables based on the header. */ 435 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 436 safe_string[sizeof(header.name)] = 0; 437 setenv("board_name", safe_string); 438 439 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 440 safe_string[sizeof(header.version)] = 0; 441 setenv("board_rev", safe_string); 442 #endif 443 return 0; 444 } 445 #endif 446 447 #ifdef CONFIG_DRIVER_TI_CPSW 448 449 static void cpsw_control(int enabled) 450 { 451 /* Additional controls can be added here */ 452 return; 453 } 454 455 static struct cpsw_slave_data cpsw_slaves[] = { 456 { 457 .slave_reg_ofs = 0x208, 458 .sliver_reg_ofs = 0xd80, 459 .phy_addr = 16, 460 }, 461 { 462 .slave_reg_ofs = 0x308, 463 .sliver_reg_ofs = 0xdc0, 464 .phy_addr = 1, 465 }, 466 }; 467 468 static struct cpsw_platform_data cpsw_data = { 469 .mdio_base = CPSW_MDIO_BASE, 470 .cpsw_base = CPSW_BASE, 471 .mdio_div = 0xff, 472 .channels = 8, 473 .cpdma_reg_ofs = 0x800, 474 .slaves = 1, 475 .slave_data = cpsw_slaves, 476 .ale_reg_ofs = 0xd00, 477 .ale_entries = 1024, 478 .host_port_reg_ofs = 0x108, 479 .hw_stats_reg_ofs = 0x900, 480 .bd_ram_ofs = 0x2000, 481 .mac_control = (1 << 5), 482 .control = cpsw_control, 483 .host_port_num = 0, 484 .version = CPSW_CTRL_VERSION_2, 485 }; 486 487 int board_eth_init(bd_t *bis) 488 { 489 int rv; 490 uint8_t mac_addr[6]; 491 uint32_t mac_hi, mac_lo; 492 493 /* try reading mac address from efuse */ 494 mac_lo = readl(&cdev->macid0l); 495 mac_hi = readl(&cdev->macid0h); 496 mac_addr[0] = mac_hi & 0xFF; 497 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 498 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 499 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 500 mac_addr[4] = mac_lo & 0xFF; 501 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 502 503 if (!getenv("ethaddr")) { 504 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 505 if (is_valid_ether_addr(mac_addr)) 506 eth_setenv_enetaddr("ethaddr", mac_addr); 507 } 508 509 mac_lo = readl(&cdev->macid1l); 510 mac_hi = readl(&cdev->macid1h); 511 mac_addr[0] = mac_hi & 0xFF; 512 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 513 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 514 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 515 mac_addr[4] = mac_lo & 0xFF; 516 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 517 518 if (!getenv("eth1addr")) { 519 if (is_valid_ether_addr(mac_addr)) 520 eth_setenv_enetaddr("eth1addr", mac_addr); 521 } 522 523 if (board_is_eposevm()) { 524 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 525 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 526 cpsw_slaves[0].phy_addr = 16; 527 } else { 528 writel(RGMII_MODE_ENABLE, &cdev->miisel); 529 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 530 cpsw_slaves[0].phy_addr = 0; 531 } 532 533 rv = cpsw_register(&cpsw_data); 534 if (rv < 0) 535 printf("Error %d registering CPSW switch\n", rv); 536 537 return rv; 538 } 539 #endif 540