1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <spl.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/mux.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/emif.h> 21 #include "board.h" 22 #include <miiphy.h> 23 #include <cpsw.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 28 29 /* 30 * Read header information from EEPROM into global structure. 31 */ 32 static int read_eeprom(struct am43xx_board_id *header) 33 { 34 /* Check if baseboard eeprom is available */ 35 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 36 printf("Could not probe the EEPROM at 0x%x\n", 37 CONFIG_SYS_I2C_EEPROM_ADDR); 38 return -ENODEV; 39 } 40 41 /* read the eeprom using i2c */ 42 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 43 sizeof(struct am43xx_board_id))) { 44 printf("Could not read the EEPROM\n"); 45 return -EIO; 46 } 47 48 if (header->magic != 0xEE3355AA) { 49 /* 50 * read the eeprom using i2c again, 51 * but use only a 1 byte address 52 */ 53 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 54 sizeof(struct am43xx_board_id))) { 55 printf("Could not read the EEPROM at 0x%x\n", 56 CONFIG_SYS_I2C_EEPROM_ADDR); 57 return -EIO; 58 } 59 60 if (header->magic != 0xEE3355AA) { 61 printf("Incorrect magic number (0x%x) in EEPROM\n", 62 header->magic); 63 return -EINVAL; 64 } 65 } 66 67 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); 68 am43xx_board_name[sizeof(header->name)] = 0; 69 70 return 0; 71 } 72 73 #ifdef CONFIG_SPL_BUILD 74 75 #define NUM_OPPS 6 76 77 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 78 { /* 19.2 MHz */ 79 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ 80 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 81 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ 82 {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ 83 {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ 84 {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ 85 }, 86 { /* 24 MHz */ 87 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 88 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 89 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 90 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 91 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 92 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 93 }, 94 { /* 25 MHz */ 95 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 96 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 97 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 98 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 99 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 100 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 101 }, 102 { /* 26 MHz */ 103 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 104 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 105 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 106 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 107 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 108 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 109 }, 110 }; 111 112 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 113 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 114 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 115 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 116 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 117 }; 118 119 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 120 {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 121 {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ 122 {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ 123 {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ 124 }; 125 126 const struct dpll_params epos_evm_dpll_ddr = { 127 266, 24, 1, -1, 1, -1, -1}; 128 129 const struct dpll_params gp_evm_dpll_ddr = { 130 400, 23, 1, -1, 1, -1, -1}; 131 132 const struct ctrl_ioregs ioregs_lpddr2 = { 133 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 134 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 135 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 136 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 137 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 138 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 139 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 140 .emif_sdram_config_ext = 0x1, 141 }; 142 143 const struct emif_regs emif_regs_lpddr2 = { 144 .sdram_config = 0x808012BA, 145 .ref_ctrl = 0x0000040D, 146 .sdram_tim1 = 0xEA86B411, 147 .sdram_tim2 = 0x103A094A, 148 .sdram_tim3 = 0x0F6BA37F, 149 .read_idle_ctrl = 0x00050000, 150 .zq_config = 0x50074BE4, 151 .temp_alert_config = 0x0, 152 .emif_rd_wr_lvl_rmp_win = 0x0, 153 .emif_rd_wr_lvl_rmp_ctl = 0x0, 154 .emif_rd_wr_lvl_ctl = 0x0, 155 .emif_ddr_phy_ctlr_1 = 0x0E084006, 156 .emif_rd_wr_exec_thresh = 0x00000405, 157 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 158 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 159 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 160 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 161 .emif_ddr_ext_phy_ctrl_5 = 0x00500050 162 }; 163 164 const u32 ext_phy_ctrl_const_base_lpddr2[] = { 165 0x00500050, 166 0x00350035, 167 0x00350035, 168 0x00350035, 169 0x00350035, 170 0x00350035, 171 0x00000000, 172 0x00000000, 173 0x00000000, 174 0x00000000, 175 0x00000000, 176 0x00000000, 177 0x00000000, 178 0x00000000, 179 0x00000000, 180 0x00000000, 181 0x00000000, 182 0x00000000, 183 0x40001000, 184 0x08102040 185 }; 186 187 const struct ctrl_ioregs ioregs_ddr3 = { 188 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 189 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 190 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 191 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 192 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 193 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 194 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 195 .emif_sdram_config_ext = 0x0143, 196 }; 197 198 const struct emif_regs ddr3_emif_regs_400Mhz = { 199 .sdram_config = 0x638413B2, 200 .ref_ctrl = 0x00000C30, 201 .sdram_tim1 = 0xEAAAD4DB, 202 .sdram_tim2 = 0x266B7FDA, 203 .sdram_tim3 = 0x107F8678, 204 .read_idle_ctrl = 0x00050000, 205 .zq_config = 0x50074BE4, 206 .temp_alert_config = 0x0, 207 .emif_ddr_phy_ctlr_1 = 0x0E004008, 208 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 209 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 210 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 211 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 212 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 213 .emif_rd_wr_lvl_rmp_win = 0x0, 214 .emif_rd_wr_lvl_rmp_ctl = 0x0, 215 .emif_rd_wr_lvl_ctl = 0x0, 216 .emif_rd_wr_exec_thresh = 0x00000405 217 }; 218 219 const u32 ext_phy_ctrl_const_base_ddr3[] = { 220 0x00400040, 221 0x00350035, 222 0x00350035, 223 0x00350035, 224 0x00350035, 225 0x00350035, 226 0x00000000, 227 0x00000000, 228 0x00000000, 229 0x00000000, 230 0x00000000, 231 0x00340034, 232 0x00340034, 233 0x00340034, 234 0x00340034, 235 0x00340034, 236 0x0, 237 0x0, 238 0x40000000, 239 0x08102040 240 }; 241 242 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 243 { 244 if (board_is_eposevm()) { 245 *regs = ext_phy_ctrl_const_base_lpddr2; 246 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 247 } else if (board_is_gpevm()) { 248 *regs = ext_phy_ctrl_const_base_ddr3; 249 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); 250 } 251 252 return; 253 } 254 255 const struct dpll_params *get_dpll_ddr_params(void) 256 { 257 struct am43xx_board_id header; 258 259 enable_i2c0_pin_mux(); 260 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 261 if (read_eeprom(&header) < 0) 262 puts("Could not get board ID.\n"); 263 264 if (board_is_eposevm()) 265 return &epos_evm_dpll_ddr; 266 else if (board_is_gpevm()) 267 return &gp_evm_dpll_ddr; 268 269 puts(" Board not supported\n"); 270 return NULL; 271 } 272 273 /* 274 * get_sys_clk_index : returns the index of the sys_clk read from 275 * ctrl status register. This value is either 276 * read from efuse or sysboot pins. 277 */ 278 static u32 get_sys_clk_index(void) 279 { 280 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 281 u32 ind = readl(&ctrl->statusreg), src; 282 283 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; 284 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ 285 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> 286 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); 287 else /* Value read from SYS BOOT pins */ 288 return ((ind & CTRL_SYSBOOT_15_14_MASK) >> 289 CTRL_SYSBOOT_15_14_SHIFT); 290 } 291 292 /* 293 * get_opp_offset: 294 * Returns the index for safest OPP of the device to boot. 295 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 296 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 297 * This data is read from dev_attribute register which is e-fused. 298 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 299 * OPP available. Lowest OPP starts with min_off. So returning the 300 * bit with rightmost '0'. 301 */ 302 static int get_opp_offset(int max_off, int min_off) 303 { 304 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 305 int opp = readl(&ctrl->dev_attr), offset, i; 306 307 for (i = max_off; i >= min_off; i--) { 308 offset = opp & (1 << i); 309 if (!offset) 310 return i; 311 } 312 313 return min_off; 314 } 315 316 const struct dpll_params *get_dpll_mpu_params(void) 317 { 318 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 319 u32 ind = get_sys_clk_index(); 320 321 return &dpll_mpu[ind][opp]; 322 } 323 324 const struct dpll_params *get_dpll_core_params(void) 325 { 326 int ind = get_sys_clk_index(); 327 328 return &dpll_core[ind]; 329 } 330 331 const struct dpll_params *get_dpll_per_params(void) 332 { 333 int ind = get_sys_clk_index(); 334 335 return &dpll_per[ind]; 336 } 337 338 void set_uart_mux_conf(void) 339 { 340 enable_uart0_pin_mux(); 341 } 342 343 void set_mux_conf_regs(void) 344 { 345 enable_board_pin_mux(); 346 } 347 348 static void enable_vtt_regulator(void) 349 { 350 u32 temp; 351 352 /* enable module */ 353 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 354 355 /* enable output for GPIO5_7 */ 356 writel(GPIO_SETDATAOUT(7), 357 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 358 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 359 temp = temp & ~(GPIO_OE_ENABLE(7)); 360 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 361 } 362 363 void sdram_init(void) 364 { 365 /* 366 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 367 * GP EMV has 1GB DDR3 connected to EMIF 368 * along with VTT regulator. 369 */ 370 if (board_is_eposevm()) { 371 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 372 } else if (board_is_gpevm()) { 373 enable_vtt_regulator(); 374 config_ddr(0, &ioregs_ddr3, NULL, NULL, 375 &ddr3_emif_regs_400Mhz, 0); 376 } 377 } 378 #endif 379 380 int board_init(void) 381 { 382 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 383 384 return 0; 385 } 386 387 #ifdef CONFIG_BOARD_LATE_INIT 388 int board_late_init(void) 389 { 390 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 391 char safe_string[HDR_NAME_LEN + 1]; 392 struct am43xx_board_id header; 393 394 if (read_eeprom(&header) < 0) 395 puts("Could not get board ID.\n"); 396 397 /* Now set variables based on the header. */ 398 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 399 safe_string[sizeof(header.name)] = 0; 400 setenv("board_name", safe_string); 401 402 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 403 safe_string[sizeof(header.version)] = 0; 404 setenv("board_rev", safe_string); 405 #endif 406 return 0; 407 } 408 #endif 409 410 #ifdef CONFIG_DRIVER_TI_CPSW 411 412 static void cpsw_control(int enabled) 413 { 414 /* Additional controls can be added here */ 415 return; 416 } 417 418 static struct cpsw_slave_data cpsw_slaves[] = { 419 { 420 .slave_reg_ofs = 0x208, 421 .sliver_reg_ofs = 0xd80, 422 .phy_addr = 16, 423 }, 424 { 425 .slave_reg_ofs = 0x308, 426 .sliver_reg_ofs = 0xdc0, 427 .phy_addr = 1, 428 }, 429 }; 430 431 static struct cpsw_platform_data cpsw_data = { 432 .mdio_base = CPSW_MDIO_BASE, 433 .cpsw_base = CPSW_BASE, 434 .mdio_div = 0xff, 435 .channels = 8, 436 .cpdma_reg_ofs = 0x800, 437 .slaves = 1, 438 .slave_data = cpsw_slaves, 439 .ale_reg_ofs = 0xd00, 440 .ale_entries = 1024, 441 .host_port_reg_ofs = 0x108, 442 .hw_stats_reg_ofs = 0x900, 443 .bd_ram_ofs = 0x2000, 444 .mac_control = (1 << 5), 445 .control = cpsw_control, 446 .host_port_num = 0, 447 .version = CPSW_CTRL_VERSION_2, 448 }; 449 450 int board_eth_init(bd_t *bis) 451 { 452 int rv; 453 uint8_t mac_addr[6]; 454 uint32_t mac_hi, mac_lo; 455 456 /* try reading mac address from efuse */ 457 mac_lo = readl(&cdev->macid0l); 458 mac_hi = readl(&cdev->macid0h); 459 mac_addr[0] = mac_hi & 0xFF; 460 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 461 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 462 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 463 mac_addr[4] = mac_lo & 0xFF; 464 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 465 466 if (!getenv("ethaddr")) { 467 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 468 if (is_valid_ether_addr(mac_addr)) 469 eth_setenv_enetaddr("ethaddr", mac_addr); 470 } 471 472 mac_lo = readl(&cdev->macid1l); 473 mac_hi = readl(&cdev->macid1h); 474 mac_addr[0] = mac_hi & 0xFF; 475 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 476 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 477 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 478 mac_addr[4] = mac_lo & 0xFF; 479 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 480 481 if (!getenv("eth1addr")) { 482 if (is_valid_ether_addr(mac_addr)) 483 eth_setenv_enetaddr("eth1addr", mac_addr); 484 } 485 486 if (board_is_eposevm()) { 487 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 488 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 489 cpsw_slaves[0].phy_addr = 16; 490 } else { 491 writel(RGMII_MODE_ENABLE, &cdev->miisel); 492 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 493 cpsw_slaves[0].phy_addr = 0; 494 } 495 496 rv = cpsw_register(&cpsw_data); 497 if (rv < 0) 498 printf("Error %d registering CPSW switch\n", rv); 499 500 return rv; 501 } 502 #endif 503