xref: /openbmc/u-boot/board/ti/am43xx/board.c (revision 8df37888)
1 /*
2  * board.c
3  *
4  * Board functions for TI AM43XX based boards
5  *
6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #include <common.h>
12 #include <i2c.h>
13 #include <linux/errno.h>
14 #include <spl.h>
15 #include <usb.h>
16 #include <asm/omap_sec_common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mux.h>
20 #include <asm/arch/ddr_defs.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/emif.h>
23 #include "../common/board_detect.h"
24 #include "board.h"
25 #include <power/pmic.h>
26 #include <power/tps65218.h>
27 #include <power/tps62362.h>
28 #include <miiphy.h>
29 #include <cpsw.h>
30 #include <linux/usb/gadget.h>
31 #include <dwc3-uboot.h>
32 #include <dwc3-omap-uboot.h>
33 #include <ti-usb-phy-uboot.h>
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
38 
39 /*
40  * Read header information from EEPROM into global structure.
41  */
42 #ifdef CONFIG_TI_I2C_BOARD_DETECT
43 void do_board_detect(void)
44 {
45 	if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
46 				 CONFIG_EEPROM_CHIP_ADDRESS))
47 		printf("ti_i2c_eeprom_init failed\n");
48 }
49 #endif
50 
51 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
52 
53 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
54 	{	/* 19.2 MHz */
55 		{125, 3, 2, -1, -1, -1, -1},	/* OPP 50 */
56 		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
57 		{125, 3, 1, -1, -1, -1, -1},	/* OPP 100 */
58 		{150, 3, 1, -1, -1, -1, -1},	/* OPP 120 */
59 		{125, 2, 1, -1, -1, -1, -1},	/* OPP TB */
60 		{625, 11, 1, -1, -1, -1, -1}	/* OPP NT */
61 	},
62 	{	/* 24 MHz */
63 		{300, 23, 1, -1, -1, -1, -1},	/* OPP 50 */
64 		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
65 		{600, 23, 1, -1, -1, -1, -1},	/* OPP 100 */
66 		{720, 23, 1, -1, -1, -1, -1},	/* OPP 120 */
67 		{800, 23, 1, -1, -1, -1, -1},	/* OPP TB */
68 		{1000, 23, 1, -1, -1, -1, -1}	/* OPP NT */
69 	},
70 	{	/* 25 MHz */
71 		{300, 24, 1, -1, -1, -1, -1},	/* OPP 50 */
72 		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
73 		{600, 24, 1, -1, -1, -1, -1},	/* OPP 100 */
74 		{720, 24, 1, -1, -1, -1, -1},	/* OPP 120 */
75 		{800, 24, 1, -1, -1, -1, -1},	/* OPP TB */
76 		{1000, 24, 1, -1, -1, -1, -1}	/* OPP NT */
77 	},
78 	{	/* 26 MHz */
79 		{300, 25, 1, -1, -1, -1, -1},	/* OPP 50 */
80 		{-1, -1, -1, -1, -1, -1, -1},	/* OPP RESERVED	*/
81 		{600, 25, 1, -1, -1, -1, -1},	/* OPP 100 */
82 		{720, 25, 1, -1, -1, -1, -1},	/* OPP 120 */
83 		{800, 25, 1, -1, -1, -1, -1},	/* OPP TB */
84 		{1000, 25, 1, -1, -1, -1, -1}	/* OPP NT */
85 	},
86 };
87 
88 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
89 		{625, 11, -1, -1, 10, 8, 4},	/* 19.2 MHz */
90 		{1000, 23, -1, -1, 10, 8, 4},	/* 24 MHz */
91 		{1000, 24, -1, -1, 10, 8, 4},	/* 25 MHz */
92 		{1000, 25, -1, -1, 10, 8, 4}	/* 26 MHz */
93 };
94 
95 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
96 		{400, 7, 5, -1, -1, -1, -1},	/* 19.2 MHz */
97 		{400, 9, 5, -1, -1, -1, -1},	/* 24 MHz */
98 		{384, 9, 5, -1, -1, -1, -1},	/* 25 MHz */
99 		{480, 12, 5, -1, -1, -1, -1}	/* 26 MHz */
100 };
101 
102 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
103 		{665, 47, 1, -1, 4, -1, -1}, /*19.2*/
104 		{133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
105 		{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
106 		{133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
107 };
108 
109 const struct dpll_params gp_evm_dpll_ddr = {
110 		50, 2, 1, -1, 2, -1, -1};
111 
112 static const struct dpll_params idk_dpll_ddr = {
113 	400, 23, 1, -1, 2, -1, -1
114 };
115 
116 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
117 	0x00500050,
118 	0x00350035,
119 	0x00350035,
120 	0x00350035,
121 	0x00350035,
122 	0x00350035,
123 	0x00000000,
124 	0x00000000,
125 	0x00000000,
126 	0x00000000,
127 	0x00000000,
128 	0x00000000,
129 	0x00000000,
130 	0x00000000,
131 	0x00000000,
132 	0x00000000,
133 	0x00000000,
134 	0x00000000,
135 	0x40001000,
136 	0x08102040
137 };
138 
139 const struct ctrl_ioregs ioregs_lpddr2 = {
140 	.cm0ioctl		= LPDDR2_ADDRCTRL_IOCTRL_VALUE,
141 	.cm1ioctl		= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
142 	.cm2ioctl		= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
143 	.dt0ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
144 	.dt1ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
145 	.dt2ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
146 	.dt3ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
147 	.emif_sdram_config_ext	= 0x1,
148 };
149 
150 const struct emif_regs emif_regs_lpddr2 = {
151 	.sdram_config			= 0x808012BA,
152 	.ref_ctrl			= 0x0000040D,
153 	.sdram_tim1			= 0xEA86B411,
154 	.sdram_tim2			= 0x103A094A,
155 	.sdram_tim3			= 0x0F6BA37F,
156 	.read_idle_ctrl			= 0x00050000,
157 	.zq_config			= 0x50074BE4,
158 	.temp_alert_config		= 0x0,
159 	.emif_rd_wr_lvl_rmp_win		= 0x0,
160 	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
161 	.emif_rd_wr_lvl_ctl		= 0x0,
162 	.emif_ddr_phy_ctlr_1		= 0x0E284006,
163 	.emif_rd_wr_exec_thresh		= 0x80000405,
164 	.emif_ddr_ext_phy_ctrl_1	= 0x04010040,
165 	.emif_ddr_ext_phy_ctrl_2	= 0x00500050,
166 	.emif_ddr_ext_phy_ctrl_3	= 0x00500050,
167 	.emif_ddr_ext_phy_ctrl_4	= 0x00500050,
168 	.emif_ddr_ext_phy_ctrl_5	= 0x00500050,
169 	.emif_prio_class_serv_map	= 0x80000001,
170 	.emif_connect_id_serv_1_map	= 0x80000094,
171 	.emif_connect_id_serv_2_map	= 0x00000000,
172 	.emif_cos_config			= 0x000FFFFF
173 };
174 
175 const struct ctrl_ioregs ioregs_ddr3 = {
176 	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
177 	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
178 	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
179 	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
180 	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
181 	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
182 	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
183 	.emif_sdram_config_ext	= 0xc163,
184 };
185 
186 const struct emif_regs ddr3_emif_regs_400Mhz = {
187 	.sdram_config			= 0x638413B2,
188 	.ref_ctrl			= 0x00000C30,
189 	.sdram_tim1			= 0xEAAAD4DB,
190 	.sdram_tim2			= 0x266B7FDA,
191 	.sdram_tim3			= 0x107F8678,
192 	.read_idle_ctrl			= 0x00050000,
193 	.zq_config			= 0x50074BE4,
194 	.temp_alert_config		= 0x0,
195 	.emif_ddr_phy_ctlr_1		= 0x0E004008,
196 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
197 	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
198 	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
199 	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
200 	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
201 	.emif_rd_wr_lvl_rmp_win		= 0x0,
202 	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
203 	.emif_rd_wr_lvl_ctl		= 0x0,
204 	.emif_rd_wr_exec_thresh		= 0x80000405,
205 	.emif_prio_class_serv_map	= 0x80000001,
206 	.emif_connect_id_serv_1_map	= 0x80000094,
207 	.emif_connect_id_serv_2_map	= 0x00000000,
208 	.emif_cos_config		= 0x000FFFFF
209 };
210 
211 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
212 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
213 	.sdram_config			= 0x638413B2,
214 	.ref_ctrl			= 0x00000C30,
215 	.sdram_tim1			= 0xEAAAD4DB,
216 	.sdram_tim2			= 0x266B7FDA,
217 	.sdram_tim3			= 0x107F8678,
218 	.read_idle_ctrl			= 0x00050000,
219 	.zq_config			= 0x50074BE4,
220 	.temp_alert_config		= 0x0,
221 	.emif_ddr_phy_ctlr_1		= 0x0E004008,
222 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
223 	.emif_ddr_ext_phy_ctrl_2	= 0x00000065,
224 	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
225 	.emif_ddr_ext_phy_ctrl_4	= 0x000000B5,
226 	.emif_ddr_ext_phy_ctrl_5	= 0x000000E5,
227 	.emif_rd_wr_exec_thresh		= 0x80000405,
228 	.emif_prio_class_serv_map	= 0x80000001,
229 	.emif_connect_id_serv_1_map	= 0x80000094,
230 	.emif_connect_id_serv_2_map	= 0x00000000,
231 	.emif_cos_config		= 0x000FFFFF
232 };
233 
234 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
235 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
236 	.sdram_config			= 0x638413B2,
237 	.ref_ctrl			= 0x00000C30,
238 	.sdram_tim1			= 0xEAAAD4DB,
239 	.sdram_tim2			= 0x266B7FDA,
240 	.sdram_tim3			= 0x107F8678,
241 	.read_idle_ctrl			= 0x00050000,
242 	.zq_config			= 0x50074BE4,
243 	.temp_alert_config		= 0x0,
244 	.emif_ddr_phy_ctlr_1		= 0x0E004008,
245 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
246 	.emif_ddr_ext_phy_ctrl_2	= 0x00000066,
247 	.emif_ddr_ext_phy_ctrl_3	= 0x00000091,
248 	.emif_ddr_ext_phy_ctrl_4	= 0x000000B9,
249 	.emif_ddr_ext_phy_ctrl_5	= 0x000000E6,
250 	.emif_rd_wr_exec_thresh		= 0x80000405,
251 	.emif_prio_class_serv_map	= 0x80000001,
252 	.emif_connect_id_serv_1_map	= 0x80000094,
253 	.emif_connect_id_serv_2_map	= 0x00000000,
254 	.emif_cos_config		= 0x000FFFFF
255 };
256 
257 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
258 	.sdram_config			= 0x638413b2,
259 	.sdram_config2			= 0x00000000,
260 	.ref_ctrl			= 0x00000c30,
261 	.sdram_tim1			= 0xeaaad4db,
262 	.sdram_tim2			= 0x266b7fda,
263 	.sdram_tim3			= 0x107f8678,
264 	.read_idle_ctrl			= 0x00050000,
265 	.zq_config			= 0x50074be4,
266 	.temp_alert_config		= 0x0,
267 	.emif_ddr_phy_ctlr_1		= 0x0e084008,
268 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
269 	.emif_ddr_ext_phy_ctrl_2	= 0x89,
270 	.emif_ddr_ext_phy_ctrl_3	= 0x90,
271 	.emif_ddr_ext_phy_ctrl_4	= 0x8e,
272 	.emif_ddr_ext_phy_ctrl_5	= 0x8d,
273 	.emif_rd_wr_lvl_rmp_win		= 0x0,
274 	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
275 	.emif_rd_wr_lvl_ctl		= 0x00000000,
276 	.emif_rd_wr_exec_thresh		= 0x80000000,
277 	.emif_prio_class_serv_map	= 0x80000001,
278 	.emif_connect_id_serv_1_map	= 0x80000094,
279 	.emif_connect_id_serv_2_map	= 0x00000000,
280 	.emif_cos_config		= 0x000FFFFF
281 };
282 
283 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
284 	.sdram_config			= 0x61a11b32,
285 	.sdram_config2			= 0x00000000,
286 	.ref_ctrl			= 0x00000c30,
287 	.sdram_tim1			= 0xeaaad4db,
288 	.sdram_tim2			= 0x266b7fda,
289 	.sdram_tim3			= 0x107f8678,
290 	.read_idle_ctrl			= 0x00050000,
291 	.zq_config			= 0x50074be4,
292 	.temp_alert_config		= 0x00000000,
293 	.emif_ddr_phy_ctlr_1		= 0x00008009,
294 	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
295 	.emif_ddr_ext_phy_ctrl_2	= 0x00000040,
296 	.emif_ddr_ext_phy_ctrl_3	= 0x0000003e,
297 	.emif_ddr_ext_phy_ctrl_4	= 0x00000051,
298 	.emif_ddr_ext_phy_ctrl_5	= 0x00000051,
299 	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
300 	.emif_rd_wr_lvl_rmp_ctl		= 0x00000000,
301 	.emif_rd_wr_lvl_ctl		= 0x00000000,
302 	.emif_rd_wr_exec_thresh		= 0x00000405,
303 	.emif_prio_class_serv_map	= 0x00000000,
304 	.emif_connect_id_serv_1_map	= 0x00000000,
305 	.emif_connect_id_serv_2_map	= 0x00000000,
306 	.emif_cos_config		= 0x00ffffff
307 };
308 
309 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
310 {
311 	if (board_is_eposevm()) {
312 		*regs = ext_phy_ctrl_const_base_lpddr2;
313 		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
314 	}
315 
316 	return;
317 }
318 
319 const struct dpll_params *get_dpll_ddr_params(void)
320 {
321 	int ind = get_sys_clk_index();
322 
323 	if (board_is_eposevm())
324 		return &epos_evm_dpll_ddr[ind];
325 	else if (board_is_evm() || board_is_sk())
326 		return &gp_evm_dpll_ddr;
327 	else if (board_is_idk())
328 		return &idk_dpll_ddr;
329 
330 	printf(" Board '%s' not supported\n", board_ti_get_name());
331 	return NULL;
332 }
333 
334 
335 /*
336  * get_opp_offset:
337  * Returns the index for safest OPP of the device to boot.
338  * max_off:	Index of the MAX OPP in DEV ATTRIBUTE register.
339  * min_off:	Index of the MIN OPP in DEV ATTRIBUTE register.
340  * This data is read from dev_attribute register which is e-fused.
341  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
342  * OPP available. Lowest OPP starts with min_off. So returning the
343  * bit with rightmost '0'.
344  */
345 static int get_opp_offset(int max_off, int min_off)
346 {
347 	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
348 	int opp, offset, i;
349 
350 	/* Bits 0:11 are defined to be the MPU_MAX_FREQ */
351 	opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
352 
353 	for (i = max_off; i >= min_off; i--) {
354 		offset = opp & (1 << i);
355 		if (!offset)
356 			return i;
357 	}
358 
359 	return min_off;
360 }
361 
362 const struct dpll_params *get_dpll_mpu_params(void)
363 {
364 	int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
365 	u32 ind = get_sys_clk_index();
366 
367 	return &dpll_mpu[ind][opp];
368 }
369 
370 const struct dpll_params *get_dpll_core_params(void)
371 {
372 	int ind = get_sys_clk_index();
373 
374 	return &dpll_core[ind];
375 }
376 
377 const struct dpll_params *get_dpll_per_params(void)
378 {
379 	int ind = get_sys_clk_index();
380 
381 	return &dpll_per[ind];
382 }
383 
384 void scale_vcores_generic(u32 m)
385 {
386 	int mpu_vdd;
387 
388 	if (i2c_probe(TPS65218_CHIP_PM))
389 		return;
390 
391 	switch (m) {
392 	case 1000:
393 		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
394 		break;
395 	case 800:
396 		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
397 		break;
398 	case 720:
399 		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
400 		break;
401 	case 600:
402 		mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
403 		break;
404 	case 300:
405 		mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
406 		break;
407 	default:
408 		puts("Unknown MPU clock, not scaling\n");
409 		return;
410 	}
411 
412 	/* Set DCDC1 (CORE) voltage to 1.1V */
413 	if (tps65218_voltage_update(TPS65218_DCDC1,
414 				    TPS65218_DCDC_VOLT_SEL_1100MV)) {
415 		printf("%s failure\n", __func__);
416 		return;
417 	}
418 
419 	/* Set DCDC2 (MPU) voltage */
420 	if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
421 		printf("%s failure\n", __func__);
422 		return;
423 	}
424 }
425 
426 void scale_vcores_idk(u32 m)
427 {
428 	int mpu_vdd;
429 
430 	if (i2c_probe(TPS62362_I2C_ADDR))
431 		return;
432 
433 	switch (m) {
434 	case 1000:
435 		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
436 		break;
437 	case 800:
438 		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
439 		break;
440 	case 720:
441 		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
442 		break;
443 	case 600:
444 		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
445 		break;
446 	case 300:
447 		mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
448 		break;
449 	default:
450 		puts("Unknown MPU clock, not scaling\n");
451 		return;
452 	}
453 
454 	/* Set VDD_MPU voltage */
455 	if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
456 		printf("%s failure\n", __func__);
457 		return;
458 	}
459 }
460 
461 void gpi2c_init(void)
462 {
463 	/* When needed to be invoked prior to BSS initialization */
464 	static bool first_time = true;
465 
466 	if (first_time) {
467 		enable_i2c0_pin_mux();
468 		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
469 			 CONFIG_SYS_OMAP24_I2C_SLAVE);
470 		first_time = false;
471 	}
472 }
473 
474 void scale_vcores(void)
475 {
476 	const struct dpll_params *mpu_params;
477 
478 	/* Ensure I2C is initialized for PMIC configuration */
479 	gpi2c_init();
480 
481 	/* Get the frequency */
482 	mpu_params = get_dpll_mpu_params();
483 
484 	if (board_is_idk())
485 		scale_vcores_idk(mpu_params->m);
486 	else
487 		scale_vcores_generic(mpu_params->m);
488 }
489 
490 void set_uart_mux_conf(void)
491 {
492 	enable_uart0_pin_mux();
493 }
494 
495 void set_mux_conf_regs(void)
496 {
497 	enable_board_pin_mux();
498 }
499 
500 static void enable_vtt_regulator(void)
501 {
502 	u32 temp;
503 
504 	/* enable module */
505 	writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
506 
507 	/* enable output for GPIO5_7 */
508 	writel(GPIO_SETDATAOUT(7),
509 	       AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
510 	temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
511 	temp = temp & ~(GPIO_OE_ENABLE(7));
512 	writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
513 }
514 
515 void sdram_init(void)
516 {
517 	/*
518 	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
519 	 * GP EMV has 1GB DDR3 connected to EMIF
520 	 * along with VTT regulator.
521 	 */
522 	if (board_is_eposevm()) {
523 		config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
524 	} else if (board_is_evm_14_or_later()) {
525 		enable_vtt_regulator();
526 		config_ddr(0, &ioregs_ddr3, NULL, NULL,
527 			   &ddr3_emif_regs_400Mhz_production, 0);
528 	} else if (board_is_evm_12_or_later()) {
529 		enable_vtt_regulator();
530 		config_ddr(0, &ioregs_ddr3, NULL, NULL,
531 			   &ddr3_emif_regs_400Mhz_beta, 0);
532 	} else if (board_is_evm()) {
533 		enable_vtt_regulator();
534 		config_ddr(0, &ioregs_ddr3, NULL, NULL,
535 			   &ddr3_emif_regs_400Mhz, 0);
536 	} else if (board_is_sk()) {
537 		config_ddr(400, &ioregs_ddr3, NULL, NULL,
538 			   &ddr3_sk_emif_regs_400Mhz, 0);
539 	} else if (board_is_idk()) {
540 		config_ddr(400, &ioregs_ddr3, NULL, NULL,
541 			   &ddr3_idk_emif_regs_400Mhz, 0);
542 	}
543 }
544 #endif
545 
546 /* setup board specific PMIC */
547 int power_init_board(void)
548 {
549 	struct pmic *p;
550 
551 	if (board_is_idk()) {
552 		power_tps62362_init(I2C_PMIC);
553 		p = pmic_get("TPS62362");
554 		if (p && !pmic_probe(p))
555 			puts("PMIC:  TPS62362\n");
556 	} else {
557 		power_tps65218_init(I2C_PMIC);
558 		p = pmic_get("TPS65218_PMIC");
559 		if (p && !pmic_probe(p))
560 			puts("PMIC:  TPS65218\n");
561 	}
562 
563 	return 0;
564 }
565 
566 int board_init(void)
567 {
568 	struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
569 	u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
570 	    modena_init0_bw_integer, modena_init0_watermark_0;
571 
572 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
573 	gpmc_init();
574 
575 	/* Clear all important bits for DSS errata that may need to be tweaked*/
576 	mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
577 	                   MREQPRIO_0_SAB_INIT0_MASK;
578 
579 	mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
580 
581 	modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
582 	                                   BW_LIMITER_BW_FRAC_MASK;
583 
584 	modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
585 	                                BW_LIMITER_BW_INT_MASK;
586 
587 	modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
588 	                                 BW_LIMITER_BW_WATERMARK_MASK;
589 
590 	/* Setting MReq Priority of the DSS*/
591 	mreqprio_0 |= 0x77;
592 
593 	/*
594 	 * Set L3 Fast Configuration Register
595 	 * Limiting bandwith for ARM core to 700 MBPS
596 	 */
597 	modena_init0_bw_fractional |= 0x10;
598 	modena_init0_bw_integer |= 0x3;
599 
600 	writel(mreqprio_0, &cdev->mreqprio_0);
601 	writel(mreqprio_1, &cdev->mreqprio_1);
602 
603 	writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
604 	writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
605 	writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
606 
607 	return 0;
608 }
609 
610 #ifdef CONFIG_BOARD_LATE_INIT
611 int board_late_init(void)
612 {
613 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
614 	set_board_info_env(NULL);
615 
616 	/*
617 	 * Default FIT boot on HS devices. Non FIT images are not allowed
618 	 * on HS devices.
619 	 */
620 	if (get_device_type() == HS_DEVICE)
621 		setenv("boot_fit", "1");
622 #endif
623 	return 0;
624 }
625 #endif
626 
627 #ifdef CONFIG_USB_DWC3
628 static struct dwc3_device usb_otg_ss1 = {
629 	.maximum_speed = USB_SPEED_HIGH,
630 	.base = USB_OTG_SS1_BASE,
631 	.tx_fifo_resize = false,
632 	.index = 0,
633 };
634 
635 static struct dwc3_omap_device usb_otg_ss1_glue = {
636 	.base = (void *)USB_OTG_SS1_GLUE_BASE,
637 	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
638 	.index = 0,
639 };
640 
641 static struct ti_usb_phy_device usb_phy1_device = {
642 	.usb2_phy_power = (void *)USB2_PHY1_POWER,
643 	.index = 0,
644 };
645 
646 static struct dwc3_device usb_otg_ss2 = {
647 	.maximum_speed = USB_SPEED_HIGH,
648 	.base = USB_OTG_SS2_BASE,
649 	.tx_fifo_resize = false,
650 	.index = 1,
651 };
652 
653 static struct dwc3_omap_device usb_otg_ss2_glue = {
654 	.base = (void *)USB_OTG_SS2_GLUE_BASE,
655 	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
656 	.index = 1,
657 };
658 
659 static struct ti_usb_phy_device usb_phy2_device = {
660 	.usb2_phy_power = (void *)USB2_PHY2_POWER,
661 	.index = 1,
662 };
663 
664 int usb_gadget_handle_interrupts(int index)
665 {
666 	u32 status;
667 
668 	status = dwc3_omap_uboot_interrupt_status(index);
669 	if (status)
670 		dwc3_uboot_handle_interrupt(index);
671 
672 	return 0;
673 }
674 #endif /* CONFIG_USB_DWC3 */
675 
676 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
677 int omap_xhci_board_usb_init(int index, enum usb_init_type init)
678 {
679 	enable_usb_clocks(index);
680 #ifdef CONFIG_USB_DWC3
681 	switch (index) {
682 	case 0:
683 		if (init == USB_INIT_DEVICE) {
684 			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
685 			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
686 			dwc3_omap_uboot_init(&usb_otg_ss1_glue);
687 			ti_usb_phy_uboot_init(&usb_phy1_device);
688 			dwc3_uboot_init(&usb_otg_ss1);
689 		}
690 		break;
691 	case 1:
692 		if (init == USB_INIT_DEVICE) {
693 			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
694 			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
695 			ti_usb_phy_uboot_init(&usb_phy2_device);
696 			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
697 			dwc3_uboot_init(&usb_otg_ss2);
698 		}
699 		break;
700 	default:
701 		printf("Invalid Controller Index\n");
702 	}
703 #endif
704 
705 	return 0;
706 }
707 
708 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
709 {
710 #ifdef CONFIG_USB_DWC3
711 	switch (index) {
712 	case 0:
713 	case 1:
714 		if (init == USB_INIT_DEVICE) {
715 			ti_usb_phy_uboot_exit(index);
716 			dwc3_uboot_exit(index);
717 			dwc3_omap_uboot_exit(index);
718 		}
719 		break;
720 	default:
721 		printf("Invalid Controller Index\n");
722 	}
723 #endif
724 	disable_usb_clocks(index);
725 
726 	return 0;
727 }
728 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
729 
730 #ifdef CONFIG_DRIVER_TI_CPSW
731 
732 static void cpsw_control(int enabled)
733 {
734 	/* Additional controls can be added here */
735 	return;
736 }
737 
738 static struct cpsw_slave_data cpsw_slaves[] = {
739 	{
740 		.slave_reg_ofs	= 0x208,
741 		.sliver_reg_ofs	= 0xd80,
742 		.phy_addr	= 16,
743 	},
744 	{
745 		.slave_reg_ofs	= 0x308,
746 		.sliver_reg_ofs	= 0xdc0,
747 		.phy_addr	= 1,
748 	},
749 };
750 
751 static struct cpsw_platform_data cpsw_data = {
752 	.mdio_base		= CPSW_MDIO_BASE,
753 	.cpsw_base		= CPSW_BASE,
754 	.mdio_div		= 0xff,
755 	.channels		= 8,
756 	.cpdma_reg_ofs		= 0x800,
757 	.slaves			= 1,
758 	.slave_data		= cpsw_slaves,
759 	.ale_reg_ofs		= 0xd00,
760 	.ale_entries		= 1024,
761 	.host_port_reg_ofs	= 0x108,
762 	.hw_stats_reg_ofs	= 0x900,
763 	.bd_ram_ofs		= 0x2000,
764 	.mac_control		= (1 << 5),
765 	.control		= cpsw_control,
766 	.host_port_num		= 0,
767 	.version		= CPSW_CTRL_VERSION_2,
768 };
769 
770 int board_eth_init(bd_t *bis)
771 {
772 	int rv;
773 	uint8_t mac_addr[6];
774 	uint32_t mac_hi, mac_lo;
775 
776 	/* try reading mac address from efuse */
777 	mac_lo = readl(&cdev->macid0l);
778 	mac_hi = readl(&cdev->macid0h);
779 	mac_addr[0] = mac_hi & 0xFF;
780 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
781 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
782 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
783 	mac_addr[4] = mac_lo & 0xFF;
784 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
785 
786 	if (!getenv("ethaddr")) {
787 		puts("<ethaddr> not set. Validating first E-fuse MAC\n");
788 		if (is_valid_ethaddr(mac_addr))
789 			eth_setenv_enetaddr("ethaddr", mac_addr);
790 	}
791 
792 	mac_lo = readl(&cdev->macid1l);
793 	mac_hi = readl(&cdev->macid1h);
794 	mac_addr[0] = mac_hi & 0xFF;
795 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
796 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
797 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
798 	mac_addr[4] = mac_lo & 0xFF;
799 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
800 
801 	if (!getenv("eth1addr")) {
802 		if (is_valid_ethaddr(mac_addr))
803 			eth_setenv_enetaddr("eth1addr", mac_addr);
804 	}
805 
806 	if (board_is_eposevm()) {
807 		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
808 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
809 		cpsw_slaves[0].phy_addr = 16;
810 	} else if (board_is_sk()) {
811 		writel(RGMII_MODE_ENABLE, &cdev->miisel);
812 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
813 		cpsw_slaves[0].phy_addr = 4;
814 		cpsw_slaves[1].phy_addr = 5;
815 	} else if (board_is_idk()) {
816 		writel(RGMII_MODE_ENABLE, &cdev->miisel);
817 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
818 		cpsw_slaves[0].phy_addr = 0;
819 	} else {
820 		writel(RGMII_MODE_ENABLE, &cdev->miisel);
821 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
822 		cpsw_slaves[0].phy_addr = 0;
823 	}
824 
825 	rv = cpsw_register(&cpsw_data);
826 	if (rv < 0)
827 		printf("Error %d registering CPSW switch\n", rv);
828 
829 	return rv;
830 }
831 #endif
832 
833 #ifdef CONFIG_SPL_LOAD_FIT
834 int board_fit_config_name_match(const char *name)
835 {
836 	if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
837 		return 0;
838 	else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
839 		return 0;
840 	else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
841 		return 0;
842 	else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
843 		return 0;
844 	else
845 		return -1;
846 }
847 #endif
848 
849 #ifdef CONFIG_TI_SECURE_DEVICE
850 void board_fit_image_post_process(void **p_image, size_t *p_size)
851 {
852 	secure_boot_verify_image(p_image, p_size);
853 }
854 #endif
855