1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <linux/errno.h> 14 #include <spl.h> 15 #include <usb.h> 16 #include <asm/omap_sec_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/mux.h> 20 #include <asm/arch/ddr_defs.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/emif.h> 23 #include <asm/omap_common.h> 24 #include "../common/board_detect.h" 25 #include "board.h" 26 #include <power/pmic.h> 27 #include <power/tps65218.h> 28 #include <power/tps62362.h> 29 #include <miiphy.h> 30 #include <cpsw.h> 31 #include <linux/usb/gadget.h> 32 #include <dwc3-uboot.h> 33 #include <dwc3-omap-uboot.h> 34 #include <ti-usb-phy-uboot.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 39 40 /* 41 * Read header information from EEPROM into global structure. 42 */ 43 #ifdef CONFIG_TI_I2C_BOARD_DETECT 44 void do_board_detect(void) 45 { 46 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 47 CONFIG_EEPROM_CHIP_ADDRESS)) 48 printf("ti_i2c_eeprom_init failed\n"); 49 } 50 #endif 51 52 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 53 54 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 55 { /* 19.2 MHz */ 56 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ 57 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 58 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ 59 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ 60 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ 61 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ 62 }, 63 { /* 24 MHz */ 64 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 65 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 66 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 67 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 68 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 69 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 70 }, 71 { /* 25 MHz */ 72 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 73 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 74 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 75 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 76 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 77 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 78 }, 79 { /* 26 MHz */ 80 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 81 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 82 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 83 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 84 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 85 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 86 }, 87 }; 88 89 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 90 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ 91 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 92 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 93 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 94 }; 95 96 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 97 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 98 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ 99 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ 100 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ 101 }; 102 103 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { 104 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ 105 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ 106 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ 107 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ 108 }; 109 110 const struct dpll_params gp_evm_dpll_ddr = { 111 50, 2, 1, -1, 2, -1, -1}; 112 113 static const struct dpll_params idk_dpll_ddr = { 114 400, 23, 1, -1, 2, -1, -1 115 }; 116 117 static const u32 ext_phy_ctrl_const_base_lpddr2[] = { 118 0x00500050, 119 0x00350035, 120 0x00350035, 121 0x00350035, 122 0x00350035, 123 0x00350035, 124 0x00000000, 125 0x00000000, 126 0x00000000, 127 0x00000000, 128 0x00000000, 129 0x00000000, 130 0x00000000, 131 0x00000000, 132 0x00000000, 133 0x00000000, 134 0x00000000, 135 0x00000000, 136 0x40001000, 137 0x08102040 138 }; 139 140 const struct ctrl_ioregs ioregs_lpddr2 = { 141 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 142 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 143 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 144 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 145 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 146 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 147 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 148 .emif_sdram_config_ext = 0x1, 149 }; 150 151 const struct emif_regs emif_regs_lpddr2 = { 152 .sdram_config = 0x808012BA, 153 .ref_ctrl = 0x0000040D, 154 .sdram_tim1 = 0xEA86B411, 155 .sdram_tim2 = 0x103A094A, 156 .sdram_tim3 = 0x0F6BA37F, 157 .read_idle_ctrl = 0x00050000, 158 .zq_config = 0x50074BE4, 159 .temp_alert_config = 0x0, 160 .emif_rd_wr_lvl_rmp_win = 0x0, 161 .emif_rd_wr_lvl_rmp_ctl = 0x0, 162 .emif_rd_wr_lvl_ctl = 0x0, 163 .emif_ddr_phy_ctlr_1 = 0x0E284006, 164 .emif_rd_wr_exec_thresh = 0x80000405, 165 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 166 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 167 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 168 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 169 .emif_ddr_ext_phy_ctrl_5 = 0x00500050, 170 .emif_prio_class_serv_map = 0x80000001, 171 .emif_connect_id_serv_1_map = 0x80000094, 172 .emif_connect_id_serv_2_map = 0x00000000, 173 .emif_cos_config = 0x000FFFFF 174 }; 175 176 const struct ctrl_ioregs ioregs_ddr3 = { 177 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 178 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 179 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 180 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 181 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 182 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 183 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 184 .emif_sdram_config_ext = 0xc163, 185 }; 186 187 const struct emif_regs ddr3_emif_regs_400Mhz = { 188 .sdram_config = 0x638413B2, 189 .ref_ctrl = 0x00000C30, 190 .sdram_tim1 = 0xEAAAD4DB, 191 .sdram_tim2 = 0x266B7FDA, 192 .sdram_tim3 = 0x107F8678, 193 .read_idle_ctrl = 0x00050000, 194 .zq_config = 0x50074BE4, 195 .temp_alert_config = 0x0, 196 .emif_ddr_phy_ctlr_1 = 0x0E004008, 197 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 198 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 199 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 200 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 201 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 202 .emif_rd_wr_lvl_rmp_win = 0x0, 203 .emif_rd_wr_lvl_rmp_ctl = 0x0, 204 .emif_rd_wr_lvl_ctl = 0x0, 205 .emif_rd_wr_exec_thresh = 0x80000405, 206 .emif_prio_class_serv_map = 0x80000001, 207 .emif_connect_id_serv_1_map = 0x80000094, 208 .emif_connect_id_serv_2_map = 0x00000000, 209 .emif_cos_config = 0x000FFFFF 210 }; 211 212 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ 213 const struct emif_regs ddr3_emif_regs_400Mhz_beta = { 214 .sdram_config = 0x638413B2, 215 .ref_ctrl = 0x00000C30, 216 .sdram_tim1 = 0xEAAAD4DB, 217 .sdram_tim2 = 0x266B7FDA, 218 .sdram_tim3 = 0x107F8678, 219 .read_idle_ctrl = 0x00050000, 220 .zq_config = 0x50074BE4, 221 .temp_alert_config = 0x0, 222 .emif_ddr_phy_ctlr_1 = 0x0E004008, 223 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 224 .emif_ddr_ext_phy_ctrl_2 = 0x00000065, 225 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 226 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, 227 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, 228 .emif_rd_wr_exec_thresh = 0x80000405, 229 .emif_prio_class_serv_map = 0x80000001, 230 .emif_connect_id_serv_1_map = 0x80000094, 231 .emif_connect_id_serv_2_map = 0x00000000, 232 .emif_cos_config = 0x000FFFFF 233 }; 234 235 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 236 const struct emif_regs ddr3_emif_regs_400Mhz_production = { 237 .sdram_config = 0x638413B2, 238 .ref_ctrl = 0x00000C30, 239 .sdram_tim1 = 0xEAAAD4DB, 240 .sdram_tim2 = 0x266B7FDA, 241 .sdram_tim3 = 0x107F8678, 242 .read_idle_ctrl = 0x00050000, 243 .zq_config = 0x50074BE4, 244 .temp_alert_config = 0x0, 245 .emif_ddr_phy_ctlr_1 = 0x0E004008, 246 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 247 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 248 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 249 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 250 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 251 .emif_rd_wr_exec_thresh = 0x80000405, 252 .emif_prio_class_serv_map = 0x80000001, 253 .emif_connect_id_serv_1_map = 0x80000094, 254 .emif_connect_id_serv_2_map = 0x00000000, 255 .emif_cos_config = 0x000FFFFF 256 }; 257 258 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { 259 .sdram_config = 0x638413b2, 260 .sdram_config2 = 0x00000000, 261 .ref_ctrl = 0x00000c30, 262 .sdram_tim1 = 0xeaaad4db, 263 .sdram_tim2 = 0x266b7fda, 264 .sdram_tim3 = 0x107f8678, 265 .read_idle_ctrl = 0x00050000, 266 .zq_config = 0x50074be4, 267 .temp_alert_config = 0x0, 268 .emif_ddr_phy_ctlr_1 = 0x0e084008, 269 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 270 .emif_ddr_ext_phy_ctrl_2 = 0x89, 271 .emif_ddr_ext_phy_ctrl_3 = 0x90, 272 .emif_ddr_ext_phy_ctrl_4 = 0x8e, 273 .emif_ddr_ext_phy_ctrl_5 = 0x8d, 274 .emif_rd_wr_lvl_rmp_win = 0x0, 275 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 276 .emif_rd_wr_lvl_ctl = 0x00000000, 277 .emif_rd_wr_exec_thresh = 0x80000000, 278 .emif_prio_class_serv_map = 0x80000001, 279 .emif_connect_id_serv_1_map = 0x80000094, 280 .emif_connect_id_serv_2_map = 0x00000000, 281 .emif_cos_config = 0x000FFFFF 282 }; 283 284 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { 285 .sdram_config = 0x61a11b32, 286 .sdram_config2 = 0x00000000, 287 .ref_ctrl = 0x00000c30, 288 .sdram_tim1 = 0xeaaad4db, 289 .sdram_tim2 = 0x266b7fda, 290 .sdram_tim3 = 0x107f8678, 291 .read_idle_ctrl = 0x00050000, 292 .zq_config = 0x50074be4, 293 .temp_alert_config = 0x00000000, 294 .emif_ddr_phy_ctlr_1 = 0x00008009, 295 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 296 .emif_ddr_ext_phy_ctrl_2 = 0x00000040, 297 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, 298 .emif_ddr_ext_phy_ctrl_4 = 0x00000051, 299 .emif_ddr_ext_phy_ctrl_5 = 0x00000051, 300 .emif_rd_wr_lvl_rmp_win = 0x00000000, 301 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 302 .emif_rd_wr_lvl_ctl = 0x00000000, 303 .emif_rd_wr_exec_thresh = 0x00000405, 304 .emif_prio_class_serv_map = 0x00000000, 305 .emif_connect_id_serv_1_map = 0x00000000, 306 .emif_connect_id_serv_2_map = 0x00000000, 307 .emif_cos_config = 0x00ffffff 308 }; 309 310 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 311 { 312 if (board_is_eposevm()) { 313 *regs = ext_phy_ctrl_const_base_lpddr2; 314 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 315 } 316 317 return; 318 } 319 320 const struct dpll_params *get_dpll_ddr_params(void) 321 { 322 int ind = get_sys_clk_index(); 323 324 if (board_is_eposevm()) 325 return &epos_evm_dpll_ddr[ind]; 326 else if (board_is_evm() || board_is_sk()) 327 return &gp_evm_dpll_ddr; 328 else if (board_is_idk()) 329 return &idk_dpll_ddr; 330 331 printf(" Board '%s' not supported\n", board_ti_get_name()); 332 return NULL; 333 } 334 335 336 /* 337 * get_opp_offset: 338 * Returns the index for safest OPP of the device to boot. 339 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 340 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 341 * This data is read from dev_attribute register which is e-fused. 342 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 343 * OPP available. Lowest OPP starts with min_off. So returning the 344 * bit with rightmost '0'. 345 */ 346 static int get_opp_offset(int max_off, int min_off) 347 { 348 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 349 int opp, offset, i; 350 351 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 352 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 353 354 for (i = max_off; i >= min_off; i--) { 355 offset = opp & (1 << i); 356 if (!offset) 357 return i; 358 } 359 360 return min_off; 361 } 362 363 const struct dpll_params *get_dpll_mpu_params(void) 364 { 365 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 366 u32 ind = get_sys_clk_index(); 367 368 return &dpll_mpu[ind][opp]; 369 } 370 371 const struct dpll_params *get_dpll_core_params(void) 372 { 373 int ind = get_sys_clk_index(); 374 375 return &dpll_core[ind]; 376 } 377 378 const struct dpll_params *get_dpll_per_params(void) 379 { 380 int ind = get_sys_clk_index(); 381 382 return &dpll_per[ind]; 383 } 384 385 void scale_vcores_generic(u32 m) 386 { 387 int mpu_vdd; 388 389 if (i2c_probe(TPS65218_CHIP_PM)) 390 return; 391 392 switch (m) { 393 case 1000: 394 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 395 break; 396 case 800: 397 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; 398 break; 399 case 720: 400 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; 401 break; 402 case 600: 403 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 404 break; 405 case 300: 406 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; 407 break; 408 default: 409 puts("Unknown MPU clock, not scaling\n"); 410 return; 411 } 412 413 /* Set DCDC1 (CORE) voltage to 1.1V */ 414 if (tps65218_voltage_update(TPS65218_DCDC1, 415 TPS65218_DCDC_VOLT_SEL_1100MV)) { 416 printf("%s failure\n", __func__); 417 return; 418 } 419 420 /* Set DCDC2 (MPU) voltage */ 421 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 422 printf("%s failure\n", __func__); 423 return; 424 } 425 426 /* Set DCDC3 (DDR) voltage */ 427 if (tps65218_voltage_update(TPS65218_DCDC3, 428 TPS65218_DCDC3_VOLT_SEL_1350MV)) { 429 printf("%s failure\n", __func__); 430 return; 431 } 432 } 433 434 void scale_vcores_idk(u32 m) 435 { 436 int mpu_vdd; 437 438 if (i2c_probe(TPS62362_I2C_ADDR)) 439 return; 440 441 switch (m) { 442 case 1000: 443 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 444 break; 445 case 800: 446 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; 447 break; 448 case 720: 449 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; 450 break; 451 case 600: 452 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; 453 break; 454 case 300: 455 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 456 break; 457 default: 458 puts("Unknown MPU clock, not scaling\n"); 459 return; 460 } 461 462 /* Set VDD_MPU voltage */ 463 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { 464 printf("%s failure\n", __func__); 465 return; 466 } 467 } 468 469 void gpi2c_init(void) 470 { 471 /* When needed to be invoked prior to BSS initialization */ 472 static bool first_time = true; 473 474 if (first_time) { 475 enable_i2c0_pin_mux(); 476 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 477 CONFIG_SYS_OMAP24_I2C_SLAVE); 478 first_time = false; 479 } 480 } 481 482 void scale_vcores(void) 483 { 484 const struct dpll_params *mpu_params; 485 486 /* Ensure I2C is initialized for PMIC configuration */ 487 gpi2c_init(); 488 489 /* Get the frequency */ 490 mpu_params = get_dpll_mpu_params(); 491 492 if (board_is_idk()) 493 scale_vcores_idk(mpu_params->m); 494 else 495 scale_vcores_generic(mpu_params->m); 496 } 497 498 void set_uart_mux_conf(void) 499 { 500 enable_uart0_pin_mux(); 501 } 502 503 void set_mux_conf_regs(void) 504 { 505 enable_board_pin_mux(); 506 } 507 508 static void enable_vtt_regulator(void) 509 { 510 u32 temp; 511 512 /* enable module */ 513 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 514 515 /* enable output for GPIO5_7 */ 516 writel(GPIO_SETDATAOUT(7), 517 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 518 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 519 temp = temp & ~(GPIO_OE_ENABLE(7)); 520 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 521 } 522 523 enum { 524 RTC_BOARD_EPOS = 1, 525 RTC_BOARD_EVM14, 526 RTC_BOARD_EVM12, 527 RTC_BOARD_GPEVM, 528 RTC_BOARD_SK, 529 }; 530 531 /* 532 * In the rtc_only+DRR in self-refresh boot path we have the board type info 533 * in the rtc scratch pad register hence we bypass the costly i2c reads to 534 * eeprom and directly programthe board name string 535 */ 536 void rtc_only_update_board_type(u32 btype) 537 { 538 const char *name = ""; 539 const char *rev = "1.0"; 540 541 switch (btype) { 542 case RTC_BOARD_EPOS: 543 name = "AM43EPOS"; 544 break; 545 case RTC_BOARD_EVM14: 546 name = "AM43__GP"; 547 rev = "1.4"; 548 break; 549 case RTC_BOARD_EVM12: 550 name = "AM43__GP"; 551 rev = "1.2"; 552 break; 553 case RTC_BOARD_GPEVM: 554 name = "AM43__GP"; 555 break; 556 case RTC_BOARD_SK: 557 name = "AM43__SK"; 558 break; 559 } 560 ti_i2c_eeprom_am_set(name, rev); 561 } 562 563 u32 rtc_only_get_board_type(void) 564 { 565 if (board_is_eposevm()) 566 return RTC_BOARD_EPOS; 567 else if (board_is_evm_14_or_later()) 568 return RTC_BOARD_EVM14; 569 else if (board_is_evm_12_or_later()) 570 return RTC_BOARD_EVM12; 571 else if (board_is_gpevm()) 572 return RTC_BOARD_GPEVM; 573 else if (board_is_sk()) 574 return RTC_BOARD_SK; 575 576 return 0; 577 } 578 579 void sdram_init(void) 580 { 581 /* 582 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 583 * GP EMV has 1GB DDR3 connected to EMIF 584 * along with VTT regulator. 585 */ 586 if (board_is_eposevm()) { 587 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 588 } else if (board_is_evm_14_or_later()) { 589 enable_vtt_regulator(); 590 config_ddr(0, &ioregs_ddr3, NULL, NULL, 591 &ddr3_emif_regs_400Mhz_production, 0); 592 } else if (board_is_evm_12_or_later()) { 593 enable_vtt_regulator(); 594 config_ddr(0, &ioregs_ddr3, NULL, NULL, 595 &ddr3_emif_regs_400Mhz_beta, 0); 596 } else if (board_is_evm()) { 597 enable_vtt_regulator(); 598 config_ddr(0, &ioregs_ddr3, NULL, NULL, 599 &ddr3_emif_regs_400Mhz, 0); 600 } else if (board_is_sk()) { 601 config_ddr(400, &ioregs_ddr3, NULL, NULL, 602 &ddr3_sk_emif_regs_400Mhz, 0); 603 } else if (board_is_idk()) { 604 config_ddr(400, &ioregs_ddr3, NULL, NULL, 605 &ddr3_idk_emif_regs_400Mhz, 0); 606 } 607 } 608 #endif 609 610 /* setup board specific PMIC */ 611 int power_init_board(void) 612 { 613 struct pmic *p; 614 615 if (board_is_idk()) { 616 power_tps62362_init(I2C_PMIC); 617 p = pmic_get("TPS62362"); 618 if (p && !pmic_probe(p)) 619 puts("PMIC: TPS62362\n"); 620 } else { 621 power_tps65218_init(I2C_PMIC); 622 p = pmic_get("TPS65218_PMIC"); 623 if (p && !pmic_probe(p)) 624 puts("PMIC: TPS65218\n"); 625 } 626 627 return 0; 628 } 629 630 int board_init(void) 631 { 632 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; 633 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, 634 modena_init0_bw_integer, modena_init0_watermark_0; 635 636 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 637 gpmc_init(); 638 639 /* 640 * Call this to initialize *ctrl again 641 */ 642 hw_data_init(); 643 644 /* Clear all important bits for DSS errata that may need to be tweaked*/ 645 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & 646 MREQPRIO_0_SAB_INIT0_MASK; 647 648 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; 649 650 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & 651 BW_LIMITER_BW_FRAC_MASK; 652 653 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & 654 BW_LIMITER_BW_INT_MASK; 655 656 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & 657 BW_LIMITER_BW_WATERMARK_MASK; 658 659 /* Setting MReq Priority of the DSS*/ 660 mreqprio_0 |= 0x77; 661 662 /* 663 * Set L3 Fast Configuration Register 664 * Limiting bandwith for ARM core to 700 MBPS 665 */ 666 modena_init0_bw_fractional |= 0x10; 667 modena_init0_bw_integer |= 0x3; 668 669 writel(mreqprio_0, &cdev->mreqprio_0); 670 writel(mreqprio_1, &cdev->mreqprio_1); 671 672 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); 673 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); 674 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); 675 676 return 0; 677 } 678 679 #ifdef CONFIG_BOARD_LATE_INIT 680 int board_late_init(void) 681 { 682 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 683 set_board_info_env(NULL); 684 685 /* 686 * Default FIT boot on HS devices. Non FIT images are not allowed 687 * on HS devices. 688 */ 689 if (get_device_type() == HS_DEVICE) 690 env_set("boot_fit", "1"); 691 #endif 692 return 0; 693 } 694 #endif 695 696 #ifdef CONFIG_USB_DWC3 697 static struct dwc3_device usb_otg_ss1 = { 698 .maximum_speed = USB_SPEED_HIGH, 699 .base = USB_OTG_SS1_BASE, 700 .tx_fifo_resize = false, 701 .index = 0, 702 }; 703 704 static struct dwc3_omap_device usb_otg_ss1_glue = { 705 .base = (void *)USB_OTG_SS1_GLUE_BASE, 706 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 707 .index = 0, 708 }; 709 710 static struct ti_usb_phy_device usb_phy1_device = { 711 .usb2_phy_power = (void *)USB2_PHY1_POWER, 712 .index = 0, 713 }; 714 715 static struct dwc3_device usb_otg_ss2 = { 716 .maximum_speed = USB_SPEED_HIGH, 717 .base = USB_OTG_SS2_BASE, 718 .tx_fifo_resize = false, 719 .index = 1, 720 }; 721 722 static struct dwc3_omap_device usb_otg_ss2_glue = { 723 .base = (void *)USB_OTG_SS2_GLUE_BASE, 724 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 725 .index = 1, 726 }; 727 728 static struct ti_usb_phy_device usb_phy2_device = { 729 .usb2_phy_power = (void *)USB2_PHY2_POWER, 730 .index = 1, 731 }; 732 733 int usb_gadget_handle_interrupts(int index) 734 { 735 u32 status; 736 737 status = dwc3_omap_uboot_interrupt_status(index); 738 if (status) 739 dwc3_uboot_handle_interrupt(index); 740 741 return 0; 742 } 743 #endif /* CONFIG_USB_DWC3 */ 744 745 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 746 int board_usb_init(int index, enum usb_init_type init) 747 { 748 enable_usb_clocks(index); 749 #ifdef CONFIG_USB_DWC3 750 switch (index) { 751 case 0: 752 if (init == USB_INIT_DEVICE) { 753 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 754 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 755 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 756 ti_usb_phy_uboot_init(&usb_phy1_device); 757 dwc3_uboot_init(&usb_otg_ss1); 758 } 759 break; 760 case 1: 761 if (init == USB_INIT_DEVICE) { 762 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 763 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 764 ti_usb_phy_uboot_init(&usb_phy2_device); 765 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 766 dwc3_uboot_init(&usb_otg_ss2); 767 } 768 break; 769 default: 770 printf("Invalid Controller Index\n"); 771 } 772 #endif 773 774 return 0; 775 } 776 777 int board_usb_cleanup(int index, enum usb_init_type init) 778 { 779 #ifdef CONFIG_USB_DWC3 780 switch (index) { 781 case 0: 782 case 1: 783 if (init == USB_INIT_DEVICE) { 784 ti_usb_phy_uboot_exit(index); 785 dwc3_uboot_exit(index); 786 dwc3_omap_uboot_exit(index); 787 } 788 break; 789 default: 790 printf("Invalid Controller Index\n"); 791 } 792 #endif 793 disable_usb_clocks(index); 794 795 return 0; 796 } 797 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 798 799 #ifdef CONFIG_DRIVER_TI_CPSW 800 801 static void cpsw_control(int enabled) 802 { 803 /* Additional controls can be added here */ 804 return; 805 } 806 807 static struct cpsw_slave_data cpsw_slaves[] = { 808 { 809 .slave_reg_ofs = 0x208, 810 .sliver_reg_ofs = 0xd80, 811 .phy_addr = 16, 812 }, 813 { 814 .slave_reg_ofs = 0x308, 815 .sliver_reg_ofs = 0xdc0, 816 .phy_addr = 1, 817 }, 818 }; 819 820 static struct cpsw_platform_data cpsw_data = { 821 .mdio_base = CPSW_MDIO_BASE, 822 .cpsw_base = CPSW_BASE, 823 .mdio_div = 0xff, 824 .channels = 8, 825 .cpdma_reg_ofs = 0x800, 826 .slaves = 1, 827 .slave_data = cpsw_slaves, 828 .ale_reg_ofs = 0xd00, 829 .ale_entries = 1024, 830 .host_port_reg_ofs = 0x108, 831 .hw_stats_reg_ofs = 0x900, 832 .bd_ram_ofs = 0x2000, 833 .mac_control = (1 << 5), 834 .control = cpsw_control, 835 .host_port_num = 0, 836 .version = CPSW_CTRL_VERSION_2, 837 }; 838 839 int board_eth_init(bd_t *bis) 840 { 841 int rv; 842 uint8_t mac_addr[6]; 843 uint32_t mac_hi, mac_lo; 844 845 /* try reading mac address from efuse */ 846 mac_lo = readl(&cdev->macid0l); 847 mac_hi = readl(&cdev->macid0h); 848 mac_addr[0] = mac_hi & 0xFF; 849 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 850 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 851 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 852 mac_addr[4] = mac_lo & 0xFF; 853 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 854 855 if (!env_get("ethaddr")) { 856 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 857 if (is_valid_ethaddr(mac_addr)) 858 eth_env_set_enetaddr("ethaddr", mac_addr); 859 } 860 861 mac_lo = readl(&cdev->macid1l); 862 mac_hi = readl(&cdev->macid1h); 863 mac_addr[0] = mac_hi & 0xFF; 864 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 865 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 866 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 867 mac_addr[4] = mac_lo & 0xFF; 868 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 869 870 if (!env_get("eth1addr")) { 871 if (is_valid_ethaddr(mac_addr)) 872 eth_env_set_enetaddr("eth1addr", mac_addr); 873 } 874 875 if (board_is_eposevm()) { 876 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 877 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 878 cpsw_slaves[0].phy_addr = 16; 879 } else if (board_is_sk()) { 880 writel(RGMII_MODE_ENABLE, &cdev->miisel); 881 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 882 cpsw_slaves[0].phy_addr = 4; 883 cpsw_slaves[1].phy_addr = 5; 884 } else if (board_is_idk()) { 885 writel(RGMII_MODE_ENABLE, &cdev->miisel); 886 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 887 cpsw_slaves[0].phy_addr = 0; 888 } else { 889 writel(RGMII_MODE_ENABLE, &cdev->miisel); 890 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 891 cpsw_slaves[0].phy_addr = 0; 892 } 893 894 rv = cpsw_register(&cpsw_data); 895 if (rv < 0) 896 printf("Error %d registering CPSW switch\n", rv); 897 898 return rv; 899 } 900 #endif 901 902 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 903 int ft_board_setup(void *blob, bd_t *bd) 904 { 905 ft_cpu_setup(blob, bd); 906 907 return 0; 908 } 909 #endif 910 911 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT) 912 int board_fit_config_name_match(const char *name) 913 { 914 bool eeprom_read = board_ti_was_eeprom_read(); 915 916 if (!strcmp(name, "am4372-generic") && !eeprom_read) 917 return 0; 918 else if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) 919 return 0; 920 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) 921 return 0; 922 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) 923 return 0; 924 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) 925 return 0; 926 else 927 return -1; 928 } 929 #endif 930 931 #ifdef CONFIG_DTB_RESELECT 932 int embedded_dtb_select(void) 933 { 934 do_board_detect(); 935 fdtdec_setup(); 936 937 return 0; 938 } 939 #endif 940 941 #ifdef CONFIG_TI_SECURE_DEVICE 942 void board_fit_image_post_process(void **p_image, size_t *p_size) 943 { 944 secure_boot_verify_image(p_image, p_size); 945 } 946 947 void board_tee_image_process(ulong tee_image, size_t tee_size) 948 { 949 secure_tee_install((u32)tee_image); 950 } 951 952 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 953 #endif 954