1 /* 2 * am3517crane.h - Header file for the AM3517 CraneBoard. 3 * 4 * Author: Srinath R <srinath@mistralsolutions.com> 5 * 6 * Based on logicpd/am3517evm/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions Pvt Ltd 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #ifndef _AM3517CRANE_H_ 26 #define _AM3517CRANE_H_ 27 28 const omap3_sysinfo sysinfo = { 29 DDR_DISCRETE, 30 "CraneBoard", 31 "NAND", 32 }; 33 /* AM3517 specific mux configuration */ 34 #define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 35 /* CCDC */ 36 #define CONTROL_PADCONF_CCDC_PCLK 0x01E4 37 #define CONTROL_PADCONF_CCDC_FIELD 0x01E6 38 #define CONTROL_PADCONF_CCDC_HD 0x01E8 39 #define CONTROL_PADCONF_CCDC_VD 0x01EA 40 #define CONTROL_PADCONF_CCDC_WEN 0x01EC 41 #define CONTROL_PADCONF_CCDC_DATA0 0x01EE 42 #define CONTROL_PADCONF_CCDC_DATA1 0x01F0 43 #define CONTROL_PADCONF_CCDC_DATA2 0x01F2 44 #define CONTROL_PADCONF_CCDC_DATA3 0x01F4 45 #define CONTROL_PADCONF_CCDC_DATA4 0x01F6 46 #define CONTROL_PADCONF_CCDC_DATA5 0x01F8 47 #define CONTROL_PADCONF_CCDC_DATA6 0x01FA 48 #define CONTROL_PADCONF_CCDC_DATA7 0x01FC 49 /* RMII */ 50 #define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE 51 #define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 52 #define CONTROL_PADCONF_RMII_RXD0 0x0202 53 #define CONTROL_PADCONF_RMII_RXD1 0x0204 54 #define CONTROL_PADCONF_RMII_CRS_DV 0x0206 55 #define CONTROL_PADCONF_RMII_RXER 0x0208 56 #define CONTROL_PADCONF_RMII_TXD0 0x020A 57 #define CONTROL_PADCONF_RMII_TXD1 0x020C 58 #define CONTROL_PADCONF_RMII_TXEN 0x020E 59 #define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 60 #define CONTROL_PADCONF_USB0_DRVBUS 0x0212 61 /* CAN */ 62 #define CONTROL_PADCONF_HECC1_TXD 0x0214 63 #define CONTROL_PADCONF_HECC1_RXD 0x0216 64 #define CONTROL_PADCONF_SYS_BOOT7 0x0218 65 #define CONTROL_PADCONF_SDRC_DQS0N 0x021A 66 #define CONTROL_PADCONF_SDRC_DQS1N 0x021C 67 #define CONTROL_PADCONF_SDRC_DQS2N 0x021E 68 #define CONTROL_PADCONF_SDRC_DQS3N 0x0220 69 #define CONTROL_PADCONF_STRBEN_DLY0 0x0222 70 #define CONTROL_PADCONF_STRBEN_DLY1 0x0224 71 #define CONTROL_PADCONF_SYS_BOOT8 0x0226 72 73 /* 74 * IEN - Input Enable 75 * IDIS - Input Disable 76 * PTD - Pull type Down 77 * PTU - Pull type Up 78 * DIS - Pull type selection is inactive 79 * EN - Pull type selection is active 80 * M0 - Mode 0 81 * The commented string gives the final mux configuration for that pin 82 */ 83 #define MUX_AM3517CRANE()\ 84 /*SDRC*/\ 85 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\ 86 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\ 87 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\ 88 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\ 89 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\ 90 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\ 91 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\ 92 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\ 93 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\ 94 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\ 95 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\ 96 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\ 97 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\ 98 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\ 99 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\ 100 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\ 101 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\ 102 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\ 103 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\ 104 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\ 105 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\ 106 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\ 107 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\ 108 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\ 109 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\ 110 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\ 111 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\ 112 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\ 113 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\ 114 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\ 115 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\ 116 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\ 117 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\ 118 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\ 119 MUX_VAL(CP(SDRC_CKE0), (M0))\ 120 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\ 121 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\ 122 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\ 123 MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\ 124 MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\ 125 MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\ 126 MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\ 127 MUX_VAL(CP(SDRC_CKE0), (M0))\ 128 MUX_VAL(CP(SDRC_CKE1), (M0))\ 129 /*sdrc_strben_dly0*/\ 130 MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\ 131 /*sdrc_strben_dly1*/\ 132 MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\ 133 /*GPMC*/\ 134 MUX_VAL(CP(GPMC_A1), (M7))\ 135 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\ 136 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\ 137 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\ 138 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\ 139 MUX_VAL(CP(GPMC_A6), (M7))\ 140 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\ 141 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\ 142 MUX_VAL(CP(GPMC_A9), (M7))\ 143 MUX_VAL(CP(GPMC_A10), (M7))\ 144 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\ 145 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\ 146 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\ 147 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\ 148 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\ 149 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\ 150 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\ 151 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\ 152 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\ 153 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\ 154 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\ 155 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\ 156 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\ 157 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\ 158 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\ 159 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\ 160 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\ 161 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\ 162 MUX_VAL(CP(GPMC_NCS2), (M7))\ 163 MUX_VAL(CP(GPMC_NCS3), (M7))\ 164 MUX_VAL(CP(GPMC_NCS4), (M7))\ 165 MUX_VAL(CP(GPMC_NCS5), (M7))\ 166 MUX_VAL(CP(GPMC_NCS6), (M7))\ 167 MUX_VAL(CP(GPMC_NCS7), (M7))\ 168 MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\ 169 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\ 170 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\ 171 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\ 172 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\ 173 MUX_VAL(CP(GPMC_NBE1), (M7))\ 174 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\ 175 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\ 176 MUX_VAL(CP(GPMC_WAIT1), (M7))\ 177 MUX_VAL(CP(GPMC_WAIT2), (M7))\ 178 MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\ 179 /*DSS*/\ 180 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\ 181 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\ 182 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\ 183 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\ 184 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\ 185 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\ 186 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\ 187 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\ 188 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\ 189 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\ 190 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\ 191 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\ 192 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\ 193 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\ 194 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\ 195 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\ 196 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\ 197 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\ 198 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\ 199 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ 200 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\ 201 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\ 202 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\ 203 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\ 204 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\ 205 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\ 206 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\ 207 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\ 208 /*MMC1*/\ 209 MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\ 210 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\ 211 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\ 212 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\ 213 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\ 214 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\ 215 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\ 216 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\ 217 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\ 218 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\ 219 /*MMC2*/\ 220 MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\ 221 MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\ 222 MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\ 223 MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\ 224 MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\ 225 MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\ 226 MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\ 227 MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\ 228 MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\ 229 MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\ 230 /*McBSP*/\ 231 MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\ 232 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\ 233 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\ 234 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\ 235 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\ 236 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\ 237 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\ 238 \ 239 MUX_VAL(CP(MCBSP2_FSX), (M7))\ 240 MUX_VAL(CP(MCBSP2_CLKX), (M7))\ 241 MUX_VAL(CP(MCBSP2_DR), (M7))\ 242 MUX_VAL(CP(MCBSP2_DX), (M7))\ 243 \ 244 MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\ 245 MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\ 246 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\ 247 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\ 248 \ 249 MUX_VAL(CP(MCBSP4_CLKX), (M7))\ 250 MUX_VAL(CP(MCBSP4_DR), (M7))\ 251 MUX_VAL(CP(MCBSP4_DX), (M7))\ 252 MUX_VAL(CP(MCBSP4_FSX), (M7))\ 253 /*UART*/\ 254 MUX_VAL(CP(UART1_TX), (M7))\ 255 MUX_VAL(CP(UART1_RTS), (M7))\ 256 MUX_VAL(CP(UART1_CTS), (M7))\ 257 MUX_VAL(CP(UART1_RX), (M7))\ 258 \ 259 MUX_VAL(CP(UART2_CTS), (M7))\ 260 MUX_VAL(CP(UART2_RTS), (M7))\ 261 MUX_VAL(CP(UART2_TX), (M7))\ 262 MUX_VAL(CP(UART2_RX), (M7))\ 263 \ 264 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\ 265 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\ 266 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\ 267 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\ 268 /*I2C 1, 2, 3*/\ 269 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\ 270 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\ 271 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\ 272 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\ 273 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\ 274 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\ 275 /*McSPI*/\ 276 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\ 277 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\ 278 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\ 279 MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\ 280 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\ 281 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\ 282 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\ 283 \ 284 MUX_VAL(CP(MCSPI2_CLK), (M7))\ 285 MUX_VAL(CP(MCSPI2_SIMO), (M7))\ 286 MUX_VAL(CP(MCSPI2_SOMI), (M7))\ 287 MUX_VAL(CP(MCSPI2_CS0), (M7))\ 288 MUX_VAL(CP(MCSPI2_CS1), (M7))\ 289 /*CCDC*/\ 290 MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\ 291 MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\ 292 MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\ 293 MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\ 294 MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\ 295 MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\ 296 MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\ 297 MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\ 298 MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\ 299 MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\ 300 MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\ 301 MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\ 302 MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\ 303 /*RMII*/\ 304 MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\ 305 MUX_VAL(CP(RMII_MDIO_CLK), (M0))\ 306 MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\ 307 MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\ 308 MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\ 309 MUX_VAL(CP(RMII_RXER), (PTD | M0))\ 310 MUX_VAL(CP(RMII_TXD0), (PTD | M0))\ 311 MUX_VAL(CP(RMII_TXD1), (PTD | M0))\ 312 MUX_VAL(CP(RMII_TXEN), (PTD | M0))\ 313 MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\ 314 /*HECC*/\ 315 MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\ 316 MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\ 317 /*HSUSB*/\ 318 MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\ 319 /*HDQ*/\ 320 MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\ 321 /*Control and debug*/\ 322 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\ 323 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\ 324 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\ 325 /*SYS_nRESWARM*/\ 326 MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\ 327 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\ 328 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\ 329 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\ 330 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\ 331 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\ 332 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\ 333 MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\ 334 MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\ 335 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\ 336 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\ 337 /*JTAG*/\ 338 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ 339 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ 340 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ 341 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ 342 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\ 343 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\ 344 /*ETK (ES2 onwards)*/\ 345 MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\ 346 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\ 347 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\ 348 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\ 349 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\ 350 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\ 351 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\ 352 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\ 353 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\ 354 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\ 355 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\ 356 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\ 357 MUX_VAL(CP(ETK_D10_ES2), (M7))\ 358 MUX_VAL(CP(ETK_D11_ES2), (M7))\ 359 MUX_VAL(CP(ETK_D12_ES2), (M7))\ 360 MUX_VAL(CP(ETK_D13_ES2), (M7))\ 361 MUX_VAL(CP(ETK_D14_ES2), (M7))\ 362 MUX_VAL(CP(ETK_D15_ES2), (M7))\ 363 /*Die to Die*/\ 364 MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\ 365 MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\ 366 MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\ 367 MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\ 368 MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\ 369 MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\ 370 MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\ 371 MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\ 372 MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\ 373 MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\ 374 MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\ 375 MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\ 376 MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\ 377 MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\ 378 MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\ 379 MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\ 380 MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\ 381 MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\ 382 MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\ 383 MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\ 384 MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\ 385 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\ 386 MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\ 387 MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\ 388 MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\ 389 MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\ 390 MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\ 391 MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\ 392 MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\ 393 MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\ 394 395 #endif /* _AM3517CRANE_H_ */ 396