1 /* 2 * mux.c 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <common.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/mux.h> 20 #include <asm/io.h> 21 #include <i2c.h> 22 #include "../common/board_detect.h" 23 #include "board.h" 24 25 static struct module_pin_mux uart0_pin_mux[] = { 26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 28 {-1}, 29 }; 30 31 static struct module_pin_mux uart1_pin_mux[] = { 32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ 33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ 34 {-1}, 35 }; 36 37 static struct module_pin_mux uart2_pin_mux[] = { 38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ 39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ 40 {-1}, 41 }; 42 43 static struct module_pin_mux uart3_pin_mux[] = { 44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ 45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ 46 {-1}, 47 }; 48 49 static struct module_pin_mux uart4_pin_mux[] = { 50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ 51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ 52 {-1}, 53 }; 54 55 static struct module_pin_mux uart5_pin_mux[] = { 56 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ 57 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ 58 {-1}, 59 }; 60 61 static struct module_pin_mux mmc0_pin_mux[] = { 62 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 63 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 64 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 65 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 66 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 67 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 68 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ 69 {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */ 70 {-1}, 71 }; 72 73 static struct module_pin_mux mmc0_no_cd_pin_mux[] = { 74 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 75 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 76 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 77 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 78 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 79 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 80 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ 81 {-1}, 82 }; 83 84 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { 85 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 86 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 87 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 88 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 89 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 90 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 91 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 92 {-1}, 93 }; 94 95 static struct module_pin_mux mmc1_pin_mux[] = { 96 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 97 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ 98 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ 99 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ 100 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ 101 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ 102 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ 103 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */ 104 {-1}, 105 }; 106 107 static struct module_pin_mux i2c0_pin_mux[] = { 108 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 109 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 110 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 111 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 112 {-1}, 113 }; 114 115 static struct module_pin_mux i2c1_pin_mux[] = { 116 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | 117 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 118 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | 119 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 120 {-1}, 121 }; 122 123 static struct module_pin_mux spi0_pin_mux[] = { 124 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ 125 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | 126 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ 127 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ 128 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | 129 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ 130 {-1}, 131 }; 132 133 static struct module_pin_mux gpio0_7_pin_mux[] = { 134 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ 135 {-1}, 136 }; 137 138 static struct module_pin_mux gpio0_18_pin_mux[] = { 139 {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */ 140 {-1}, 141 }; 142 143 static struct module_pin_mux rgmii1_pin_mux[] = { 144 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ 145 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 146 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ 147 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ 148 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ 149 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ 150 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ 151 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 152 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 153 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 154 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 155 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 156 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 157 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 158 {-1}, 159 }; 160 161 static struct module_pin_mux mii1_pin_mux[] = { 162 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ 163 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ 164 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ 165 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ 166 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ 167 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ 168 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ 169 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ 170 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ 171 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ 172 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ 173 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ 174 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ 175 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 176 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 177 {-1}, 178 }; 179 180 static struct module_pin_mux rmii1_pin_mux[] = { 181 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 182 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 183 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */ 184 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */ 185 {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */ 186 {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */ 187 {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */ 188 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */ 189 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */ 190 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ 191 {-1}, 192 }; 193 194 #ifdef CONFIG_NAND 195 static struct module_pin_mux nand_pin_mux[] = { 196 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ 197 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ 198 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ 199 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ 200 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ 201 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ 202 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ 203 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ 204 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT 205 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ 206 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ 207 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ 208 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ 209 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ 210 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ 211 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ 212 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ 213 #endif 214 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ 215 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ 216 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ 217 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ 218 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ 219 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ 220 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ 221 {-1}, 222 }; 223 #elif defined(CONFIG_NOR) 224 static struct module_pin_mux bone_norcape_pin_mux[] = { 225 {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ 226 {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ 227 {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ 228 {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ 229 {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ 230 {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ 231 {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ 232 {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ 233 {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ 234 {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ 235 {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ 236 {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ 237 {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ 238 {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ 239 {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ 240 {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ 241 {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ 242 {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ 243 {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ 244 {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ 245 {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ 246 {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ 247 {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ 248 {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ 249 {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ 250 {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ 251 {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ 252 {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ 253 {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ 254 {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ 255 {-1}, 256 }; 257 #endif 258 259 static struct module_pin_mux uart3_icev2_pin_mux[] = { 260 {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ 261 {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */ 262 {-1}, 263 }; 264 265 #if defined(CONFIG_NOR_BOOT) 266 void enable_norboot_pin_mux(void) 267 { 268 configure_module_pin_mux(bone_norcape_pin_mux); 269 } 270 #endif 271 272 void enable_uart0_pin_mux(void) 273 { 274 configure_module_pin_mux(uart0_pin_mux); 275 } 276 277 void enable_uart1_pin_mux(void) 278 { 279 configure_module_pin_mux(uart1_pin_mux); 280 } 281 282 void enable_uart2_pin_mux(void) 283 { 284 configure_module_pin_mux(uart2_pin_mux); 285 } 286 287 void enable_uart3_pin_mux(void) 288 { 289 configure_module_pin_mux(uart3_pin_mux); 290 } 291 292 void enable_uart4_pin_mux(void) 293 { 294 configure_module_pin_mux(uart4_pin_mux); 295 } 296 297 void enable_uart5_pin_mux(void) 298 { 299 configure_module_pin_mux(uart5_pin_mux); 300 } 301 302 void enable_i2c0_pin_mux(void) 303 { 304 configure_module_pin_mux(i2c0_pin_mux); 305 } 306 307 /* 308 * The AM335x GP EVM, if daughter card(s) are connected, can have 8 309 * different profiles. These profiles determine what peripherals are 310 * valid and need pinmux to be configured. 311 */ 312 #define PROFILE_NONE 0x0 313 #define PROFILE_0 (1 << 0) 314 #define PROFILE_1 (1 << 1) 315 #define PROFILE_2 (1 << 2) 316 #define PROFILE_3 (1 << 3) 317 #define PROFILE_4 (1 << 4) 318 #define PROFILE_5 (1 << 5) 319 #define PROFILE_6 (1 << 6) 320 #define PROFILE_7 (1 << 7) 321 #define PROFILE_MASK 0x7 322 #define PROFILE_ALL 0xFF 323 324 /* CPLD registers */ 325 #define I2C_CPLD_ADDR 0x35 326 #define CFG_REG 0x10 327 328 static unsigned short detect_daughter_board_profile(void) 329 { 330 unsigned short val; 331 332 if (i2c_probe(I2C_CPLD_ADDR)) 333 return PROFILE_NONE; 334 335 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) 336 return PROFILE_NONE; 337 338 return (1 << (val & PROFILE_MASK)); 339 } 340 341 void enable_board_pin_mux(void) 342 { 343 /* Do board-specific muxes. */ 344 if (board_is_bone()) { 345 /* Beaglebone pinmux */ 346 configure_module_pin_mux(mii1_pin_mux); 347 configure_module_pin_mux(mmc0_pin_mux); 348 #if defined(CONFIG_NAND) 349 configure_module_pin_mux(nand_pin_mux); 350 #elif defined(CONFIG_NOR) 351 configure_module_pin_mux(bone_norcape_pin_mux); 352 #else 353 configure_module_pin_mux(mmc1_pin_mux); 354 #endif 355 } else if (board_is_gp_evm()) { 356 /* General Purpose EVM */ 357 unsigned short profile = detect_daughter_board_profile(); 358 configure_module_pin_mux(rgmii1_pin_mux); 359 configure_module_pin_mux(mmc0_pin_mux); 360 /* In profile #2 i2c1 and spi0 conflict. */ 361 if (profile & ~PROFILE_2) 362 configure_module_pin_mux(i2c1_pin_mux); 363 /* Profiles 2 & 3 don't have NAND */ 364 #ifdef CONFIG_NAND 365 if (profile & ~(PROFILE_2 | PROFILE_3)) 366 configure_module_pin_mux(nand_pin_mux); 367 #endif 368 else if (profile == PROFILE_2) { 369 configure_module_pin_mux(mmc1_pin_mux); 370 configure_module_pin_mux(spi0_pin_mux); 371 } 372 } else if (board_is_idk()) { 373 /* Industrial Motor Control (IDK) */ 374 configure_module_pin_mux(mii1_pin_mux); 375 configure_module_pin_mux(mmc0_no_cd_pin_mux); 376 } else if (board_is_evm_sk()) { 377 /* Starter Kit EVM */ 378 configure_module_pin_mux(i2c1_pin_mux); 379 configure_module_pin_mux(gpio0_7_pin_mux); 380 configure_module_pin_mux(rgmii1_pin_mux); 381 configure_module_pin_mux(mmc0_pin_mux_sk_evm); 382 } else if (board_is_bone_lt()) { 383 /* Beaglebone LT pinmux */ 384 configure_module_pin_mux(mii1_pin_mux); 385 configure_module_pin_mux(mmc0_pin_mux); 386 #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) 387 configure_module_pin_mux(nand_pin_mux); 388 #elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT) 389 configure_module_pin_mux(bone_norcape_pin_mux); 390 #else 391 configure_module_pin_mux(mmc1_pin_mux); 392 #endif 393 } else if (board_is_icev2()) { 394 configure_module_pin_mux(mmc0_pin_mux); 395 configure_module_pin_mux(gpio0_18_pin_mux); 396 configure_module_pin_mux(uart3_icev2_pin_mux); 397 configure_module_pin_mux(rmii1_pin_mux); 398 configure_module_pin_mux(spi0_pin_mux); 399 } else { 400 /* Unknown board. We might still be able to boot. */ 401 puts("Bad EEPROM or unknown board, cannot configure pinmux."); 402 } 403 } 404