1 /* 2 * mux.c 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <common.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/mux.h> 20 #include <asm/io.h> 21 #include <i2c.h> 22 #include "board.h" 23 24 static struct module_pin_mux uart0_pin_mux[] = { 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 27 {-1}, 28 }; 29 30 static struct module_pin_mux mmc0_pin_mux[] = { 31 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 32 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 33 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 34 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 35 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 36 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 37 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ 38 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 39 {-1}, 40 }; 41 42 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { 43 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 44 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 45 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 46 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 47 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 48 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 49 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 50 {-1}, 51 }; 52 53 static struct module_pin_mux mmc1_pin_mux[] = { 54 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 55 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ 56 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ 57 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ 58 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ 59 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ 60 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ 61 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */ 62 {-1}, 63 }; 64 65 static struct module_pin_mux i2c0_pin_mux[] = { 66 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 67 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 68 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 69 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 70 {-1}, 71 }; 72 73 static struct module_pin_mux i2c1_pin_mux[] = { 74 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | 75 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 76 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | 77 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 78 {-1}, 79 }; 80 81 static struct module_pin_mux spi0_pin_mux[] = { 82 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ 83 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | 84 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ 85 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ 86 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | 87 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ 88 {-1}, 89 }; 90 91 static struct module_pin_mux gpio0_7_pin_mux[] = { 92 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ 93 {-1}, 94 }; 95 96 static struct module_pin_mux rgmii1_pin_mux[] = { 97 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ 98 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 99 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ 100 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ 101 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ 102 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ 103 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ 104 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 105 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 106 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 107 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 108 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 109 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 110 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 111 {-1}, 112 }; 113 114 static struct module_pin_mux mii1_pin_mux[] = { 115 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ 116 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ 117 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ 118 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ 119 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ 120 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ 121 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ 122 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ 123 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ 124 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ 125 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ 126 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ 127 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ 128 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 129 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 130 {-1}, 131 }; 132 133 void enable_uart0_pin_mux(void) 134 { 135 configure_module_pin_mux(uart0_pin_mux); 136 } 137 138 139 void enable_i2c0_pin_mux(void) 140 { 141 configure_module_pin_mux(i2c0_pin_mux); 142 } 143 144 /* 145 * The AM335x GP EVM, if daughter card(s) are connected, can have 8 146 * different profiles. These profiles determine what peripherals are 147 * valid and need pinmux to be configured. 148 */ 149 #define PROFILE_NONE 0x0 150 #define PROFILE_0 (1 << 0) 151 #define PROFILE_1 (1 << 1) 152 #define PROFILE_2 (1 << 2) 153 #define PROFILE_3 (1 << 3) 154 #define PROFILE_4 (1 << 4) 155 #define PROFILE_5 (1 << 5) 156 #define PROFILE_6 (1 << 6) 157 #define PROFILE_7 (1 << 7) 158 #define PROFILE_MASK 0x7 159 #define PROFILE_ALL 0xFF 160 161 /* CPLD registers */ 162 #define I2C_CPLD_ADDR 0x35 163 #define CFG_REG 0x10 164 165 static unsigned short detect_daughter_board_profile(void) 166 { 167 unsigned short val; 168 169 if (i2c_probe(I2C_CPLD_ADDR)) 170 return PROFILE_NONE; 171 172 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) 173 return PROFILE_NONE; 174 175 return (1 << (val & PROFILE_MASK)); 176 } 177 178 void enable_board_pin_mux(struct am335x_baseboard_id *header) 179 { 180 /* Do board-specific muxes. */ 181 if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) { 182 /* Beaglebone pinmux */ 183 configure_module_pin_mux(i2c1_pin_mux); 184 configure_module_pin_mux(mii1_pin_mux); 185 configure_module_pin_mux(mmc0_pin_mux); 186 configure_module_pin_mux(mmc1_pin_mux); 187 } else if (!strncmp(header->config, "SKU#01", 6)) { 188 /* General Purpose EVM */ 189 unsigned short profile = detect_daughter_board_profile(); 190 configure_module_pin_mux(rgmii1_pin_mux); 191 configure_module_pin_mux(mmc0_pin_mux); 192 /* In profile #2 i2c1 and spi0 conflict. */ 193 if (profile & ~PROFILE_2) 194 configure_module_pin_mux(i2c1_pin_mux); 195 else if (profile == PROFILE_2) { 196 configure_module_pin_mux(mmc1_pin_mux); 197 configure_module_pin_mux(spi0_pin_mux); 198 } 199 } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) { 200 /* Starter Kit EVM */ 201 configure_module_pin_mux(i2c1_pin_mux); 202 configure_module_pin_mux(gpio0_7_pin_mux); 203 configure_module_pin_mux(rgmii1_pin_mux); 204 configure_module_pin_mux(mmc0_pin_mux_sk_evm); 205 } else { 206 puts("Unknown board, cannot configure pinmux."); 207 hang(); 208 } 209 } 210