1 /* 2 * mux.c 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <common.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/mux.h> 20 #include <asm/io.h> 21 #include <i2c.h> 22 #include "board.h" 23 24 static struct module_pin_mux uart0_pin_mux[] = { 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 27 {-1}, 28 }; 29 30 static struct module_pin_mux uart1_pin_mux[] = { 31 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ 32 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ 33 {-1}, 34 }; 35 36 static struct module_pin_mux uart2_pin_mux[] = { 37 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ 38 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ 39 {-1}, 40 }; 41 42 static struct module_pin_mux uart3_pin_mux[] = { 43 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ 44 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ 45 {-1}, 46 }; 47 48 static struct module_pin_mux uart4_pin_mux[] = { 49 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ 50 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ 51 {-1}, 52 }; 53 54 static struct module_pin_mux uart5_pin_mux[] = { 55 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ 56 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ 57 {-1}, 58 }; 59 60 static struct module_pin_mux mmc0_pin_mux[] = { 61 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 62 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 63 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 64 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 65 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 66 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 67 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ 68 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 69 {-1}, 70 }; 71 72 static struct module_pin_mux mmc0_no_cd_pin_mux[] = { 73 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 74 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 75 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 76 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 77 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 78 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 79 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ 80 {-1}, 81 }; 82 83 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { 84 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 85 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 86 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 87 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 88 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 89 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 90 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 91 {-1}, 92 }; 93 94 static struct module_pin_mux mmc1_pin_mux[] = { 95 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 96 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ 97 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ 98 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ 99 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ 100 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ 101 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ 102 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */ 103 {-1}, 104 }; 105 106 static struct module_pin_mux i2c0_pin_mux[] = { 107 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 108 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 109 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 110 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 111 {-1}, 112 }; 113 114 static struct module_pin_mux i2c1_pin_mux[] = { 115 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | 116 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 117 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | 118 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 119 {-1}, 120 }; 121 122 static struct module_pin_mux spi0_pin_mux[] = { 123 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ 124 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | 125 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ 126 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ 127 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | 128 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ 129 {-1}, 130 }; 131 132 static struct module_pin_mux gpio0_7_pin_mux[] = { 133 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ 134 {-1}, 135 }; 136 137 static struct module_pin_mux rgmii1_pin_mux[] = { 138 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ 139 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 140 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ 141 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ 142 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ 143 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ 144 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ 145 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 146 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 147 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 148 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 149 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 150 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 151 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 152 {-1}, 153 }; 154 155 static struct module_pin_mux mii1_pin_mux[] = { 156 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ 157 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ 158 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ 159 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ 160 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ 161 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ 162 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ 163 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ 164 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ 165 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ 166 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ 167 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ 168 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ 169 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 170 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 171 {-1}, 172 }; 173 174 #ifdef CONFIG_NAND 175 static struct module_pin_mux nand_pin_mux[] = { 176 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ 177 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ 178 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ 179 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ 180 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ 181 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ 182 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ 183 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ 184 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT 185 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ 186 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ 187 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ 188 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ 189 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ 190 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ 191 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ 192 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ 193 #endif 194 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ 195 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ 196 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ 197 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ 198 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ 199 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ 200 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ 201 {-1}, 202 }; 203 #elif defined(CONFIG_NOR) 204 static struct module_pin_mux bone_norcape_pin_mux[] = { 205 {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ 206 {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ 207 {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ 208 {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ 209 {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ 210 {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ 211 {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ 212 {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ 213 {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ 214 {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ 215 {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ 216 {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ 217 {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ 218 {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ 219 {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ 220 {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ 221 {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ 222 {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ 223 {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ 224 {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ 225 {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ 226 {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ 227 {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ 228 {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ 229 {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ 230 {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ 231 {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ 232 {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ 233 {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ 234 {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ 235 {-1}, 236 }; 237 #endif 238 239 #if defined(CONFIG_NOR_BOOT) 240 void enable_norboot_pin_mux(void) 241 { 242 configure_module_pin_mux(bone_norcape_pin_mux); 243 } 244 #endif 245 246 void enable_uart0_pin_mux(void) 247 { 248 configure_module_pin_mux(uart0_pin_mux); 249 } 250 251 void enable_uart1_pin_mux(void) 252 { 253 configure_module_pin_mux(uart1_pin_mux); 254 } 255 256 void enable_uart2_pin_mux(void) 257 { 258 configure_module_pin_mux(uart2_pin_mux); 259 } 260 261 void enable_uart3_pin_mux(void) 262 { 263 configure_module_pin_mux(uart3_pin_mux); 264 } 265 266 void enable_uart4_pin_mux(void) 267 { 268 configure_module_pin_mux(uart4_pin_mux); 269 } 270 271 void enable_uart5_pin_mux(void) 272 { 273 configure_module_pin_mux(uart5_pin_mux); 274 } 275 276 void enable_i2c0_pin_mux(void) 277 { 278 configure_module_pin_mux(i2c0_pin_mux); 279 } 280 281 /* 282 * The AM335x GP EVM, if daughter card(s) are connected, can have 8 283 * different profiles. These profiles determine what peripherals are 284 * valid and need pinmux to be configured. 285 */ 286 #define PROFILE_NONE 0x0 287 #define PROFILE_0 (1 << 0) 288 #define PROFILE_1 (1 << 1) 289 #define PROFILE_2 (1 << 2) 290 #define PROFILE_3 (1 << 3) 291 #define PROFILE_4 (1 << 4) 292 #define PROFILE_5 (1 << 5) 293 #define PROFILE_6 (1 << 6) 294 #define PROFILE_7 (1 << 7) 295 #define PROFILE_MASK 0x7 296 #define PROFILE_ALL 0xFF 297 298 /* CPLD registers */ 299 #define I2C_CPLD_ADDR 0x35 300 #define CFG_REG 0x10 301 302 static unsigned short detect_daughter_board_profile(void) 303 { 304 unsigned short val; 305 306 if (i2c_probe(I2C_CPLD_ADDR)) 307 return PROFILE_NONE; 308 309 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) 310 return PROFILE_NONE; 311 312 return (1 << (val & PROFILE_MASK)); 313 } 314 315 void enable_board_pin_mux(struct am335x_baseboard_id *header) 316 { 317 /* Do board-specific muxes. */ 318 if (board_is_bone(header)) { 319 /* Beaglebone pinmux */ 320 configure_module_pin_mux(i2c1_pin_mux); 321 configure_module_pin_mux(mii1_pin_mux); 322 configure_module_pin_mux(mmc0_pin_mux); 323 #if defined(CONFIG_NAND) 324 configure_module_pin_mux(nand_pin_mux); 325 #elif defined(CONFIG_NOR) 326 configure_module_pin_mux(bone_norcape_pin_mux); 327 #else 328 configure_module_pin_mux(mmc1_pin_mux); 329 #endif 330 } else if (board_is_gp_evm(header)) { 331 /* General Purpose EVM */ 332 unsigned short profile = detect_daughter_board_profile(); 333 configure_module_pin_mux(rgmii1_pin_mux); 334 configure_module_pin_mux(mmc0_pin_mux); 335 /* In profile #2 i2c1 and spi0 conflict. */ 336 if (profile & ~PROFILE_2) 337 configure_module_pin_mux(i2c1_pin_mux); 338 /* Profiles 2 & 3 don't have NAND */ 339 #ifdef CONFIG_NAND 340 if (profile & ~(PROFILE_2 | PROFILE_3)) 341 configure_module_pin_mux(nand_pin_mux); 342 #endif 343 else if (profile == PROFILE_2) { 344 configure_module_pin_mux(mmc1_pin_mux); 345 configure_module_pin_mux(spi0_pin_mux); 346 } 347 } else if (board_is_idk(header)) { 348 /* Industrial Motor Control (IDK) */ 349 configure_module_pin_mux(mii1_pin_mux); 350 configure_module_pin_mux(mmc0_no_cd_pin_mux); 351 } else if (board_is_evm_sk(header)) { 352 /* Starter Kit EVM */ 353 configure_module_pin_mux(i2c1_pin_mux); 354 configure_module_pin_mux(gpio0_7_pin_mux); 355 configure_module_pin_mux(rgmii1_pin_mux); 356 configure_module_pin_mux(mmc0_pin_mux_sk_evm); 357 } else if (board_is_bone_lt(header)) { 358 /* Beaglebone LT pinmux */ 359 configure_module_pin_mux(i2c1_pin_mux); 360 configure_module_pin_mux(mii1_pin_mux); 361 configure_module_pin_mux(mmc0_pin_mux); 362 #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) 363 configure_module_pin_mux(nand_pin_mux); 364 #elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT) 365 configure_module_pin_mux(bone_norcape_pin_mux); 366 #else 367 configure_module_pin_mux(mmc1_pin_mux); 368 #endif 369 } else { 370 puts("Unknown board, cannot configure pinmux."); 371 hang(); 372 } 373 } 374