1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <serial.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/clk_synthesizer.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/mem.h> 25 #include <asm/io.h> 26 #include <asm/emif.h> 27 #include <asm/gpio.h> 28 #include <asm/omap_sec_common.h> 29 #include <i2c.h> 30 #include <miiphy.h> 31 #include <cpsw.h> 32 #include <power/tps65217.h> 33 #include <power/tps65910.h> 34 #include <environment.h> 35 #include <watchdog.h> 36 #include <environment.h> 37 #include "../common/board_detect.h" 38 #include "board.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* GPIO that controls power to DDR on EVM-SK */ 43 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 44 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) 45 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) 46 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) 47 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) 48 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) 49 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) 50 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11) 51 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26) 52 53 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 54 55 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT) 56 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT) 57 58 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1) 59 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1) 60 61 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024) 62 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024) 63 64 /* 65 * Read header information from EEPROM into global structure. 66 */ 67 #ifdef CONFIG_TI_I2C_BOARD_DETECT 68 void do_board_detect(void) 69 { 70 enable_i2c0_pin_mux(); 71 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 72 73 if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR)) 74 printf("ti_i2c_eeprom_init failed\n"); 75 } 76 #endif 77 78 #ifndef CONFIG_DM_SERIAL 79 struct serial_device *default_serial_console(void) 80 { 81 if (board_is_icev2()) 82 return &eserial4_device; 83 else 84 return &eserial1_device; 85 } 86 #endif 87 88 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 89 static const struct ddr_data ddr2_data = { 90 .datardsratio0 = MT47H128M16RT25E_RD_DQS, 91 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, 92 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, 93 }; 94 95 static const struct cmd_control ddr2_cmd_ctrl_data = { 96 .cmd0csratio = MT47H128M16RT25E_RATIO, 97 98 .cmd1csratio = MT47H128M16RT25E_RATIO, 99 100 .cmd2csratio = MT47H128M16RT25E_RATIO, 101 }; 102 103 static const struct emif_regs ddr2_emif_reg_data = { 104 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 105 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 106 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 107 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 108 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 109 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 110 }; 111 112 static const struct emif_regs ddr2_evm_emif_reg_data = { 113 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 114 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 115 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 116 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 117 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 118 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, 119 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 120 }; 121 122 static const struct ddr_data ddr3_data = { 123 .datardsratio0 = MT41J128MJT125_RD_DQS, 124 .datawdsratio0 = MT41J128MJT125_WR_DQS, 125 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 126 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 127 }; 128 129 static const struct ddr_data ddr3_beagleblack_data = { 130 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 131 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 132 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 133 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 134 }; 135 136 static const struct ddr_data ddr3_evm_data = { 137 .datardsratio0 = MT41J512M8RH125_RD_DQS, 138 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 139 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 140 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 141 }; 142 143 static const struct ddr_data ddr3_icev2_data = { 144 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, 145 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, 146 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, 147 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, 148 }; 149 150 static const struct cmd_control ddr3_cmd_ctrl_data = { 151 .cmd0csratio = MT41J128MJT125_RATIO, 152 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 153 154 .cmd1csratio = MT41J128MJT125_RATIO, 155 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 156 157 .cmd2csratio = MT41J128MJT125_RATIO, 158 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 159 }; 160 161 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 162 .cmd0csratio = MT41K256M16HA125E_RATIO, 163 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 164 165 .cmd1csratio = MT41K256M16HA125E_RATIO, 166 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 167 168 .cmd2csratio = MT41K256M16HA125E_RATIO, 169 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 170 }; 171 172 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 173 .cmd0csratio = MT41J512M8RH125_RATIO, 174 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 175 176 .cmd1csratio = MT41J512M8RH125_RATIO, 177 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 178 179 .cmd2csratio = MT41J512M8RH125_RATIO, 180 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 181 }; 182 183 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { 184 .cmd0csratio = MT41J128MJT125_RATIO_400MHz, 185 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 186 187 .cmd1csratio = MT41J128MJT125_RATIO_400MHz, 188 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 189 190 .cmd2csratio = MT41J128MJT125_RATIO_400MHz, 191 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 192 }; 193 194 static struct emif_regs ddr3_emif_reg_data = { 195 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 196 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 197 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 198 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 199 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 200 .zq_config = MT41J128MJT125_ZQ_CFG, 201 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 202 PHY_EN_DYN_PWRDN, 203 }; 204 205 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 206 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 207 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 208 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 209 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 210 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 211 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK, 212 .zq_config = MT41K256M16HA125E_ZQ_CFG, 213 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 214 }; 215 216 static struct emif_regs ddr3_evm_emif_reg_data = { 217 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 218 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 219 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 220 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 221 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 222 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, 223 .zq_config = MT41J512M8RH125_ZQ_CFG, 224 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 225 PHY_EN_DYN_PWRDN, 226 }; 227 228 static struct emif_regs ddr3_icev2_emif_reg_data = { 229 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, 230 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, 231 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, 232 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, 233 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, 234 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, 235 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | 236 PHY_EN_DYN_PWRDN, 237 }; 238 239 #ifdef CONFIG_SPL_OS_BOOT 240 int spl_start_uboot(void) 241 { 242 /* break into full u-boot on 'c' */ 243 if (serial_tstc() && serial_getc() == 'c') 244 return 1; 245 246 #ifdef CONFIG_SPL_ENV_SUPPORT 247 env_init(); 248 env_relocate_spec(); 249 if (getenv_yesno("boot_os") != 1) 250 return 1; 251 #endif 252 253 return 0; 254 } 255 #endif 256 257 #define OSC (V_OSCK/1000000) 258 const struct dpll_params dpll_ddr = { 259 266, OSC-1, 1, -1, -1, -1, -1}; 260 const struct dpll_params dpll_ddr_evm_sk = { 261 303, OSC-1, 1, -1, -1, -1, -1}; 262 const struct dpll_params dpll_ddr_bone_black = { 263 400, OSC-1, 1, -1, -1, -1, -1}; 264 265 void am33xx_spl_board_init(void) 266 { 267 int mpu_vdd; 268 269 /* Get the frequency */ 270 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 271 272 if (board_is_bone() || board_is_bone_lt()) { 273 /* BeagleBone PMIC Code */ 274 int usb_cur_lim; 275 276 /* 277 * Only perform PMIC configurations if board rev > A1 278 * on Beaglebone White 279 */ 280 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) 281 return; 282 283 if (i2c_probe(TPS65217_CHIP_PM)) 284 return; 285 286 /* 287 * On Beaglebone White we need to ensure we have AC power 288 * before increasing the frequency. 289 */ 290 if (board_is_bone()) { 291 uchar pmic_status_reg; 292 if (tps65217_reg_read(TPS65217_STATUS, 293 &pmic_status_reg)) 294 return; 295 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 296 puts("No AC power, disabling frequency switch\n"); 297 return; 298 } 299 } 300 301 /* 302 * Override what we have detected since we know if we have 303 * a Beaglebone Black it supports 1GHz. 304 */ 305 if (board_is_bone_lt()) 306 dpll_mpu_opp100.m = MPUPLL_M_1000; 307 308 /* 309 * Increase USB current limit to 1300mA or 1800mA and set 310 * the MPU voltage controller as needed. 311 */ 312 if (dpll_mpu_opp100.m == MPUPLL_M_1000) { 313 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 314 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 315 } else { 316 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 317 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 318 } 319 320 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 321 TPS65217_POWER_PATH, 322 usb_cur_lim, 323 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 324 puts("tps65217_reg_write failure\n"); 325 326 /* Set DCDC3 (CORE) voltage to 1.125V */ 327 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 328 TPS65217_DCDC_VOLT_SEL_1125MV)) { 329 puts("tps65217_voltage_update failure\n"); 330 return; 331 } 332 333 /* Set CORE Frequencies to OPP100 */ 334 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 335 336 /* Set DCDC2 (MPU) voltage */ 337 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 338 puts("tps65217_voltage_update failure\n"); 339 return; 340 } 341 342 /* 343 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 344 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. 345 */ 346 if (board_is_bone()) { 347 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 348 TPS65217_DEFLS1, 349 TPS65217_LDO_VOLTAGE_OUT_3_3, 350 TPS65217_LDO_MASK)) 351 puts("tps65217_reg_write failure\n"); 352 } else { 353 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 354 TPS65217_DEFLS1, 355 TPS65217_LDO_VOLTAGE_OUT_1_8, 356 TPS65217_LDO_MASK)) 357 puts("tps65217_reg_write failure\n"); 358 } 359 360 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 361 TPS65217_DEFLS2, 362 TPS65217_LDO_VOLTAGE_OUT_3_3, 363 TPS65217_LDO_MASK)) 364 puts("tps65217_reg_write failure\n"); 365 } else { 366 int sil_rev; 367 368 /* 369 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 370 * MPU frequencies we support we use a CORE voltage of 371 * 1.1375V. For MPU voltage we need to switch based on 372 * the frequency we are running at. 373 */ 374 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 375 return; 376 377 /* 378 * Depending on MPU clock and PG we will need a different 379 * VDD to drive at that speed. 380 */ 381 sil_rev = readl(&cdev->deviceid) >> 28; 382 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, 383 dpll_mpu_opp100.m); 384 385 /* Tell the TPS65910 to use i2c */ 386 tps65910_set_i2c_control(); 387 388 /* First update MPU voltage. */ 389 if (tps65910_voltage_update(MPU, mpu_vdd)) 390 return; 391 392 /* Second, update the CORE voltage. */ 393 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) 394 return; 395 396 /* Set CORE Frequencies to OPP100 */ 397 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 398 } 399 400 /* Set MPU Frequency to what we detected now that voltages are set */ 401 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 402 } 403 404 const struct dpll_params *get_dpll_ddr_params(void) 405 { 406 if (board_is_evm_sk()) 407 return &dpll_ddr_evm_sk; 408 else if (board_is_bone_lt() || board_is_icev2()) 409 return &dpll_ddr_bone_black; 410 else if (board_is_evm_15_or_later()) 411 return &dpll_ddr_evm_sk; 412 else 413 return &dpll_ddr; 414 } 415 416 void set_uart_mux_conf(void) 417 { 418 #if CONFIG_CONS_INDEX == 1 419 enable_uart0_pin_mux(); 420 #elif CONFIG_CONS_INDEX == 2 421 enable_uart1_pin_mux(); 422 #elif CONFIG_CONS_INDEX == 3 423 enable_uart2_pin_mux(); 424 #elif CONFIG_CONS_INDEX == 4 425 enable_uart3_pin_mux(); 426 #elif CONFIG_CONS_INDEX == 5 427 enable_uart4_pin_mux(); 428 #elif CONFIG_CONS_INDEX == 6 429 enable_uart5_pin_mux(); 430 #endif 431 } 432 433 void set_mux_conf_regs(void) 434 { 435 enable_board_pin_mux(); 436 } 437 438 const struct ctrl_ioregs ioregs_evmsk = { 439 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 440 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 441 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 442 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 443 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 444 }; 445 446 const struct ctrl_ioregs ioregs_bonelt = { 447 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 448 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 449 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 450 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 451 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 452 }; 453 454 const struct ctrl_ioregs ioregs_evm15 = { 455 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 456 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 457 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, 458 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 459 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 460 }; 461 462 const struct ctrl_ioregs ioregs = { 463 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 464 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 465 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 466 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 467 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 468 }; 469 470 void sdram_init(void) 471 { 472 if (board_is_evm_sk()) { 473 /* 474 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 475 * This is safe enough to do on older revs. 476 */ 477 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 478 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 479 } 480 481 if (board_is_icev2()) { 482 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); 483 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); 484 } 485 486 if (board_is_evm_sk()) 487 config_ddr(303, &ioregs_evmsk, &ddr3_data, 488 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 489 else if (board_is_bone_lt()) 490 config_ddr(400, &ioregs_bonelt, 491 &ddr3_beagleblack_data, 492 &ddr3_beagleblack_cmd_ctrl_data, 493 &ddr3_beagleblack_emif_reg_data, 0); 494 else if (board_is_evm_15_or_later()) 495 config_ddr(303, &ioregs_evm15, &ddr3_evm_data, 496 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 497 else if (board_is_icev2()) 498 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, 499 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 500 0); 501 else if (board_is_gp_evm()) 502 config_ddr(266, &ioregs, &ddr2_data, 503 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0); 504 else 505 config_ddr(266, &ioregs, &ddr2_data, 506 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 507 } 508 #endif 509 510 #if !defined(CONFIG_SPL_BUILD) || \ 511 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 512 static void request_and_set_gpio(int gpio, char *name, int val) 513 { 514 int ret; 515 516 ret = gpio_request(gpio, name); 517 if (ret < 0) { 518 printf("%s: Unable to request %s\n", __func__, name); 519 return; 520 } 521 522 ret = gpio_direction_output(gpio, 0); 523 if (ret < 0) { 524 printf("%s: Unable to set %s as output\n", __func__, name); 525 goto err_free_gpio; 526 } 527 528 gpio_set_value(gpio, val); 529 530 return; 531 532 err_free_gpio: 533 gpio_free(gpio); 534 } 535 536 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1); 537 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0); 538 539 /** 540 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock 541 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle 542 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to 543 * give 50MHz output for Eth0 and 1. 544 */ 545 static struct clk_synth cdce913_data = { 546 .id = 0x81, 547 .capacitor = 0x90, 548 .mux = 0x6d, 549 .pdiv2 = 0x2, 550 .pdiv3 = 0x2, 551 }; 552 #endif 553 554 /* 555 * Basic board specific setup. Pinmux has been handled already. 556 */ 557 int board_init(void) 558 { 559 #if defined(CONFIG_HW_WATCHDOG) 560 hw_watchdog_init(); 561 #endif 562 563 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 564 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 565 gpmc_init(); 566 #endif 567 568 #if !defined(CONFIG_SPL_BUILD) || \ 569 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 570 if (board_is_icev2()) { 571 int rv; 572 u32 reg; 573 574 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); 575 /* Make J19 status available on GPIO1_26 */ 576 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL); 577 578 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); 579 /* 580 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using 581 * jumpers near the port. Read the jumper value and set 582 * the pinmux, external mux and PHY clock accordingly. 583 * As jumper line is overridden by PHY RX_DV pin immediately 584 * after bootstrap (power-up/reset), we need to sample 585 * it during PHY reset using GPIO rising edge detection. 586 */ 587 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); 588 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */ 589 reg = readl(GPIO0_RISINGDETECT) | BIT(11); 590 writel(reg, GPIO0_RISINGDETECT); 591 reg = readl(GPIO1_RISINGDETECT) | BIT(26); 592 writel(reg, GPIO1_RISINGDETECT); 593 /* Reset PHYs to capture the Jumper setting */ 594 gpio_set_value(GPIO_PHY_RESET, 0); 595 udelay(2); /* PHY datasheet states 1uS min. */ 596 gpio_set_value(GPIO_PHY_RESET, 1); 597 598 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11); 599 if (reg) { 600 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */ 601 /* RMII mode */ 602 printf("ETH0, CPSW\n"); 603 } else { 604 /* MII mode */ 605 printf("ETH0, PRU\n"); 606 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ 607 } 608 609 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26); 610 if (reg) { 611 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */ 612 /* RMII mode */ 613 printf("ETH1, CPSW\n"); 614 gpio_set_value(GPIO_MUX_MII_CTRL, 1); 615 } else { 616 /* MII mode */ 617 printf("ETH1, PRU\n"); 618 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ 619 } 620 621 /* disable rising edge IRQs */ 622 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11); 623 writel(reg, GPIO0_RISINGDETECT); 624 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26); 625 writel(reg, GPIO1_RISINGDETECT); 626 627 rv = setup_clock_synthesizer(&cdce913_data); 628 if (rv) { 629 printf("Clock synthesizer setup failed %d\n", rv); 630 return rv; 631 } 632 633 /* reset PHYs */ 634 gpio_set_value(GPIO_PHY_RESET, 0); 635 udelay(2); /* PHY datasheet states 1uS min. */ 636 gpio_set_value(GPIO_PHY_RESET, 1); 637 } 638 #endif 639 640 return 0; 641 } 642 643 #ifdef CONFIG_BOARD_LATE_INIT 644 int board_late_init(void) 645 { 646 #if !defined(CONFIG_SPL_BUILD) 647 uint8_t mac_addr[6]; 648 uint32_t mac_hi, mac_lo; 649 #endif 650 651 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 652 char *name = NULL; 653 654 if (board_is_bone_lt()) { 655 /* BeagleBoard.org BeagleBone Black Wireless: */ 656 if (!strncmp(board_ti_get_rev(), "BWA", 3)) { 657 name = "BBBW"; 658 } 659 /* SeeedStudio BeagleBone Green Wireless */ 660 if (!strncmp(board_ti_get_rev(), "GW1", 3)) { 661 name = "BBGW"; 662 } 663 /* BeagleBoard.org BeagleBone Blue */ 664 if (!strncmp(board_ti_get_rev(), "BLA", 3)) { 665 name = "BBBL"; 666 } 667 } 668 669 if (board_is_bbg1()) 670 name = "BBG1"; 671 set_board_info_env(name); 672 673 /* 674 * Default FIT boot on HS devices. Non FIT images are not allowed 675 * on HS devices. 676 */ 677 if (get_device_type() == HS_DEVICE) 678 setenv("boot_fit", "1"); 679 #endif 680 681 #if !defined(CONFIG_SPL_BUILD) 682 /* try reading mac address from efuse */ 683 mac_lo = readl(&cdev->macid0l); 684 mac_hi = readl(&cdev->macid0h); 685 mac_addr[0] = mac_hi & 0xFF; 686 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 687 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 688 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 689 mac_addr[4] = mac_lo & 0xFF; 690 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 691 692 if (!getenv("ethaddr")) { 693 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 694 695 if (is_valid_ethaddr(mac_addr)) 696 eth_setenv_enetaddr("ethaddr", mac_addr); 697 } 698 699 mac_lo = readl(&cdev->macid1l); 700 mac_hi = readl(&cdev->macid1h); 701 mac_addr[0] = mac_hi & 0xFF; 702 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 703 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 704 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 705 mac_addr[4] = mac_lo & 0xFF; 706 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 707 708 if (!getenv("eth1addr")) { 709 if (is_valid_ethaddr(mac_addr)) 710 eth_setenv_enetaddr("eth1addr", mac_addr); 711 } 712 #endif 713 714 return 0; 715 } 716 #endif 717 718 #ifndef CONFIG_DM_ETH 719 720 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 721 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 722 static void cpsw_control(int enabled) 723 { 724 /* VTP can be added here */ 725 726 return; 727 } 728 729 static struct cpsw_slave_data cpsw_slaves[] = { 730 { 731 .slave_reg_ofs = 0x208, 732 .sliver_reg_ofs = 0xd80, 733 .phy_addr = 0, 734 }, 735 { 736 .slave_reg_ofs = 0x308, 737 .sliver_reg_ofs = 0xdc0, 738 .phy_addr = 1, 739 }, 740 }; 741 742 static struct cpsw_platform_data cpsw_data = { 743 .mdio_base = CPSW_MDIO_BASE, 744 .cpsw_base = CPSW_BASE, 745 .mdio_div = 0xff, 746 .channels = 8, 747 .cpdma_reg_ofs = 0x800, 748 .slaves = 1, 749 .slave_data = cpsw_slaves, 750 .ale_reg_ofs = 0xd00, 751 .ale_entries = 1024, 752 .host_port_reg_ofs = 0x108, 753 .hw_stats_reg_ofs = 0x900, 754 .bd_ram_ofs = 0x2000, 755 .mac_control = (1 << 5), 756 .control = cpsw_control, 757 .host_port_num = 0, 758 .version = CPSW_CTRL_VERSION_2, 759 }; 760 #endif 761 762 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ 763 defined(CONFIG_SPL_BUILD)) || \ 764 ((defined(CONFIG_DRIVER_TI_CPSW) || \ 765 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ 766 !defined(CONFIG_SPL_BUILD)) 767 768 /* 769 * This function will: 770 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr 771 * in the environment 772 * Perform fixups to the PHY present on certain boards. We only need this 773 * function in: 774 * - SPL with either CPSW or USB ethernet support 775 * - Full U-Boot, with either CPSW or USB ethernet 776 * Build in only these cases to avoid warnings about unused variables 777 * when we build an SPL that has neither option but full U-Boot will. 778 */ 779 int board_eth_init(bd_t *bis) 780 { 781 int rv, n = 0; 782 #if defined(CONFIG_USB_ETHER) && \ 783 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 784 uint8_t mac_addr[6]; 785 uint32_t mac_hi, mac_lo; 786 787 /* 788 * use efuse mac address for USB ethernet as we know that 789 * both CPSW and USB ethernet will never be active at the same time 790 */ 791 mac_lo = readl(&cdev->macid0l); 792 mac_hi = readl(&cdev->macid0h); 793 mac_addr[0] = mac_hi & 0xFF; 794 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 795 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 796 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 797 mac_addr[4] = mac_lo & 0xFF; 798 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 799 #endif 800 801 802 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 803 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 804 805 #ifdef CONFIG_DRIVER_TI_CPSW 806 if (board_is_bone() || board_is_bone_lt() || 807 board_is_idk()) { 808 writel(MII_MODE_ENABLE, &cdev->miisel); 809 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 810 PHY_INTERFACE_MODE_MII; 811 } else if (board_is_icev2()) { 812 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 813 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 814 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; 815 cpsw_slaves[0].phy_addr = 1; 816 cpsw_slaves[1].phy_addr = 3; 817 } else { 818 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 819 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 820 PHY_INTERFACE_MODE_RGMII; 821 } 822 823 rv = cpsw_register(&cpsw_data); 824 if (rv < 0) 825 printf("Error %d registering CPSW switch\n", rv); 826 else 827 n += rv; 828 #endif 829 830 /* 831 * 832 * CPSW RGMII Internal Delay Mode is not supported in all PVT 833 * operating points. So we must set the TX clock delay feature 834 * in the AR8051 PHY. Since we only support a single ethernet 835 * device in U-Boot, we only do this for the first instance. 836 */ 837 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 838 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 839 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 840 #define AR8051_RGMII_TX_CLK_DLY 0x100 841 842 if (board_is_evm_sk() || board_is_gp_evm()) { 843 const char *devname; 844 devname = miiphy_get_current_dev(); 845 846 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 847 AR8051_DEBUG_RGMII_CLK_DLY_REG); 848 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 849 AR8051_RGMII_TX_CLK_DLY); 850 } 851 #endif 852 #if defined(CONFIG_USB_ETHER) && \ 853 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 854 if (is_valid_ethaddr(mac_addr)) 855 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 856 857 rv = usb_eth_initialize(bis); 858 if (rv < 0) 859 printf("Error %d registering USB_ETHER\n", rv); 860 else 861 n += rv; 862 #endif 863 return n; 864 } 865 #endif 866 867 #endif /* CONFIG_DM_ETH */ 868 869 #ifdef CONFIG_SPL_LOAD_FIT 870 int board_fit_config_name_match(const char *name) 871 { 872 if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) 873 return 0; 874 else if (board_is_bone() && !strcmp(name, "am335x-bone")) 875 return 0; 876 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) 877 return 0; 878 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) 879 return 0; 880 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) 881 return 0; 882 else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) 883 return 0; 884 else 885 return -1; 886 } 887 #endif 888 889 #ifdef CONFIG_TI_SECURE_DEVICE 890 void board_fit_image_post_process(void **p_image, size_t *p_size) 891 { 892 secure_boot_verify_image(p_image, p_size); 893 } 894 #endif 895