1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * board.c 4 * 5 * Board functions for TI AM335X based boards 6 * 7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <serial.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/clk_synthesizer.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/mem.h> 25 #include <asm/io.h> 26 #include <asm/emif.h> 27 #include <asm/gpio.h> 28 #include <asm/omap_common.h> 29 #include <asm/omap_sec_common.h> 30 #include <asm/omap_mmc.h> 31 #include <i2c.h> 32 #include <miiphy.h> 33 #include <cpsw.h> 34 #include <power/tps65217.h> 35 #include <power/tps65910.h> 36 #include <environment.h> 37 #include <watchdog.h> 38 #include <environment.h> 39 #include "../common/board_detect.h" 40 #include "board.h" 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* GPIO that controls power to DDR on EVM-SK */ 45 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 46 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) 47 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) 48 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) 49 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) 50 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) 51 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) 52 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11) 53 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26) 54 55 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 56 57 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT) 58 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT) 59 60 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1) 61 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1) 62 63 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024) 64 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024) 65 66 /* 67 * Read header information from EEPROM into global structure. 68 */ 69 #ifdef CONFIG_TI_I2C_BOARD_DETECT 70 void do_board_detect(void) 71 { 72 enable_i2c0_pin_mux(); 73 #ifndef CONFIG_DM_I2C 74 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 75 #endif 76 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 77 CONFIG_EEPROM_CHIP_ADDRESS)) 78 printf("ti_i2c_eeprom_init failed\n"); 79 } 80 #endif 81 82 #ifndef CONFIG_DM_SERIAL 83 struct serial_device *default_serial_console(void) 84 { 85 if (board_is_icev2()) 86 return &eserial4_device; 87 else 88 return &eserial1_device; 89 } 90 #endif 91 92 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 93 static const struct ddr_data ddr2_data = { 94 .datardsratio0 = MT47H128M16RT25E_RD_DQS, 95 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, 96 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, 97 }; 98 99 static const struct cmd_control ddr2_cmd_ctrl_data = { 100 .cmd0csratio = MT47H128M16RT25E_RATIO, 101 102 .cmd1csratio = MT47H128M16RT25E_RATIO, 103 104 .cmd2csratio = MT47H128M16RT25E_RATIO, 105 }; 106 107 static const struct emif_regs ddr2_emif_reg_data = { 108 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 109 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 110 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 111 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 112 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 113 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 114 }; 115 116 static const struct emif_regs ddr2_evm_emif_reg_data = { 117 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 118 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 119 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 120 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 121 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 122 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, 123 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 124 }; 125 126 static const struct ddr_data ddr3_data = { 127 .datardsratio0 = MT41J128MJT125_RD_DQS, 128 .datawdsratio0 = MT41J128MJT125_WR_DQS, 129 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 130 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 131 }; 132 133 static const struct ddr_data ddr3_beagleblack_data = { 134 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 135 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 136 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 137 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 138 }; 139 140 static const struct ddr_data ddr3_evm_data = { 141 .datardsratio0 = MT41J512M8RH125_RD_DQS, 142 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 143 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 144 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 145 }; 146 147 static const struct ddr_data ddr3_icev2_data = { 148 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, 149 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, 150 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, 151 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, 152 }; 153 154 static const struct cmd_control ddr3_cmd_ctrl_data = { 155 .cmd0csratio = MT41J128MJT125_RATIO, 156 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 157 158 .cmd1csratio = MT41J128MJT125_RATIO, 159 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 160 161 .cmd2csratio = MT41J128MJT125_RATIO, 162 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 163 }; 164 165 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 166 .cmd0csratio = MT41K256M16HA125E_RATIO, 167 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 168 169 .cmd1csratio = MT41K256M16HA125E_RATIO, 170 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 171 172 .cmd2csratio = MT41K256M16HA125E_RATIO, 173 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 174 }; 175 176 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 177 .cmd0csratio = MT41J512M8RH125_RATIO, 178 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 179 180 .cmd1csratio = MT41J512M8RH125_RATIO, 181 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 182 183 .cmd2csratio = MT41J512M8RH125_RATIO, 184 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 185 }; 186 187 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { 188 .cmd0csratio = MT41J128MJT125_RATIO_400MHz, 189 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 190 191 .cmd1csratio = MT41J128MJT125_RATIO_400MHz, 192 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 193 194 .cmd2csratio = MT41J128MJT125_RATIO_400MHz, 195 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 196 }; 197 198 static struct emif_regs ddr3_emif_reg_data = { 199 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 200 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 201 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 202 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 203 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 204 .zq_config = MT41J128MJT125_ZQ_CFG, 205 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 206 PHY_EN_DYN_PWRDN, 207 }; 208 209 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 210 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 211 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 212 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 213 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 214 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 215 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK, 216 .zq_config = MT41K256M16HA125E_ZQ_CFG, 217 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 218 }; 219 220 static struct emif_regs ddr3_evm_emif_reg_data = { 221 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 222 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 223 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 224 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 225 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 226 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, 227 .zq_config = MT41J512M8RH125_ZQ_CFG, 228 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 229 PHY_EN_DYN_PWRDN, 230 }; 231 232 static struct emif_regs ddr3_icev2_emif_reg_data = { 233 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, 234 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, 235 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, 236 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, 237 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, 238 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, 239 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | 240 PHY_EN_DYN_PWRDN, 241 }; 242 243 #ifdef CONFIG_SPL_OS_BOOT 244 int spl_start_uboot(void) 245 { 246 #ifdef CONFIG_SPL_SERIAL_SUPPORT 247 /* break into full u-boot on 'c' */ 248 if (serial_tstc() && serial_getc() == 'c') 249 return 1; 250 #endif 251 252 #ifdef CONFIG_SPL_ENV_SUPPORT 253 env_init(); 254 env_load(); 255 if (env_get_yesno("boot_os") != 1) 256 return 1; 257 #endif 258 259 return 0; 260 } 261 #endif 262 263 const struct dpll_params *get_dpll_ddr_params(void) 264 { 265 int ind = get_sys_clk_index(); 266 267 if (board_is_evm_sk()) 268 return &dpll_ddr3_303MHz[ind]; 269 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2()) 270 return &dpll_ddr3_400MHz[ind]; 271 else if (board_is_evm_15_or_later()) 272 return &dpll_ddr3_303MHz[ind]; 273 else 274 return &dpll_ddr2_266MHz[ind]; 275 } 276 277 static u8 bone_not_connected_to_ac_power(void) 278 { 279 if (board_is_bone()) { 280 uchar pmic_status_reg; 281 if (tps65217_reg_read(TPS65217_STATUS, 282 &pmic_status_reg)) 283 return 1; 284 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 285 puts("No AC power, switching to default OPP\n"); 286 return 1; 287 } 288 } 289 return 0; 290 } 291 292 const struct dpll_params *get_dpll_mpu_params(void) 293 { 294 int ind = get_sys_clk_index(); 295 int freq = am335x_get_efuse_mpu_max_freq(cdev); 296 297 if (bone_not_connected_to_ac_power()) 298 freq = MPUPLL_M_600; 299 300 if (board_is_pb() || board_is_bone_lt()) 301 freq = MPUPLL_M_1000; 302 303 switch (freq) { 304 case MPUPLL_M_1000: 305 return &dpll_mpu_opp[ind][5]; 306 case MPUPLL_M_800: 307 return &dpll_mpu_opp[ind][4]; 308 case MPUPLL_M_720: 309 return &dpll_mpu_opp[ind][3]; 310 case MPUPLL_M_600: 311 return &dpll_mpu_opp[ind][2]; 312 case MPUPLL_M_500: 313 return &dpll_mpu_opp100; 314 case MPUPLL_M_300: 315 return &dpll_mpu_opp[ind][0]; 316 } 317 318 return &dpll_mpu_opp[ind][0]; 319 } 320 321 static void scale_vcores_bone(int freq) 322 { 323 int usb_cur_lim, mpu_vdd; 324 325 /* 326 * Only perform PMIC configurations if board rev > A1 327 * on Beaglebone White 328 */ 329 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) 330 return; 331 332 #ifndef CONFIG_DM_I2C 333 if (i2c_probe(TPS65217_CHIP_PM)) 334 return; 335 #else 336 if (power_tps65217_init(0)) 337 return; 338 #endif 339 340 341 /* 342 * On Beaglebone White we need to ensure we have AC power 343 * before increasing the frequency. 344 */ 345 if (bone_not_connected_to_ac_power()) 346 freq = MPUPLL_M_600; 347 348 /* 349 * Override what we have detected since we know if we have 350 * a Beaglebone Black it supports 1GHz. 351 */ 352 if (board_is_pb() || board_is_bone_lt()) 353 freq = MPUPLL_M_1000; 354 355 switch (freq) { 356 case MPUPLL_M_1000: 357 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 358 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 359 break; 360 case MPUPLL_M_800: 361 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 362 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 363 break; 364 case MPUPLL_M_720: 365 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; 366 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 367 break; 368 case MPUPLL_M_600: 369 case MPUPLL_M_500: 370 case MPUPLL_M_300: 371 default: 372 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; 373 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 374 break; 375 } 376 377 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 378 TPS65217_POWER_PATH, 379 usb_cur_lim, 380 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 381 puts("tps65217_reg_write failure\n"); 382 383 /* Set DCDC3 (CORE) voltage to 1.10V */ 384 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 385 TPS65217_DCDC_VOLT_SEL_1100MV)) { 386 puts("tps65217_voltage_update failure\n"); 387 return; 388 } 389 390 /* Set DCDC2 (MPU) voltage */ 391 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 392 puts("tps65217_voltage_update failure\n"); 393 return; 394 } 395 396 /* 397 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 398 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. 399 */ 400 if (board_is_bone()) { 401 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 402 TPS65217_DEFLS1, 403 TPS65217_LDO_VOLTAGE_OUT_3_3, 404 TPS65217_LDO_MASK)) 405 puts("tps65217_reg_write failure\n"); 406 } else { 407 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 408 TPS65217_DEFLS1, 409 TPS65217_LDO_VOLTAGE_OUT_1_8, 410 TPS65217_LDO_MASK)) 411 puts("tps65217_reg_write failure\n"); 412 } 413 414 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 415 TPS65217_DEFLS2, 416 TPS65217_LDO_VOLTAGE_OUT_3_3, 417 TPS65217_LDO_MASK)) 418 puts("tps65217_reg_write failure\n"); 419 } 420 421 void scale_vcores_generic(int freq) 422 { 423 int sil_rev, mpu_vdd; 424 425 /* 426 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 427 * MPU frequencies we support we use a CORE voltage of 428 * 1.10V. For MPU voltage we need to switch based on 429 * the frequency we are running at. 430 */ 431 #ifndef CONFIG_DM_I2C 432 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 433 return; 434 #else 435 if (power_tps65910_init(0)) 436 return; 437 #endif 438 /* 439 * Depending on MPU clock and PG we will need a different 440 * VDD to drive at that speed. 441 */ 442 sil_rev = readl(&cdev->deviceid) >> 28; 443 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); 444 445 /* Tell the TPS65910 to use i2c */ 446 tps65910_set_i2c_control(); 447 448 /* First update MPU voltage. */ 449 if (tps65910_voltage_update(MPU, mpu_vdd)) 450 return; 451 452 /* Second, update the CORE voltage. */ 453 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0)) 454 return; 455 456 } 457 458 void gpi2c_init(void) 459 { 460 /* When needed to be invoked prior to BSS initialization */ 461 static bool first_time = true; 462 463 if (first_time) { 464 enable_i2c0_pin_mux(); 465 #ifndef CONFIG_DM_I2C 466 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 467 CONFIG_SYS_OMAP24_I2C_SLAVE); 468 #endif 469 first_time = false; 470 } 471 } 472 473 void scale_vcores(void) 474 { 475 int freq; 476 477 gpi2c_init(); 478 freq = am335x_get_efuse_mpu_max_freq(cdev); 479 480 if (board_is_beaglebonex()) 481 scale_vcores_bone(freq); 482 else 483 scale_vcores_generic(freq); 484 } 485 486 void set_uart_mux_conf(void) 487 { 488 #if CONFIG_CONS_INDEX == 1 489 enable_uart0_pin_mux(); 490 #elif CONFIG_CONS_INDEX == 2 491 enable_uart1_pin_mux(); 492 #elif CONFIG_CONS_INDEX == 3 493 enable_uart2_pin_mux(); 494 #elif CONFIG_CONS_INDEX == 4 495 enable_uart3_pin_mux(); 496 #elif CONFIG_CONS_INDEX == 5 497 enable_uart4_pin_mux(); 498 #elif CONFIG_CONS_INDEX == 6 499 enable_uart5_pin_mux(); 500 #endif 501 } 502 503 void set_mux_conf_regs(void) 504 { 505 enable_board_pin_mux(); 506 } 507 508 const struct ctrl_ioregs ioregs_evmsk = { 509 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 510 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 511 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 512 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 513 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 514 }; 515 516 const struct ctrl_ioregs ioregs_bonelt = { 517 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 518 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 519 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 520 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 521 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 522 }; 523 524 const struct ctrl_ioregs ioregs_evm15 = { 525 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 526 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 527 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, 528 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 529 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 530 }; 531 532 const struct ctrl_ioregs ioregs = { 533 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 534 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 535 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 536 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 537 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 538 }; 539 540 void sdram_init(void) 541 { 542 if (board_is_evm_sk()) { 543 /* 544 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 545 * This is safe enough to do on older revs. 546 */ 547 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 548 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 549 } 550 551 if (board_is_icev2()) { 552 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); 553 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); 554 } 555 556 if (board_is_evm_sk()) 557 config_ddr(303, &ioregs_evmsk, &ddr3_data, 558 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 559 else if (board_is_pb() || board_is_bone_lt()) 560 config_ddr(400, &ioregs_bonelt, 561 &ddr3_beagleblack_data, 562 &ddr3_beagleblack_cmd_ctrl_data, 563 &ddr3_beagleblack_emif_reg_data, 0); 564 else if (board_is_evm_15_or_later()) 565 config_ddr(303, &ioregs_evm15, &ddr3_evm_data, 566 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 567 else if (board_is_icev2()) 568 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, 569 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 570 0); 571 else if (board_is_gp_evm()) 572 config_ddr(266, &ioregs, &ddr2_data, 573 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0); 574 else 575 config_ddr(266, &ioregs, &ddr2_data, 576 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 577 } 578 #endif 579 580 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ 581 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))) 582 static void request_and_set_gpio(int gpio, char *name, int val) 583 { 584 int ret; 585 586 ret = gpio_request(gpio, name); 587 if (ret < 0) { 588 printf("%s: Unable to request %s\n", __func__, name); 589 return; 590 } 591 592 ret = gpio_direction_output(gpio, 0); 593 if (ret < 0) { 594 printf("%s: Unable to set %s as output\n", __func__, name); 595 goto err_free_gpio; 596 } 597 598 gpio_set_value(gpio, val); 599 600 return; 601 602 err_free_gpio: 603 gpio_free(gpio); 604 } 605 606 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1); 607 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0); 608 609 /** 610 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock 611 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle 612 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to 613 * give 50MHz output for Eth0 and 1. 614 */ 615 static struct clk_synth cdce913_data = { 616 .id = 0x81, 617 .capacitor = 0x90, 618 .mux = 0x6d, 619 .pdiv2 = 0x2, 620 .pdiv3 = 0x2, 621 }; 622 #endif 623 624 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \ 625 defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) 626 627 #define MAX_CPSW_SLAVES 2 628 629 /* At the moment, we do not want to stop booting for any failures here */ 630 int ft_board_setup(void *fdt, bd_t *bd) 631 { 632 const char *slave_path, *enet_name; 633 int enetnode, slavenode, phynode; 634 struct udevice *ethdev; 635 char alias[16]; 636 u32 phy_id[2]; 637 int phy_addr; 638 int i, ret; 639 640 /* phy address fixup needed only on beagle bone family */ 641 if (!board_is_beaglebonex()) 642 goto done; 643 644 for (i = 0; i < MAX_CPSW_SLAVES; i++) { 645 sprintf(alias, "ethernet%d", i); 646 647 slave_path = fdt_get_alias(fdt, alias); 648 if (!slave_path) 649 continue; 650 651 slavenode = fdt_path_offset(fdt, slave_path); 652 if (slavenode < 0) 653 continue; 654 655 enetnode = fdt_parent_offset(fdt, slavenode); 656 enet_name = fdt_get_name(fdt, enetnode, NULL); 657 658 ethdev = eth_get_dev_by_name(enet_name); 659 if (!ethdev) 660 continue; 661 662 phy_addr = cpsw_get_slave_phy_addr(ethdev, i); 663 664 /* check for phy_id as well as phy-handle properties */ 665 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id", 666 phy_id, 2); 667 if (ret == 2) { 668 if (phy_id[1] != phy_addr) { 669 printf("fixing up phy_id for %s, old: %d, new: %d\n", 670 alias, phy_id[1], phy_addr); 671 672 phy_id[0] = cpu_to_fdt32(phy_id[0]); 673 phy_id[1] = cpu_to_fdt32(phy_addr); 674 do_fixup_by_path(fdt, slave_path, "phy_id", 675 phy_id, sizeof(phy_id), 0); 676 } 677 } else { 678 phynode = fdtdec_lookup_phandle(fdt, slavenode, 679 "phy-handle"); 680 if (phynode < 0) 681 continue; 682 683 ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT); 684 if (ret < 0) 685 continue; 686 687 if (ret != phy_addr) { 688 printf("fixing up phy-handle for %s, old: %d, new: %d\n", 689 alias, ret, phy_addr); 690 691 fdt_setprop_u32(fdt, phynode, "reg", 692 cpu_to_fdt32(phy_addr)); 693 } 694 } 695 } 696 697 done: 698 return 0; 699 } 700 #endif 701 702 /* 703 * Basic board specific setup. Pinmux has been handled already. 704 */ 705 int board_init(void) 706 { 707 #if defined(CONFIG_HW_WATCHDOG) 708 hw_watchdog_init(); 709 #endif 710 711 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 712 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 713 gpmc_init(); 714 #endif 715 716 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ 717 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))) 718 if (board_is_icev2()) { 719 int rv; 720 u32 reg; 721 722 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); 723 /* Make J19 status available on GPIO1_26 */ 724 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL); 725 726 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); 727 /* 728 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using 729 * jumpers near the port. Read the jumper value and set 730 * the pinmux, external mux and PHY clock accordingly. 731 * As jumper line is overridden by PHY RX_DV pin immediately 732 * after bootstrap (power-up/reset), we need to sample 733 * it during PHY reset using GPIO rising edge detection. 734 */ 735 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); 736 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */ 737 reg = readl(GPIO0_RISINGDETECT) | BIT(11); 738 writel(reg, GPIO0_RISINGDETECT); 739 reg = readl(GPIO1_RISINGDETECT) | BIT(26); 740 writel(reg, GPIO1_RISINGDETECT); 741 /* Reset PHYs to capture the Jumper setting */ 742 gpio_set_value(GPIO_PHY_RESET, 0); 743 udelay(2); /* PHY datasheet states 1uS min. */ 744 gpio_set_value(GPIO_PHY_RESET, 1); 745 746 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11); 747 if (reg) { 748 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */ 749 /* RMII mode */ 750 printf("ETH0, CPSW\n"); 751 } else { 752 /* MII mode */ 753 printf("ETH0, PRU\n"); 754 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ 755 } 756 757 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26); 758 if (reg) { 759 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */ 760 /* RMII mode */ 761 printf("ETH1, CPSW\n"); 762 gpio_set_value(GPIO_MUX_MII_CTRL, 1); 763 } else { 764 /* MII mode */ 765 printf("ETH1, PRU\n"); 766 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ 767 } 768 769 /* disable rising edge IRQs */ 770 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11); 771 writel(reg, GPIO0_RISINGDETECT); 772 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26); 773 writel(reg, GPIO1_RISINGDETECT); 774 775 rv = setup_clock_synthesizer(&cdce913_data); 776 if (rv) { 777 printf("Clock synthesizer setup failed %d\n", rv); 778 return rv; 779 } 780 781 /* reset PHYs */ 782 gpio_set_value(GPIO_PHY_RESET, 0); 783 udelay(2); /* PHY datasheet states 1uS min. */ 784 gpio_set_value(GPIO_PHY_RESET, 1); 785 } 786 #endif 787 788 return 0; 789 } 790 791 #ifdef CONFIG_BOARD_LATE_INIT 792 int board_late_init(void) 793 { 794 #if !defined(CONFIG_SPL_BUILD) 795 uint8_t mac_addr[6]; 796 uint32_t mac_hi, mac_lo; 797 #endif 798 799 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 800 char *name = NULL; 801 802 if (board_is_bone_lt()) { 803 /* BeagleBoard.org BeagleBone Black Wireless: */ 804 if (!strncmp(board_ti_get_rev(), "BWA", 3)) { 805 name = "BBBW"; 806 } 807 /* SeeedStudio BeagleBone Green Wireless */ 808 if (!strncmp(board_ti_get_rev(), "GW1", 3)) { 809 name = "BBGW"; 810 } 811 /* BeagleBoard.org BeagleBone Blue */ 812 if (!strncmp(board_ti_get_rev(), "BLA", 3)) { 813 name = "BBBL"; 814 } 815 } 816 817 if (board_is_bbg1()) 818 name = "BBG1"; 819 if (board_is_bben()) 820 name = "BBEN"; 821 set_board_info_env(name); 822 823 /* 824 * Default FIT boot on HS devices. Non FIT images are not allowed 825 * on HS devices. 826 */ 827 if (get_device_type() == HS_DEVICE) 828 env_set("boot_fit", "1"); 829 #endif 830 831 #if !defined(CONFIG_SPL_BUILD) 832 /* try reading mac address from efuse */ 833 mac_lo = readl(&cdev->macid0l); 834 mac_hi = readl(&cdev->macid0h); 835 mac_addr[0] = mac_hi & 0xFF; 836 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 837 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 838 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 839 mac_addr[4] = mac_lo & 0xFF; 840 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 841 842 if (!env_get("ethaddr")) { 843 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 844 845 if (is_valid_ethaddr(mac_addr)) 846 eth_env_set_enetaddr("ethaddr", mac_addr); 847 } 848 849 mac_lo = readl(&cdev->macid1l); 850 mac_hi = readl(&cdev->macid1h); 851 mac_addr[0] = mac_hi & 0xFF; 852 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 853 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 854 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 855 mac_addr[4] = mac_lo & 0xFF; 856 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 857 858 if (!env_get("eth1addr")) { 859 if (is_valid_ethaddr(mac_addr)) 860 eth_env_set_enetaddr("eth1addr", mac_addr); 861 } 862 #endif 863 864 if (!env_get("serial#")) { 865 char *board_serial = env_get("board_serial"); 866 char *ethaddr = env_get("ethaddr"); 867 868 if (!board_serial || !strncmp(board_serial, "unknown", 7)) 869 env_set("serial#", ethaddr); 870 else 871 env_set("serial#", board_serial); 872 } 873 874 return 0; 875 } 876 #endif 877 878 #ifndef CONFIG_DM_ETH 879 880 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 881 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 882 static void cpsw_control(int enabled) 883 { 884 /* VTP can be added here */ 885 886 return; 887 } 888 889 static struct cpsw_slave_data cpsw_slaves[] = { 890 { 891 .slave_reg_ofs = 0x208, 892 .sliver_reg_ofs = 0xd80, 893 .phy_addr = 0, 894 }, 895 { 896 .slave_reg_ofs = 0x308, 897 .sliver_reg_ofs = 0xdc0, 898 .phy_addr = 1, 899 }, 900 }; 901 902 static struct cpsw_platform_data cpsw_data = { 903 .mdio_base = CPSW_MDIO_BASE, 904 .cpsw_base = CPSW_BASE, 905 .mdio_div = 0xff, 906 .channels = 8, 907 .cpdma_reg_ofs = 0x800, 908 .slaves = 1, 909 .slave_data = cpsw_slaves, 910 .ale_reg_ofs = 0xd00, 911 .ale_entries = 1024, 912 .host_port_reg_ofs = 0x108, 913 .hw_stats_reg_ofs = 0x900, 914 .bd_ram_ofs = 0x2000, 915 .mac_control = (1 << 5), 916 .control = cpsw_control, 917 .host_port_num = 0, 918 .version = CPSW_CTRL_VERSION_2, 919 }; 920 #endif 921 922 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\ 923 defined(CONFIG_SPL_BUILD)) || \ 924 ((defined(CONFIG_DRIVER_TI_CPSW) || \ 925 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ 926 !defined(CONFIG_SPL_BUILD)) 927 928 /* 929 * This function will: 930 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr 931 * in the environment 932 * Perform fixups to the PHY present on certain boards. We only need this 933 * function in: 934 * - SPL with either CPSW or USB ethernet support 935 * - Full U-Boot, with either CPSW or USB ethernet 936 * Build in only these cases to avoid warnings about unused variables 937 * when we build an SPL that has neither option but full U-Boot will. 938 */ 939 int board_eth_init(bd_t *bis) 940 { 941 int rv, n = 0; 942 #if defined(CONFIG_USB_ETHER) && \ 943 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) 944 uint8_t mac_addr[6]; 945 uint32_t mac_hi, mac_lo; 946 947 /* 948 * use efuse mac address for USB ethernet as we know that 949 * both CPSW and USB ethernet will never be active at the same time 950 */ 951 mac_lo = readl(&cdev->macid0l); 952 mac_hi = readl(&cdev->macid0h); 953 mac_addr[0] = mac_hi & 0xFF; 954 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 955 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 956 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 957 mac_addr[4] = mac_lo & 0xFF; 958 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 959 #endif 960 961 962 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 963 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 964 965 #ifdef CONFIG_DRIVER_TI_CPSW 966 if (board_is_bone() || board_is_bone_lt() || board_is_bben() || 967 board_is_idk()) { 968 writel(MII_MODE_ENABLE, &cdev->miisel); 969 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 970 PHY_INTERFACE_MODE_MII; 971 } else if (board_is_icev2()) { 972 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 973 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 974 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; 975 cpsw_slaves[0].phy_addr = 1; 976 cpsw_slaves[1].phy_addr = 3; 977 } else { 978 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 979 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 980 PHY_INTERFACE_MODE_RGMII; 981 } 982 983 rv = cpsw_register(&cpsw_data); 984 if (rv < 0) 985 printf("Error %d registering CPSW switch\n", rv); 986 else 987 n += rv; 988 #endif 989 990 /* 991 * 992 * CPSW RGMII Internal Delay Mode is not supported in all PVT 993 * operating points. So we must set the TX clock delay feature 994 * in the AR8051 PHY. Since we only support a single ethernet 995 * device in U-Boot, we only do this for the first instance. 996 */ 997 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 998 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 999 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 1000 #define AR8051_RGMII_TX_CLK_DLY 0x100 1001 1002 if (board_is_evm_sk() || board_is_gp_evm() || board_is_bben()) { 1003 const char *devname; 1004 devname = miiphy_get_current_dev(); 1005 1006 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 1007 AR8051_DEBUG_RGMII_CLK_DLY_REG); 1008 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 1009 AR8051_RGMII_TX_CLK_DLY); 1010 } 1011 #endif 1012 #if defined(CONFIG_USB_ETHER) && \ 1013 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) 1014 if (is_valid_ethaddr(mac_addr)) 1015 eth_env_set_enetaddr("usbnet_devaddr", mac_addr); 1016 1017 rv = usb_eth_initialize(bis); 1018 if (rv < 0) 1019 printf("Error %d registering USB_ETHER\n", rv); 1020 else 1021 n += rv; 1022 #endif 1023 return n; 1024 } 1025 #endif 1026 1027 #endif /* CONFIG_DM_ETH */ 1028 1029 #ifdef CONFIG_SPL_LOAD_FIT 1030 int board_fit_config_name_match(const char *name) 1031 { 1032 if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) 1033 return 0; 1034 else if (board_is_bone() && !strcmp(name, "am335x-bone")) 1035 return 0; 1036 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) 1037 return 0; 1038 else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle")) 1039 return 0; 1040 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) 1041 return 0; 1042 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) 1043 return 0; 1044 else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) 1045 return 0; 1046 else 1047 return -1; 1048 } 1049 #endif 1050 1051 #ifdef CONFIG_TI_SECURE_DEVICE 1052 void board_fit_image_post_process(void **p_image, size_t *p_size) 1053 { 1054 secure_boot_verify_image(p_image, p_size); 1055 } 1056 #endif 1057 1058 #if !CONFIG_IS_ENABLED(OF_CONTROL) 1059 static const struct omap_hsmmc_plat am335x_mmc0_platdata = { 1060 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, 1061 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, 1062 .cfg.f_min = 400000, 1063 .cfg.f_max = 52000000, 1064 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, 1065 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 1066 }; 1067 1068 U_BOOT_DEVICE(am335x_mmc0) = { 1069 .name = "omap_hsmmc", 1070 .platdata = &am335x_mmc0_platdata, 1071 }; 1072 1073 static const struct omap_hsmmc_plat am335x_mmc1_platdata = { 1074 .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE, 1075 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT, 1076 .cfg.f_min = 400000, 1077 .cfg.f_max = 52000000, 1078 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, 1079 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 1080 }; 1081 1082 U_BOOT_DEVICE(am335x_mmc1) = { 1083 .name = "omap_hsmmc", 1084 .platdata = &am335x_mmc1_platdata, 1085 }; 1086 #endif 1087