1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <serial.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/clk_synthesizer.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/mem.h> 25 #include <asm/io.h> 26 #include <asm/emif.h> 27 #include <asm/gpio.h> 28 #include <asm/omap_sec_common.h> 29 #include <i2c.h> 30 #include <miiphy.h> 31 #include <cpsw.h> 32 #include <power/tps65217.h> 33 #include <power/tps65910.h> 34 #include <environment.h> 35 #include <watchdog.h> 36 #include <environment.h> 37 #include "../common/board_detect.h" 38 #include "board.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* GPIO that controls power to DDR on EVM-SK */ 43 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 44 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) 45 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) 46 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) 47 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) 48 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) 49 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) 50 51 #if defined(CONFIG_SPL_BUILD) || \ 52 (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) 53 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 54 #endif 55 56 /* 57 * Read header information from EEPROM into global structure. 58 */ 59 static inline int __maybe_unused read_eeprom(void) 60 { 61 return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR); 62 } 63 64 #ifndef CONFIG_DM_SERIAL 65 struct serial_device *default_serial_console(void) 66 { 67 if (board_is_icev2()) 68 return &eserial4_device; 69 else 70 return &eserial1_device; 71 } 72 #endif 73 74 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 75 static const struct ddr_data ddr2_data = { 76 .datardsratio0 = MT47H128M16RT25E_RD_DQS, 77 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, 78 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, 79 }; 80 81 static const struct cmd_control ddr2_cmd_ctrl_data = { 82 .cmd0csratio = MT47H128M16RT25E_RATIO, 83 84 .cmd1csratio = MT47H128M16RT25E_RATIO, 85 86 .cmd2csratio = MT47H128M16RT25E_RATIO, 87 }; 88 89 static const struct emif_regs ddr2_emif_reg_data = { 90 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 91 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 92 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 93 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 94 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 95 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 96 }; 97 98 static const struct ddr_data ddr3_data = { 99 .datardsratio0 = MT41J128MJT125_RD_DQS, 100 .datawdsratio0 = MT41J128MJT125_WR_DQS, 101 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 102 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 103 }; 104 105 static const struct ddr_data ddr3_beagleblack_data = { 106 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 107 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 108 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 109 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 110 }; 111 112 static const struct ddr_data ddr3_evm_data = { 113 .datardsratio0 = MT41J512M8RH125_RD_DQS, 114 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 115 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 116 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 117 }; 118 119 static const struct ddr_data ddr3_icev2_data = { 120 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, 121 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, 122 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, 123 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, 124 }; 125 126 static const struct cmd_control ddr3_cmd_ctrl_data = { 127 .cmd0csratio = MT41J128MJT125_RATIO, 128 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 129 130 .cmd1csratio = MT41J128MJT125_RATIO, 131 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 132 133 .cmd2csratio = MT41J128MJT125_RATIO, 134 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 135 }; 136 137 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 138 .cmd0csratio = MT41K256M16HA125E_RATIO, 139 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 140 141 .cmd1csratio = MT41K256M16HA125E_RATIO, 142 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 143 144 .cmd2csratio = MT41K256M16HA125E_RATIO, 145 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 146 }; 147 148 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 149 .cmd0csratio = MT41J512M8RH125_RATIO, 150 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 151 152 .cmd1csratio = MT41J512M8RH125_RATIO, 153 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 154 155 .cmd2csratio = MT41J512M8RH125_RATIO, 156 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 157 }; 158 159 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { 160 .cmd0csratio = MT41J128MJT125_RATIO_400MHz, 161 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 162 163 .cmd1csratio = MT41J128MJT125_RATIO_400MHz, 164 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 165 166 .cmd2csratio = MT41J128MJT125_RATIO_400MHz, 167 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 168 }; 169 170 static struct emif_regs ddr3_emif_reg_data = { 171 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 172 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 173 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 174 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 175 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 176 .zq_config = MT41J128MJT125_ZQ_CFG, 177 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 178 PHY_EN_DYN_PWRDN, 179 }; 180 181 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 182 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 183 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 184 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 185 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 186 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 187 .zq_config = MT41K256M16HA125E_ZQ_CFG, 188 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 189 }; 190 191 static struct emif_regs ddr3_evm_emif_reg_data = { 192 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 193 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 194 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 195 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 196 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 197 .zq_config = MT41J512M8RH125_ZQ_CFG, 198 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 199 PHY_EN_DYN_PWRDN, 200 }; 201 202 static struct emif_regs ddr3_icev2_emif_reg_data = { 203 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, 204 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, 205 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, 206 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, 207 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, 208 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, 209 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | 210 PHY_EN_DYN_PWRDN, 211 }; 212 213 #ifdef CONFIG_SPL_OS_BOOT 214 int spl_start_uboot(void) 215 { 216 /* break into full u-boot on 'c' */ 217 if (serial_tstc() && serial_getc() == 'c') 218 return 1; 219 220 #ifdef CONFIG_SPL_ENV_SUPPORT 221 env_init(); 222 env_relocate_spec(); 223 if (getenv_yesno("boot_os") != 1) 224 return 1; 225 #endif 226 227 return 0; 228 } 229 #endif 230 231 #define OSC (V_OSCK/1000000) 232 const struct dpll_params dpll_ddr = { 233 266, OSC-1, 1, -1, -1, -1, -1}; 234 const struct dpll_params dpll_ddr_evm_sk = { 235 303, OSC-1, 1, -1, -1, -1, -1}; 236 const struct dpll_params dpll_ddr_bone_black = { 237 400, OSC-1, 1, -1, -1, -1, -1}; 238 239 void am33xx_spl_board_init(void) 240 { 241 int mpu_vdd; 242 243 if (read_eeprom() < 0) 244 puts("Could not get board ID.\n"); 245 246 /* Get the frequency */ 247 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 248 249 if (board_is_bone() || board_is_bone_lt()) { 250 /* BeagleBone PMIC Code */ 251 int usb_cur_lim; 252 253 /* 254 * Only perform PMIC configurations if board rev > A1 255 * on Beaglebone White 256 */ 257 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) 258 return; 259 260 if (i2c_probe(TPS65217_CHIP_PM)) 261 return; 262 263 /* 264 * On Beaglebone White we need to ensure we have AC power 265 * before increasing the frequency. 266 */ 267 if (board_is_bone()) { 268 uchar pmic_status_reg; 269 if (tps65217_reg_read(TPS65217_STATUS, 270 &pmic_status_reg)) 271 return; 272 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 273 puts("No AC power, disabling frequency switch\n"); 274 return; 275 } 276 } 277 278 /* 279 * Override what we have detected since we know if we have 280 * a Beaglebone Black it supports 1GHz. 281 */ 282 if (board_is_bone_lt()) 283 dpll_mpu_opp100.m = MPUPLL_M_1000; 284 285 /* 286 * Increase USB current limit to 1300mA or 1800mA and set 287 * the MPU voltage controller as needed. 288 */ 289 if (dpll_mpu_opp100.m == MPUPLL_M_1000) { 290 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 291 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 292 } else { 293 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 294 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 295 } 296 297 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 298 TPS65217_POWER_PATH, 299 usb_cur_lim, 300 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 301 puts("tps65217_reg_write failure\n"); 302 303 /* Set DCDC3 (CORE) voltage to 1.125V */ 304 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 305 TPS65217_DCDC_VOLT_SEL_1125MV)) { 306 puts("tps65217_voltage_update failure\n"); 307 return; 308 } 309 310 /* Set CORE Frequencies to OPP100 */ 311 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 312 313 /* Set DCDC2 (MPU) voltage */ 314 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 315 puts("tps65217_voltage_update failure\n"); 316 return; 317 } 318 319 /* 320 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 321 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. 322 */ 323 if (board_is_bone()) { 324 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 325 TPS65217_DEFLS1, 326 TPS65217_LDO_VOLTAGE_OUT_3_3, 327 TPS65217_LDO_MASK)) 328 puts("tps65217_reg_write failure\n"); 329 } else { 330 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 331 TPS65217_DEFLS1, 332 TPS65217_LDO_VOLTAGE_OUT_1_8, 333 TPS65217_LDO_MASK)) 334 puts("tps65217_reg_write failure\n"); 335 } 336 337 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 338 TPS65217_DEFLS2, 339 TPS65217_LDO_VOLTAGE_OUT_3_3, 340 TPS65217_LDO_MASK)) 341 puts("tps65217_reg_write failure\n"); 342 } else { 343 int sil_rev; 344 345 /* 346 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 347 * MPU frequencies we support we use a CORE voltage of 348 * 1.1375V. For MPU voltage we need to switch based on 349 * the frequency we are running at. 350 */ 351 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 352 return; 353 354 /* 355 * Depending on MPU clock and PG we will need a different 356 * VDD to drive at that speed. 357 */ 358 sil_rev = readl(&cdev->deviceid) >> 28; 359 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, 360 dpll_mpu_opp100.m); 361 362 /* Tell the TPS65910 to use i2c */ 363 tps65910_set_i2c_control(); 364 365 /* First update MPU voltage. */ 366 if (tps65910_voltage_update(MPU, mpu_vdd)) 367 return; 368 369 /* Second, update the CORE voltage. */ 370 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) 371 return; 372 373 /* Set CORE Frequencies to OPP100 */ 374 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 375 } 376 377 /* Set MPU Frequency to what we detected now that voltages are set */ 378 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 379 } 380 381 const struct dpll_params *get_dpll_ddr_params(void) 382 { 383 enable_i2c0_pin_mux(); 384 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 385 if (read_eeprom() < 0) 386 puts("Could not get board ID.\n"); 387 388 if (board_is_evm_sk()) 389 return &dpll_ddr_evm_sk; 390 else if (board_is_bone_lt() || board_is_icev2()) 391 return &dpll_ddr_bone_black; 392 else if (board_is_evm_15_or_later()) 393 return &dpll_ddr_evm_sk; 394 else 395 return &dpll_ddr; 396 } 397 398 void set_uart_mux_conf(void) 399 { 400 #if CONFIG_CONS_INDEX == 1 401 enable_uart0_pin_mux(); 402 #elif CONFIG_CONS_INDEX == 2 403 enable_uart1_pin_mux(); 404 #elif CONFIG_CONS_INDEX == 3 405 enable_uart2_pin_mux(); 406 #elif CONFIG_CONS_INDEX == 4 407 enable_uart3_pin_mux(); 408 #elif CONFIG_CONS_INDEX == 5 409 enable_uart4_pin_mux(); 410 #elif CONFIG_CONS_INDEX == 6 411 enable_uart5_pin_mux(); 412 #endif 413 } 414 415 void set_mux_conf_regs(void) 416 { 417 if (read_eeprom() < 0) 418 puts("Could not get board ID.\n"); 419 420 enable_board_pin_mux(); 421 } 422 423 const struct ctrl_ioregs ioregs_evmsk = { 424 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 425 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 426 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 427 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 428 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 429 }; 430 431 const struct ctrl_ioregs ioregs_bonelt = { 432 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 433 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 434 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 435 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 436 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 437 }; 438 439 const struct ctrl_ioregs ioregs_evm15 = { 440 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 441 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 442 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, 443 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 444 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 445 }; 446 447 const struct ctrl_ioregs ioregs = { 448 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 449 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 450 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 451 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 452 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 453 }; 454 455 void sdram_init(void) 456 { 457 if (read_eeprom() < 0) 458 puts("Could not get board ID.\n"); 459 460 if (board_is_evm_sk()) { 461 /* 462 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 463 * This is safe enough to do on older revs. 464 */ 465 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 466 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 467 } 468 469 if (board_is_icev2()) { 470 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); 471 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); 472 } 473 474 if (board_is_evm_sk()) 475 config_ddr(303, &ioregs_evmsk, &ddr3_data, 476 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 477 else if (board_is_bone_lt()) 478 config_ddr(400, &ioregs_bonelt, 479 &ddr3_beagleblack_data, 480 &ddr3_beagleblack_cmd_ctrl_data, 481 &ddr3_beagleblack_emif_reg_data, 0); 482 else if (board_is_evm_15_or_later()) 483 config_ddr(303, &ioregs_evm15, &ddr3_evm_data, 484 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 485 else if (board_is_icev2()) 486 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, 487 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 488 0); 489 else 490 config_ddr(266, &ioregs, &ddr2_data, 491 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 492 } 493 #endif 494 495 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 496 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 497 static void request_and_set_gpio(int gpio, char *name) 498 { 499 int ret; 500 501 ret = gpio_request(gpio, name); 502 if (ret < 0) { 503 printf("%s: Unable to request %s\n", __func__, name); 504 return; 505 } 506 507 ret = gpio_direction_output(gpio, 0); 508 if (ret < 0) { 509 printf("%s: Unable to set %s as output\n", __func__, name); 510 goto err_free_gpio; 511 } 512 513 gpio_set_value(gpio, 1); 514 515 return; 516 517 err_free_gpio: 518 gpio_free(gpio); 519 } 520 521 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N); 522 523 /** 524 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock 525 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle 526 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to 527 * give 50MHz output for Eth0 and 1. 528 */ 529 static struct clk_synth cdce913_data = { 530 .id = 0x81, 531 .capacitor = 0x90, 532 .mux = 0x6d, 533 .pdiv2 = 0x2, 534 .pdiv3 = 0x2, 535 }; 536 #endif 537 538 /* 539 * Basic board specific setup. Pinmux has been handled already. 540 */ 541 int board_init(void) 542 { 543 #if defined(CONFIG_HW_WATCHDOG) 544 hw_watchdog_init(); 545 #endif 546 547 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 548 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 549 gpmc_init(); 550 #endif 551 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) 552 int rv; 553 554 if (board_is_icev2()) { 555 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); 556 REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL); 557 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); 558 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); 559 560 rv = setup_clock_synthesizer(&cdce913_data); 561 if (rv) { 562 printf("Clock synthesizer setup failed %d\n", rv); 563 return rv; 564 } 565 } 566 #endif 567 568 return 0; 569 } 570 571 #ifdef CONFIG_BOARD_LATE_INIT 572 int board_late_init(void) 573 { 574 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 575 int rc; 576 char *name = NULL; 577 578 rc = read_eeprom(); 579 if (rc) 580 puts("Could not get board ID.\n"); 581 582 if (board_is_bbg1()) 583 name = "BBG1"; 584 set_board_info_env(name); 585 #endif 586 587 return 0; 588 } 589 #endif 590 591 #ifndef CONFIG_DM_ETH 592 593 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 594 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 595 static void cpsw_control(int enabled) 596 { 597 /* VTP can be added here */ 598 599 return; 600 } 601 602 static struct cpsw_slave_data cpsw_slaves[] = { 603 { 604 .slave_reg_ofs = 0x208, 605 .sliver_reg_ofs = 0xd80, 606 .phy_addr = 0, 607 }, 608 { 609 .slave_reg_ofs = 0x308, 610 .sliver_reg_ofs = 0xdc0, 611 .phy_addr = 1, 612 }, 613 }; 614 615 static struct cpsw_platform_data cpsw_data = { 616 .mdio_base = CPSW_MDIO_BASE, 617 .cpsw_base = CPSW_BASE, 618 .mdio_div = 0xff, 619 .channels = 8, 620 .cpdma_reg_ofs = 0x800, 621 .slaves = 1, 622 .slave_data = cpsw_slaves, 623 .ale_reg_ofs = 0xd00, 624 .ale_entries = 1024, 625 .host_port_reg_ofs = 0x108, 626 .hw_stats_reg_ofs = 0x900, 627 .bd_ram_ofs = 0x2000, 628 .mac_control = (1 << 5), 629 .control = cpsw_control, 630 .host_port_num = 0, 631 .version = CPSW_CTRL_VERSION_2, 632 }; 633 #endif 634 635 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ 636 defined(CONFIG_SPL_BUILD)) || \ 637 ((defined(CONFIG_DRIVER_TI_CPSW) || \ 638 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ 639 !defined(CONFIG_SPL_BUILD)) 640 641 /* 642 * This function will: 643 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr 644 * in the environment 645 * Perform fixups to the PHY present on certain boards. We only need this 646 * function in: 647 * - SPL with either CPSW or USB ethernet support 648 * - Full U-Boot, with either CPSW or USB ethernet 649 * Build in only these cases to avoid warnings about unused variables 650 * when we build an SPL that has neither option but full U-Boot will. 651 */ 652 int board_eth_init(bd_t *bis) 653 { 654 int rv, n = 0; 655 uint8_t mac_addr[6]; 656 uint32_t mac_hi, mac_lo; 657 __maybe_unused struct ti_am_eeprom *header; 658 659 /* try reading mac address from efuse */ 660 mac_lo = readl(&cdev->macid0l); 661 mac_hi = readl(&cdev->macid0h); 662 mac_addr[0] = mac_hi & 0xFF; 663 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 664 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 665 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 666 mac_addr[4] = mac_lo & 0xFF; 667 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 668 669 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 670 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 671 if (!getenv("ethaddr")) { 672 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 673 674 if (is_valid_ethaddr(mac_addr)) 675 eth_setenv_enetaddr("ethaddr", mac_addr); 676 } 677 678 #ifdef CONFIG_DRIVER_TI_CPSW 679 680 mac_lo = readl(&cdev->macid1l); 681 mac_hi = readl(&cdev->macid1h); 682 mac_addr[0] = mac_hi & 0xFF; 683 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 684 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 685 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 686 mac_addr[4] = mac_lo & 0xFF; 687 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 688 689 if (!getenv("eth1addr")) { 690 if (is_valid_ethaddr(mac_addr)) 691 eth_setenv_enetaddr("eth1addr", mac_addr); 692 } 693 694 if (read_eeprom() < 0) 695 puts("Could not get board ID.\n"); 696 697 if (board_is_bone() || board_is_bone_lt() || 698 board_is_idk()) { 699 writel(MII_MODE_ENABLE, &cdev->miisel); 700 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 701 PHY_INTERFACE_MODE_MII; 702 } else if (board_is_icev2()) { 703 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 704 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 705 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; 706 cpsw_slaves[0].phy_addr = 1; 707 cpsw_slaves[1].phy_addr = 3; 708 } else { 709 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 710 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 711 PHY_INTERFACE_MODE_RGMII; 712 } 713 714 rv = cpsw_register(&cpsw_data); 715 if (rv < 0) 716 printf("Error %d registering CPSW switch\n", rv); 717 else 718 n += rv; 719 #endif 720 721 /* 722 * 723 * CPSW RGMII Internal Delay Mode is not supported in all PVT 724 * operating points. So we must set the TX clock delay feature 725 * in the AR8051 PHY. Since we only support a single ethernet 726 * device in U-Boot, we only do this for the first instance. 727 */ 728 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 729 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 730 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 731 #define AR8051_RGMII_TX_CLK_DLY 0x100 732 733 if (board_is_evm_sk() || board_is_gp_evm()) { 734 const char *devname; 735 devname = miiphy_get_current_dev(); 736 737 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 738 AR8051_DEBUG_RGMII_CLK_DLY_REG); 739 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 740 AR8051_RGMII_TX_CLK_DLY); 741 } 742 #endif 743 #if defined(CONFIG_USB_ETHER) && \ 744 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 745 if (is_valid_ethaddr(mac_addr)) 746 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 747 748 rv = usb_eth_initialize(bis); 749 if (rv < 0) 750 printf("Error %d registering USB_ETHER\n", rv); 751 else 752 n += rv; 753 #endif 754 return n; 755 } 756 #endif 757 758 #endif /* CONFIG_DM_ETH */ 759 760 #ifdef CONFIG_SPL_LOAD_FIT 761 int board_fit_config_name_match(const char *name) 762 { 763 if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) 764 return 0; 765 else if (board_is_bone() && !strcmp(name, "am335x-bone")) 766 return 0; 767 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) 768 return 0; 769 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) 770 return 0; 771 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) 772 return 0; 773 else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) 774 return 0; 775 else 776 return -1; 777 } 778 #endif 779 780 #ifdef CONFIG_TI_SECURE_DEVICE 781 void board_fit_image_post_process(void **p_image, size_t *p_size) 782 { 783 secure_boot_verify_image(p_image, p_size); 784 } 785 #endif 786