xref: /openbmc/u-boot/board/ti/am335x/board.c (revision ad560f87)
1 /*
2  * board.c
3  *
4  * Board functions for TI AM335X based boards
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #include <common.h>
12 #include <errno.h>
13 #include <spl.h>
14 #include <serial.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/clk_synthesizer.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/mem.h>
25 #include <asm/io.h>
26 #include <asm/emif.h>
27 #include <asm/gpio.h>
28 #include <asm/omap_sec_common.h>
29 #include <i2c.h>
30 #include <miiphy.h>
31 #include <cpsw.h>
32 #include <power/tps65217.h>
33 #include <power/tps65910.h>
34 #include <environment.h>
35 #include <watchdog.h>
36 #include <environment.h>
37 #include "../common/board_detect.h"
38 #include "board.h"
39 
40 DECLARE_GLOBAL_DATA_PTR;
41 
42 /* GPIO that controls power to DDR on EVM-SK */
43 #define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
44 #define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
45 #define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
46 #define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
47 #define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
48 #define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
49 #define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
50 #define GPIO_ETH0_MODE		GPIO_TO_PIN(0, 11)
51 #define GPIO_ETH1_MODE		GPIO_TO_PIN(1, 26)
52 
53 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
54 
55 #define GPIO0_RISINGDETECT	(AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
56 #define GPIO1_RISINGDETECT	(AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
57 
58 #define GPIO0_IRQSTATUS1	(AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
59 #define GPIO1_IRQSTATUS1	(AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
60 
61 #define GPIO0_IRQSTATUSRAW	(AM33XX_GPIO0_BASE + 0x024)
62 #define GPIO1_IRQSTATUSRAW	(AM33XX_GPIO1_BASE + 0x024)
63 
64 /*
65  * Read header information from EEPROM into global structure.
66  */
67 static inline int __maybe_unused read_eeprom(void)
68 {
69 	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
70 }
71 
72 #ifndef CONFIG_DM_SERIAL
73 struct serial_device *default_serial_console(void)
74 {
75 	if (board_is_icev2())
76 		return &eserial4_device;
77 	else
78 		return &eserial1_device;
79 }
80 #endif
81 
82 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
83 static const struct ddr_data ddr2_data = {
84 	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
85 	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
86 	.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
87 };
88 
89 static const struct cmd_control ddr2_cmd_ctrl_data = {
90 	.cmd0csratio = MT47H128M16RT25E_RATIO,
91 
92 	.cmd1csratio = MT47H128M16RT25E_RATIO,
93 
94 	.cmd2csratio = MT47H128M16RT25E_RATIO,
95 };
96 
97 static const struct emif_regs ddr2_emif_reg_data = {
98 	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
99 	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
100 	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
101 	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
102 	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
103 	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
104 };
105 
106 static const struct ddr_data ddr3_data = {
107 	.datardsratio0 = MT41J128MJT125_RD_DQS,
108 	.datawdsratio0 = MT41J128MJT125_WR_DQS,
109 	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
110 	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
111 };
112 
113 static const struct ddr_data ddr3_beagleblack_data = {
114 	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
115 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
116 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
117 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
118 };
119 
120 static const struct ddr_data ddr3_evm_data = {
121 	.datardsratio0 = MT41J512M8RH125_RD_DQS,
122 	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
123 	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
124 	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
125 };
126 
127 static const struct ddr_data ddr3_icev2_data = {
128 	.datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
129 	.datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
130 	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
131 	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
132 };
133 
134 static const struct cmd_control ddr3_cmd_ctrl_data = {
135 	.cmd0csratio = MT41J128MJT125_RATIO,
136 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
137 
138 	.cmd1csratio = MT41J128MJT125_RATIO,
139 	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
140 
141 	.cmd2csratio = MT41J128MJT125_RATIO,
142 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
143 };
144 
145 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
146 	.cmd0csratio = MT41K256M16HA125E_RATIO,
147 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
148 
149 	.cmd1csratio = MT41K256M16HA125E_RATIO,
150 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
151 
152 	.cmd2csratio = MT41K256M16HA125E_RATIO,
153 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
154 };
155 
156 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
157 	.cmd0csratio = MT41J512M8RH125_RATIO,
158 	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
159 
160 	.cmd1csratio = MT41J512M8RH125_RATIO,
161 	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
162 
163 	.cmd2csratio = MT41J512M8RH125_RATIO,
164 	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
165 };
166 
167 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
168 	.cmd0csratio = MT41J128MJT125_RATIO_400MHz,
169 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
170 
171 	.cmd1csratio = MT41J128MJT125_RATIO_400MHz,
172 	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
173 
174 	.cmd2csratio = MT41J128MJT125_RATIO_400MHz,
175 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
176 };
177 
178 static struct emif_regs ddr3_emif_reg_data = {
179 	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
180 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
181 	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
182 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
183 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
184 	.zq_config = MT41J128MJT125_ZQ_CFG,
185 	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
186 				PHY_EN_DYN_PWRDN,
187 };
188 
189 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
190 	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
191 	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
192 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
193 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
194 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
195 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
196 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
197 };
198 
199 static struct emif_regs ddr3_evm_emif_reg_data = {
200 	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
201 	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
202 	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
203 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
204 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
205 	.zq_config = MT41J512M8RH125_ZQ_CFG,
206 	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
207 				PHY_EN_DYN_PWRDN,
208 };
209 
210 static struct emif_regs ddr3_icev2_emif_reg_data = {
211 	.sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
212 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
213 	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
214 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
215 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
216 	.zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
217 	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
218 				PHY_EN_DYN_PWRDN,
219 };
220 
221 #ifdef CONFIG_SPL_OS_BOOT
222 int spl_start_uboot(void)
223 {
224 	/* break into full u-boot on 'c' */
225 	if (serial_tstc() && serial_getc() == 'c')
226 		return 1;
227 
228 #ifdef CONFIG_SPL_ENV_SUPPORT
229 	env_init();
230 	env_relocate_spec();
231 	if (getenv_yesno("boot_os") != 1)
232 		return 1;
233 #endif
234 
235 	return 0;
236 }
237 #endif
238 
239 #define OSC	(V_OSCK/1000000)
240 const struct dpll_params dpll_ddr = {
241 		266, OSC-1, 1, -1, -1, -1, -1};
242 const struct dpll_params dpll_ddr_evm_sk = {
243 		303, OSC-1, 1, -1, -1, -1, -1};
244 const struct dpll_params dpll_ddr_bone_black = {
245 		400, OSC-1, 1, -1, -1, -1, -1};
246 
247 void am33xx_spl_board_init(void)
248 {
249 	int mpu_vdd;
250 
251 	if (read_eeprom() < 0)
252 		puts("Could not get board ID.\n");
253 
254 	/* Get the frequency */
255 	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
256 
257 	if (board_is_bone() || board_is_bone_lt()) {
258 		/* BeagleBone PMIC Code */
259 		int usb_cur_lim;
260 
261 		/*
262 		 * Only perform PMIC configurations if board rev > A1
263 		 * on Beaglebone White
264 		 */
265 		if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
266 			return;
267 
268 		if (i2c_probe(TPS65217_CHIP_PM))
269 			return;
270 
271 		/*
272 		 * On Beaglebone White we need to ensure we have AC power
273 		 * before increasing the frequency.
274 		 */
275 		if (board_is_bone()) {
276 			uchar pmic_status_reg;
277 			if (tps65217_reg_read(TPS65217_STATUS,
278 					      &pmic_status_reg))
279 				return;
280 			if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
281 				puts("No AC power, disabling frequency switch\n");
282 				return;
283 			}
284 		}
285 
286 		/*
287 		 * Override what we have detected since we know if we have
288 		 * a Beaglebone Black it supports 1GHz.
289 		 */
290 		if (board_is_bone_lt())
291 			dpll_mpu_opp100.m = MPUPLL_M_1000;
292 
293 		/*
294 		 * Increase USB current limit to 1300mA or 1800mA and set
295 		 * the MPU voltage controller as needed.
296 		 */
297 		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
298 			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
299 			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
300 		} else {
301 			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
302 			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
303 		}
304 
305 		if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
306 				       TPS65217_POWER_PATH,
307 				       usb_cur_lim,
308 				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
309 			puts("tps65217_reg_write failure\n");
310 
311 		/* Set DCDC3 (CORE) voltage to 1.125V */
312 		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
313 					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
314 			puts("tps65217_voltage_update failure\n");
315 			return;
316 		}
317 
318 		/* Set CORE Frequencies to OPP100 */
319 		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
320 
321 		/* Set DCDC2 (MPU) voltage */
322 		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
323 			puts("tps65217_voltage_update failure\n");
324 			return;
325 		}
326 
327 		/*
328 		 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
329 		 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
330 		 */
331 		if (board_is_bone()) {
332 			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
333 					       TPS65217_DEFLS1,
334 					       TPS65217_LDO_VOLTAGE_OUT_3_3,
335 					       TPS65217_LDO_MASK))
336 				puts("tps65217_reg_write failure\n");
337 		} else {
338 			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
339 					       TPS65217_DEFLS1,
340 					       TPS65217_LDO_VOLTAGE_OUT_1_8,
341 					       TPS65217_LDO_MASK))
342 				puts("tps65217_reg_write failure\n");
343 		}
344 
345 		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
346 				       TPS65217_DEFLS2,
347 				       TPS65217_LDO_VOLTAGE_OUT_3_3,
348 				       TPS65217_LDO_MASK))
349 			puts("tps65217_reg_write failure\n");
350 	} else {
351 		int sil_rev;
352 
353 		/*
354 		 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
355 		 * MPU frequencies we support we use a CORE voltage of
356 		 * 1.1375V.  For MPU voltage we need to switch based on
357 		 * the frequency we are running at.
358 		 */
359 		if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
360 			return;
361 
362 		/*
363 		 * Depending on MPU clock and PG we will need a different
364 		 * VDD to drive at that speed.
365 		 */
366 		sil_rev = readl(&cdev->deviceid) >> 28;
367 		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
368 						      dpll_mpu_opp100.m);
369 
370 		/* Tell the TPS65910 to use i2c */
371 		tps65910_set_i2c_control();
372 
373 		/* First update MPU voltage. */
374 		if (tps65910_voltage_update(MPU, mpu_vdd))
375 			return;
376 
377 		/* Second, update the CORE voltage. */
378 		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
379 			return;
380 
381 		/* Set CORE Frequencies to OPP100 */
382 		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
383 	}
384 
385 	/* Set MPU Frequency to what we detected now that voltages are set */
386 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
387 }
388 
389 const struct dpll_params *get_dpll_ddr_params(void)
390 {
391 	enable_i2c0_pin_mux();
392 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
393 	if (read_eeprom() < 0)
394 		puts("Could not get board ID.\n");
395 
396 	if (board_is_evm_sk())
397 		return &dpll_ddr_evm_sk;
398 	else if (board_is_bone_lt() || board_is_icev2())
399 		return &dpll_ddr_bone_black;
400 	else if (board_is_evm_15_or_later())
401 		return &dpll_ddr_evm_sk;
402 	else
403 		return &dpll_ddr;
404 }
405 
406 void set_uart_mux_conf(void)
407 {
408 #if CONFIG_CONS_INDEX == 1
409 	enable_uart0_pin_mux();
410 #elif CONFIG_CONS_INDEX == 2
411 	enable_uart1_pin_mux();
412 #elif CONFIG_CONS_INDEX == 3
413 	enable_uart2_pin_mux();
414 #elif CONFIG_CONS_INDEX == 4
415 	enable_uart3_pin_mux();
416 #elif CONFIG_CONS_INDEX == 5
417 	enable_uart4_pin_mux();
418 #elif CONFIG_CONS_INDEX == 6
419 	enable_uart5_pin_mux();
420 #endif
421 }
422 
423 void set_mux_conf_regs(void)
424 {
425 	if (read_eeprom() < 0)
426 		puts("Could not get board ID.\n");
427 
428 	enable_board_pin_mux();
429 }
430 
431 const struct ctrl_ioregs ioregs_evmsk = {
432 	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
433 	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
434 	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
435 	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
436 	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
437 };
438 
439 const struct ctrl_ioregs ioregs_bonelt = {
440 	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
441 	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
442 	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
443 	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
444 	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
445 };
446 
447 const struct ctrl_ioregs ioregs_evm15 = {
448 	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
449 	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
450 	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
451 	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
452 	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
453 };
454 
455 const struct ctrl_ioregs ioregs = {
456 	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
457 	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
458 	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
459 	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
460 	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
461 };
462 
463 void sdram_init(void)
464 {
465 	if (read_eeprom() < 0)
466 		puts("Could not get board ID.\n");
467 
468 	if (board_is_evm_sk()) {
469 		/*
470 		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
471 		 * This is safe enough to do on older revs.
472 		 */
473 		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
474 		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
475 	}
476 
477 	if (board_is_icev2()) {
478 		gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
479 		gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
480 	}
481 
482 	if (board_is_evm_sk())
483 		config_ddr(303, &ioregs_evmsk, &ddr3_data,
484 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
485 	else if (board_is_bone_lt())
486 		config_ddr(400, &ioregs_bonelt,
487 			   &ddr3_beagleblack_data,
488 			   &ddr3_beagleblack_cmd_ctrl_data,
489 			   &ddr3_beagleblack_emif_reg_data, 0);
490 	else if (board_is_evm_15_or_later())
491 		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
492 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
493 	else if (board_is_icev2())
494 		config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
495 			   &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
496 			   0);
497 	else
498 		config_ddr(266, &ioregs, &ddr2_data,
499 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
500 }
501 #endif
502 
503 #if !defined(CONFIG_SPL_BUILD) || \
504 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
505 static void request_and_set_gpio(int gpio, char *name, int val)
506 {
507 	int ret;
508 
509 	ret = gpio_request(gpio, name);
510 	if (ret < 0) {
511 		printf("%s: Unable to request %s\n", __func__, name);
512 		return;
513 	}
514 
515 	ret = gpio_direction_output(gpio, 0);
516 	if (ret < 0) {
517 		printf("%s: Unable to set %s  as output\n", __func__, name);
518 		goto err_free_gpio;
519 	}
520 
521 	gpio_set_value(gpio, val);
522 
523 	return;
524 
525 err_free_gpio:
526 	gpio_free(gpio);
527 }
528 
529 #define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
530 #define REQUEST_AND_CLR_GPIO(N)	request_and_set_gpio(N, #N, 0);
531 
532 /**
533  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
534  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
535  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
536  * give 50MHz output for Eth0 and 1.
537  */
538 static struct clk_synth cdce913_data = {
539 	.id = 0x81,
540 	.capacitor = 0x90,
541 	.mux = 0x6d,
542 	.pdiv2 = 0x2,
543 	.pdiv3 = 0x2,
544 };
545 #endif
546 
547 /*
548  * Basic board specific setup.  Pinmux has been handled already.
549  */
550 int board_init(void)
551 {
552 #if defined(CONFIG_HW_WATCHDOG)
553 	hw_watchdog_init();
554 #endif
555 
556 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
557 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
558 	gpmc_init();
559 #endif
560 
561 #if !defined(CONFIG_SPL_BUILD) || \
562 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
563 	if (board_is_icev2()) {
564 		int rv;
565 		u32 reg;
566 
567 		REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
568 		/* Make J19 status available on GPIO1_26 */
569 		REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
570 
571 		REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
572 		/*
573 		 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
574 		 * jumpers near the port. Read the jumper value and set
575 		 * the pinmux, external mux and PHY clock accordingly.
576 		 * As jumper line is overridden by PHY RX_DV pin immediately
577 		 * after bootstrap (power-up/reset), we need to sample
578 		 * it during PHY reset using GPIO rising edge detection.
579 		 */
580 		REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
581 		/* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
582 		reg = readl(GPIO0_RISINGDETECT) | BIT(11);
583 		writel(reg, GPIO0_RISINGDETECT);
584 		reg = readl(GPIO1_RISINGDETECT) | BIT(26);
585 		writel(reg, GPIO1_RISINGDETECT);
586 		/* Reset PHYs to capture the Jumper setting */
587 		gpio_set_value(GPIO_PHY_RESET, 0);
588 		udelay(2);	/* PHY datasheet states 1uS min. */
589 		gpio_set_value(GPIO_PHY_RESET, 1);
590 
591 		reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
592 		if (reg) {
593 			writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
594 			/* RMII mode */
595 			printf("ETH0, CPSW\n");
596 		} else {
597 			/* MII mode */
598 			printf("ETH0, PRU\n");
599 			cdce913_data.pdiv3 = 4;	/* 25MHz PHY clk */
600 		}
601 
602 		reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
603 		if (reg) {
604 			writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
605 			/* RMII mode */
606 			printf("ETH1, CPSW\n");
607 			gpio_set_value(GPIO_MUX_MII_CTRL, 1);
608 		} else {
609 			/* MII mode */
610 			printf("ETH1, PRU\n");
611 			cdce913_data.pdiv2 = 4;	/* 25MHz PHY clk */
612 		}
613 
614 		/* disable rising edge IRQs */
615 		reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
616 		writel(reg, GPIO0_RISINGDETECT);
617 		reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
618 		writel(reg, GPIO1_RISINGDETECT);
619 
620 		rv = setup_clock_synthesizer(&cdce913_data);
621 		if (rv) {
622 			printf("Clock synthesizer setup failed %d\n", rv);
623 			return rv;
624 		}
625 
626 		/* reset PHYs */
627 		gpio_set_value(GPIO_PHY_RESET, 0);
628 		udelay(2);	/* PHY datasheet states 1uS min. */
629 		gpio_set_value(GPIO_PHY_RESET, 1);
630 	}
631 #endif
632 
633 	return 0;
634 }
635 
636 #ifdef CONFIG_BOARD_LATE_INIT
637 int board_late_init(void)
638 {
639 #if !defined(CONFIG_SPL_BUILD)
640 	uint8_t mac_addr[6];
641 	uint32_t mac_hi, mac_lo;
642 #endif
643 
644 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
645 	int rc;
646 	char *name = NULL;
647 
648 	rc = read_eeprom();
649 	if (rc)
650 		puts("Could not get board ID.\n");
651 
652 	if (board_is_bbg1())
653 		name = "BBG1";
654 	set_board_info_env(name);
655 #endif
656 
657 #if !defined(CONFIG_SPL_BUILD)
658 	/* try reading mac address from efuse */
659 	mac_lo = readl(&cdev->macid0l);
660 	mac_hi = readl(&cdev->macid0h);
661 	mac_addr[0] = mac_hi & 0xFF;
662 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
663 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
664 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
665 	mac_addr[4] = mac_lo & 0xFF;
666 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
667 
668 	if (!getenv("ethaddr")) {
669 		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
670 
671 		if (is_valid_ethaddr(mac_addr))
672 			eth_setenv_enetaddr("ethaddr", mac_addr);
673 	}
674 
675 	mac_lo = readl(&cdev->macid1l);
676 	mac_hi = readl(&cdev->macid1h);
677 	mac_addr[0] = mac_hi & 0xFF;
678 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
679 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
680 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
681 	mac_addr[4] = mac_lo & 0xFF;
682 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
683 
684 	if (!getenv("eth1addr")) {
685 		if (is_valid_ethaddr(mac_addr))
686 			eth_setenv_enetaddr("eth1addr", mac_addr);
687 	}
688 #endif
689 
690 	return 0;
691 }
692 #endif
693 
694 #ifndef CONFIG_DM_ETH
695 
696 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
697 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
698 static void cpsw_control(int enabled)
699 {
700 	/* VTP can be added here */
701 
702 	return;
703 }
704 
705 static struct cpsw_slave_data cpsw_slaves[] = {
706 	{
707 		.slave_reg_ofs	= 0x208,
708 		.sliver_reg_ofs	= 0xd80,
709 		.phy_addr	= 0,
710 	},
711 	{
712 		.slave_reg_ofs	= 0x308,
713 		.sliver_reg_ofs	= 0xdc0,
714 		.phy_addr	= 1,
715 	},
716 };
717 
718 static struct cpsw_platform_data cpsw_data = {
719 	.mdio_base		= CPSW_MDIO_BASE,
720 	.cpsw_base		= CPSW_BASE,
721 	.mdio_div		= 0xff,
722 	.channels		= 8,
723 	.cpdma_reg_ofs		= 0x800,
724 	.slaves			= 1,
725 	.slave_data		= cpsw_slaves,
726 	.ale_reg_ofs		= 0xd00,
727 	.ale_entries		= 1024,
728 	.host_port_reg_ofs	= 0x108,
729 	.hw_stats_reg_ofs	= 0x900,
730 	.bd_ram_ofs		= 0x2000,
731 	.mac_control		= (1 << 5),
732 	.control		= cpsw_control,
733 	.host_port_num		= 0,
734 	.version		= CPSW_CTRL_VERSION_2,
735 };
736 #endif
737 
738 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
739 	defined(CONFIG_SPL_BUILD)) || \
740 	((defined(CONFIG_DRIVER_TI_CPSW) || \
741 	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
742 	 !defined(CONFIG_SPL_BUILD))
743 
744 /*
745  * This function will:
746  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
747  * in the environment
748  * Perform fixups to the PHY present on certain boards.  We only need this
749  * function in:
750  * - SPL with either CPSW or USB ethernet support
751  * - Full U-Boot, with either CPSW or USB ethernet
752  * Build in only these cases to avoid warnings about unused variables
753  * when we build an SPL that has neither option but full U-Boot will.
754  */
755 int board_eth_init(bd_t *bis)
756 {
757 	int rv, n = 0;
758 #if defined(CONFIG_USB_ETHER) && \
759 	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
760 	uint8_t mac_addr[6];
761 	uint32_t mac_hi, mac_lo;
762 
763 	/*
764 	 * use efuse mac address for USB ethernet as we know that
765 	 * both CPSW and USB ethernet will never be active at the same time
766 	 */
767 	mac_lo = readl(&cdev->macid0l);
768 	mac_hi = readl(&cdev->macid0h);
769 	mac_addr[0] = mac_hi & 0xFF;
770 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
771 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
772 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
773 	mac_addr[4] = mac_lo & 0xFF;
774 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
775 #endif
776 
777 
778 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
779 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
780 
781 #ifdef CONFIG_DRIVER_TI_CPSW
782 	if (read_eeprom() < 0)
783 		puts("Could not get board ID.\n");
784 
785 	if (board_is_bone() || board_is_bone_lt() ||
786 	    board_is_idk()) {
787 		writel(MII_MODE_ENABLE, &cdev->miisel);
788 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
789 				PHY_INTERFACE_MODE_MII;
790 	} else if (board_is_icev2()) {
791 		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
792 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
793 		cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
794 		cpsw_slaves[0].phy_addr = 1;
795 		cpsw_slaves[1].phy_addr = 3;
796 	} else {
797 		writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
798 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
799 				PHY_INTERFACE_MODE_RGMII;
800 	}
801 
802 	rv = cpsw_register(&cpsw_data);
803 	if (rv < 0)
804 		printf("Error %d registering CPSW switch\n", rv);
805 	else
806 		n += rv;
807 #endif
808 
809 	/*
810 	 *
811 	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
812 	 * operating points.  So we must set the TX clock delay feature
813 	 * in the AR8051 PHY.  Since we only support a single ethernet
814 	 * device in U-Boot, we only do this for the first instance.
815 	 */
816 #define AR8051_PHY_DEBUG_ADDR_REG	0x1d
817 #define AR8051_PHY_DEBUG_DATA_REG	0x1e
818 #define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
819 #define AR8051_RGMII_TX_CLK_DLY		0x100
820 
821 	if (board_is_evm_sk() || board_is_gp_evm()) {
822 		const char *devname;
823 		devname = miiphy_get_current_dev();
824 
825 		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
826 				AR8051_DEBUG_RGMII_CLK_DLY_REG);
827 		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
828 				AR8051_RGMII_TX_CLK_DLY);
829 	}
830 #endif
831 #if defined(CONFIG_USB_ETHER) && \
832 	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
833 	if (is_valid_ethaddr(mac_addr))
834 		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
835 
836 	rv = usb_eth_initialize(bis);
837 	if (rv < 0)
838 		printf("Error %d registering USB_ETHER\n", rv);
839 	else
840 		n += rv;
841 #endif
842 	return n;
843 }
844 #endif
845 
846 #endif /* CONFIG_DM_ETH */
847 
848 #ifdef CONFIG_SPL_LOAD_FIT
849 int board_fit_config_name_match(const char *name)
850 {
851 	if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
852 		return 0;
853 	else if (board_is_bone() && !strcmp(name, "am335x-bone"))
854 		return 0;
855 	else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
856 		return 0;
857 	else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
858 		return 0;
859 	else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
860 		return 0;
861 	else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
862 		return 0;
863 	else
864 		return -1;
865 }
866 #endif
867 
868 #ifdef CONFIG_TI_SECURE_DEVICE
869 void board_fit_image_post_process(void **p_image, size_t *p_size)
870 {
871 	secure_boot_verify_image(p_image, p_size);
872 }
873 #endif
874