1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/omap.h> 17 #include <asm/arch/ddr_defs.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/mmc_host_def.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mem.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <cpsw.h> 29 #include <power/tps65217.h> 30 #include <power/tps65910.h> 31 #include <environment.h> 32 #include <watchdog.h> 33 #include "board.h" 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 /* GPIO that controls power to DDR on EVM-SK */ 38 #define GPIO_DDR_VTT_EN 7 39 40 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 41 42 /* 43 * Read header information from EEPROM into global structure. 44 */ 45 static int read_eeprom(struct am335x_baseboard_id *header) 46 { 47 /* Check if baseboard eeprom is available */ 48 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 49 puts("Could not probe the EEPROM; something fundamentally " 50 "wrong on the I2C bus.\n"); 51 return -ENODEV; 52 } 53 54 /* read the eeprom using i2c */ 55 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 56 sizeof(struct am335x_baseboard_id))) { 57 puts("Could not read the EEPROM; something fundamentally" 58 " wrong on the I2C bus.\n"); 59 return -EIO; 60 } 61 62 if (header->magic != 0xEE3355AA) { 63 /* 64 * read the eeprom using i2c again, 65 * but use only a 1 byte address 66 */ 67 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 68 sizeof(struct am335x_baseboard_id))) { 69 puts("Could not read the EEPROM; something " 70 "fundamentally wrong on the I2C bus.\n"); 71 return -EIO; 72 } 73 74 if (header->magic != 0xEE3355AA) { 75 printf("Incorrect magic number (0x%x) in EEPROM\n", 76 header->magic); 77 return -EINVAL; 78 } 79 } 80 81 return 0; 82 } 83 84 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) 85 static const struct ddr_data ddr2_data = { 86 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 87 (MT47H128M16RT25E_RD_DQS<<20) | 88 (MT47H128M16RT25E_RD_DQS<<10) | 89 (MT47H128M16RT25E_RD_DQS<<0)), 90 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 91 (MT47H128M16RT25E_WR_DQS<<20) | 92 (MT47H128M16RT25E_WR_DQS<<10) | 93 (MT47H128M16RT25E_WR_DQS<<0)), 94 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 95 (MT47H128M16RT25E_PHY_WRLVL<<20) | 96 (MT47H128M16RT25E_PHY_WRLVL<<10) | 97 (MT47H128M16RT25E_PHY_WRLVL<<0)), 98 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 99 (MT47H128M16RT25E_PHY_GATELVL<<20) | 100 (MT47H128M16RT25E_PHY_GATELVL<<10) | 101 (MT47H128M16RT25E_PHY_GATELVL<<0)), 102 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 103 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 104 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 105 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 106 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 107 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 108 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 109 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 110 }; 111 112 static const struct cmd_control ddr2_cmd_ctrl_data = { 113 .cmd0csratio = MT47H128M16RT25E_RATIO, 114 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 115 116 .cmd1csratio = MT47H128M16RT25E_RATIO, 117 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 118 119 .cmd2csratio = MT47H128M16RT25E_RATIO, 120 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 121 }; 122 123 static const struct emif_regs ddr2_emif_reg_data = { 124 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 125 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 126 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 127 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 128 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 129 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 130 }; 131 132 static const struct ddr_data ddr3_data = { 133 .datardsratio0 = MT41J128MJT125_RD_DQS, 134 .datawdsratio0 = MT41J128MJT125_WR_DQS, 135 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 136 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 137 }; 138 139 static const struct ddr_data ddr3_beagleblack_data = { 140 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 141 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 142 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 143 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 144 }; 145 146 static const struct ddr_data ddr3_evm_data = { 147 .datardsratio0 = MT41J512M8RH125_RD_DQS, 148 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 149 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 150 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 151 }; 152 153 static const struct cmd_control ddr3_cmd_ctrl_data = { 154 .cmd0csratio = MT41J128MJT125_RATIO, 155 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 156 157 .cmd1csratio = MT41J128MJT125_RATIO, 158 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 159 160 .cmd2csratio = MT41J128MJT125_RATIO, 161 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 162 }; 163 164 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 165 .cmd0csratio = MT41K256M16HA125E_RATIO, 166 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 167 168 .cmd1csratio = MT41K256M16HA125E_RATIO, 169 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 170 171 .cmd2csratio = MT41K256M16HA125E_RATIO, 172 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 173 }; 174 175 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 176 .cmd0csratio = MT41J512M8RH125_RATIO, 177 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 178 179 .cmd1csratio = MT41J512M8RH125_RATIO, 180 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 181 182 .cmd2csratio = MT41J512M8RH125_RATIO, 183 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 184 }; 185 186 static struct emif_regs ddr3_emif_reg_data = { 187 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 188 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 189 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 190 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 191 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 192 .zq_config = MT41J128MJT125_ZQ_CFG, 193 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 194 PHY_EN_DYN_PWRDN, 195 }; 196 197 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 198 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 199 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 200 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 201 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 202 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 203 .zq_config = MT41K256M16HA125E_ZQ_CFG, 204 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 205 }; 206 207 static struct emif_regs ddr3_evm_emif_reg_data = { 208 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 209 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 210 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 211 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 212 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 213 .zq_config = MT41J512M8RH125_ZQ_CFG, 214 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 215 PHY_EN_DYN_PWRDN, 216 }; 217 218 #ifdef CONFIG_SPL_OS_BOOT 219 int spl_start_uboot(void) 220 { 221 /* break into full u-boot on 'c' */ 222 return (serial_tstc() && serial_getc() == 'c'); 223 } 224 #endif 225 226 #define OSC (V_OSCK/1000000) 227 const struct dpll_params dpll_ddr = { 228 266, OSC-1, 1, -1, -1, -1, -1}; 229 const struct dpll_params dpll_ddr_evm_sk = { 230 303, OSC-1, 1, -1, -1, -1, -1}; 231 const struct dpll_params dpll_ddr_bone_black = { 232 400, OSC-1, 1, -1, -1, -1, -1}; 233 234 void am33xx_spl_board_init(void) 235 { 236 struct am335x_baseboard_id header; 237 int mpu_vdd; 238 239 if (read_eeprom(&header) < 0) 240 puts("Could not get board ID.\n"); 241 242 /* Get the frequency */ 243 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 244 245 if (board_is_bone(&header) || board_is_bone_lt(&header)) { 246 /* BeagleBone PMIC Code */ 247 int usb_cur_lim; 248 249 /* 250 * Only perform PMIC configurations if board rev > A1 251 * on Beaglebone White 252 */ 253 if (board_is_bone(&header) && !strncmp(header.version, 254 "00A1", 4)) 255 return; 256 257 if (i2c_probe(TPS65217_CHIP_PM)) 258 return; 259 260 /* 261 * On Beaglebone White we need to ensure we have AC power 262 * before increasing the frequency. 263 */ 264 if (board_is_bone(&header)) { 265 uchar pmic_status_reg; 266 if (tps65217_reg_read(TPS65217_STATUS, 267 &pmic_status_reg)) 268 return; 269 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 270 puts("No AC power, disabling frequency switch\n"); 271 return; 272 } 273 } 274 275 /* 276 * Override what we have detected since we know if we have 277 * a Beaglebone Black it supports 1GHz. 278 */ 279 if (board_is_bone_lt(&header)) 280 dpll_mpu_opp100.m = MPUPLL_M_1000; 281 282 /* 283 * Increase USB current limit to 1300mA or 1800mA and set 284 * the MPU voltage controller as needed. 285 */ 286 if (dpll_mpu_opp100.m == MPUPLL_M_1000) { 287 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 288 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 289 } else { 290 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 291 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 292 } 293 294 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 295 TPS65217_POWER_PATH, 296 usb_cur_lim, 297 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 298 puts("tps65217_reg_write failure\n"); 299 300 /* Set DCDC3 (CORE) voltage to 1.125V */ 301 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 302 TPS65217_DCDC_VOLT_SEL_1125MV)) { 303 puts("tps65217_voltage_update failure\n"); 304 return; 305 } 306 307 /* Set CORE Frequencies to OPP100 */ 308 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 309 310 /* Set DCDC2 (MPU) voltage */ 311 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 312 puts("tps65217_voltage_update failure\n"); 313 return; 314 } 315 316 /* 317 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 318 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. 319 */ 320 if (board_is_bone(&header)) { 321 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 322 TPS65217_DEFLS1, 323 TPS65217_LDO_VOLTAGE_OUT_3_3, 324 TPS65217_LDO_MASK)) 325 puts("tps65217_reg_write failure\n"); 326 } else { 327 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 328 TPS65217_DEFLS1, 329 TPS65217_LDO_VOLTAGE_OUT_1_8, 330 TPS65217_LDO_MASK)) 331 puts("tps65217_reg_write failure\n"); 332 } 333 334 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 335 TPS65217_DEFLS2, 336 TPS65217_LDO_VOLTAGE_OUT_3_3, 337 TPS65217_LDO_MASK)) 338 puts("tps65217_reg_write failure\n"); 339 } else { 340 int sil_rev; 341 342 /* 343 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 344 * MPU frequencies we support we use a CORE voltage of 345 * 1.1375V. For MPU voltage we need to switch based on 346 * the frequency we are running at. 347 */ 348 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 349 return; 350 351 /* 352 * Depending on MPU clock and PG we will need a different 353 * VDD to drive at that speed. 354 */ 355 sil_rev = readl(&cdev->deviceid) >> 28; 356 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, 357 dpll_mpu_opp100.m); 358 359 /* Tell the TPS65910 to use i2c */ 360 tps65910_set_i2c_control(); 361 362 /* First update MPU voltage. */ 363 if (tps65910_voltage_update(MPU, mpu_vdd)) 364 return; 365 366 /* Second, update the CORE voltage. */ 367 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) 368 return; 369 370 /* Set CORE Frequencies to OPP100 */ 371 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 372 } 373 374 /* Set MPU Frequency to what we detected now that voltages are set */ 375 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 376 } 377 378 const struct dpll_params *get_dpll_ddr_params(void) 379 { 380 struct am335x_baseboard_id header; 381 382 enable_i2c0_pin_mux(); 383 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 384 if (read_eeprom(&header) < 0) 385 puts("Could not get board ID.\n"); 386 387 if (board_is_evm_sk(&header)) 388 return &dpll_ddr_evm_sk; 389 else if (board_is_bone_lt(&header)) 390 return &dpll_ddr_bone_black; 391 else if (board_is_evm_15_or_later(&header)) 392 return &dpll_ddr_evm_sk; 393 else 394 return &dpll_ddr; 395 } 396 397 void set_uart_mux_conf(void) 398 { 399 #ifdef CONFIG_SERIAL1 400 enable_uart0_pin_mux(); 401 #endif /* CONFIG_SERIAL1 */ 402 #ifdef CONFIG_SERIAL2 403 enable_uart1_pin_mux(); 404 #endif /* CONFIG_SERIAL2 */ 405 #ifdef CONFIG_SERIAL3 406 enable_uart2_pin_mux(); 407 #endif /* CONFIG_SERIAL3 */ 408 #ifdef CONFIG_SERIAL4 409 enable_uart3_pin_mux(); 410 #endif /* CONFIG_SERIAL4 */ 411 #ifdef CONFIG_SERIAL5 412 enable_uart4_pin_mux(); 413 #endif /* CONFIG_SERIAL5 */ 414 #ifdef CONFIG_SERIAL6 415 enable_uart5_pin_mux(); 416 #endif /* CONFIG_SERIAL6 */ 417 } 418 419 void set_mux_conf_regs(void) 420 { 421 __maybe_unused struct am335x_baseboard_id header; 422 423 if (read_eeprom(&header) < 0) 424 puts("Could not get board ID.\n"); 425 426 enable_board_pin_mux(&header); 427 } 428 429 void sdram_init(void) 430 { 431 __maybe_unused struct am335x_baseboard_id header; 432 433 if (read_eeprom(&header) < 0) 434 puts("Could not get board ID.\n"); 435 436 if (board_is_evm_sk(&header)) { 437 /* 438 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 439 * This is safe enough to do on older revs. 440 */ 441 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 442 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 443 } 444 445 if (board_is_evm_sk(&header)) 446 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 447 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 448 else if (board_is_bone_lt(&header)) 449 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, 450 &ddr3_beagleblack_data, 451 &ddr3_beagleblack_cmd_ctrl_data, 452 &ddr3_beagleblack_emif_reg_data, 0); 453 else if (board_is_evm_15_or_later(&header)) 454 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, 455 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 456 else 457 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 458 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 459 } 460 #endif 461 462 /* 463 * Basic board specific setup. Pinmux has been handled already. 464 */ 465 int board_init(void) 466 { 467 #ifdef CONFIG_NOR 468 const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, 469 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, 470 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; 471 #endif 472 473 #if defined(CONFIG_HW_WATCHDOG) 474 hw_watchdog_init(); 475 #endif 476 477 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 478 479 gpmc_init(); 480 481 #ifdef CONFIG_NOR 482 /* Reconfigure CS0 for NOR instead of NAND. */ 483 enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], 484 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); 485 #endif 486 487 return 0; 488 } 489 490 #ifdef CONFIG_BOARD_LATE_INIT 491 int board_late_init(void) 492 { 493 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 494 char safe_string[HDR_NAME_LEN + 1]; 495 struct am335x_baseboard_id header; 496 497 if (read_eeprom(&header) < 0) 498 puts("Could not get board ID.\n"); 499 500 /* Now set variables based on the header. */ 501 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 502 safe_string[sizeof(header.name)] = 0; 503 setenv("board_name", safe_string); 504 505 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 506 safe_string[sizeof(header.version)] = 0; 507 setenv("board_rev", safe_string); 508 #endif 509 510 return 0; 511 } 512 #endif 513 514 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 515 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 516 static void cpsw_control(int enabled) 517 { 518 /* VTP can be added here */ 519 520 return; 521 } 522 523 static struct cpsw_slave_data cpsw_slaves[] = { 524 { 525 .slave_reg_ofs = 0x208, 526 .sliver_reg_ofs = 0xd80, 527 .phy_id = 0, 528 }, 529 { 530 .slave_reg_ofs = 0x308, 531 .sliver_reg_ofs = 0xdc0, 532 .phy_id = 1, 533 }, 534 }; 535 536 static struct cpsw_platform_data cpsw_data = { 537 .mdio_base = CPSW_MDIO_BASE, 538 .cpsw_base = CPSW_BASE, 539 .mdio_div = 0xff, 540 .channels = 8, 541 .cpdma_reg_ofs = 0x800, 542 .slaves = 1, 543 .slave_data = cpsw_slaves, 544 .ale_reg_ofs = 0xd00, 545 .ale_entries = 1024, 546 .host_port_reg_ofs = 0x108, 547 .hw_stats_reg_ofs = 0x900, 548 .bd_ram_ofs = 0x2000, 549 .mac_control = (1 << 5), 550 .control = cpsw_control, 551 .host_port_num = 0, 552 .version = CPSW_CTRL_VERSION_2, 553 }; 554 #endif 555 556 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 557 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 558 int board_eth_init(bd_t *bis) 559 { 560 int rv, n = 0; 561 uint8_t mac_addr[6]; 562 uint32_t mac_hi, mac_lo; 563 __maybe_unused struct am335x_baseboard_id header; 564 565 /* try reading mac address from efuse */ 566 mac_lo = readl(&cdev->macid0l); 567 mac_hi = readl(&cdev->macid0h); 568 mac_addr[0] = mac_hi & 0xFF; 569 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 570 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 571 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 572 mac_addr[4] = mac_lo & 0xFF; 573 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 574 575 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 576 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 577 if (!getenv("ethaddr")) { 578 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 579 580 if (is_valid_ether_addr(mac_addr)) 581 eth_setenv_enetaddr("ethaddr", mac_addr); 582 } 583 584 #ifdef CONFIG_DRIVER_TI_CPSW 585 if (read_eeprom(&header) < 0) 586 puts("Could not get board ID.\n"); 587 588 if (board_is_bone(&header) || board_is_bone_lt(&header) || 589 board_is_idk(&header)) { 590 writel(MII_MODE_ENABLE, &cdev->miisel); 591 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 592 PHY_INTERFACE_MODE_MII; 593 } else { 594 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 595 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 596 PHY_INTERFACE_MODE_RGMII; 597 } 598 599 rv = cpsw_register(&cpsw_data); 600 if (rv < 0) 601 printf("Error %d registering CPSW switch\n", rv); 602 else 603 n += rv; 604 #endif 605 606 /* 607 * 608 * CPSW RGMII Internal Delay Mode is not supported in all PVT 609 * operating points. So we must set the TX clock delay feature 610 * in the AR8051 PHY. Since we only support a single ethernet 611 * device in U-Boot, we only do this for the first instance. 612 */ 613 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 614 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 615 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 616 #define AR8051_RGMII_TX_CLK_DLY 0x100 617 618 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { 619 const char *devname; 620 devname = miiphy_get_current_dev(); 621 622 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 623 AR8051_DEBUG_RGMII_CLK_DLY_REG); 624 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 625 AR8051_RGMII_TX_CLK_DLY); 626 } 627 #endif 628 #if defined(CONFIG_USB_ETHER) && \ 629 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 630 if (is_valid_ether_addr(mac_addr)) 631 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 632 633 rv = usb_eth_initialize(bis); 634 if (rv < 0) 635 printf("Error %d registering USB_ETHER\n", rv); 636 else 637 n += rv; 638 #endif 639 return n; 640 } 641 #endif 642