1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <common.h> 20 #include <errno.h> 21 #include <spl.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/hardware.h> 24 #include <asm/arch/omap.h> 25 #include <asm/arch/ddr_defs.h> 26 #include <asm/arch/clock.h> 27 #include <asm/arch/gpio.h> 28 #include <asm/arch/mmc_host_def.h> 29 #include <asm/arch/sys_proto.h> 30 #include <asm/io.h> 31 #include <asm/emif.h> 32 #include <asm/gpio.h> 33 #include <i2c.h> 34 #include <miiphy.h> 35 #include <cpsw.h> 36 #include "board.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 41 #ifdef CONFIG_SPL_BUILD 42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 43 #endif 44 45 /* MII mode defines */ 46 #define MII_MODE_ENABLE 0x0 47 #define RGMII_MODE_ENABLE 0xA 48 49 /* GPIO that controls power to DDR on EVM-SK */ 50 #define GPIO_DDR_VTT_EN 7 51 52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 53 54 static struct am335x_baseboard_id __attribute__((section (".data"))) header; 55 56 static inline int board_is_bone(void) 57 { 58 return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); 59 } 60 61 static inline int board_is_bone_lt(void) 62 { 63 return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); 64 } 65 66 static inline int board_is_evm_sk(void) 67 { 68 return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); 69 } 70 71 /* 72 * Read header information from EEPROM into global structure. 73 */ 74 static int read_eeprom(void) 75 { 76 /* Check if baseboard eeprom is available */ 77 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 78 puts("Could not probe the EEPROM; something fundamentally " 79 "wrong on the I2C bus.\n"); 80 return -ENODEV; 81 } 82 83 /* read the eeprom using i2c */ 84 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, 85 sizeof(header))) { 86 puts("Could not read the EEPROM; something fundamentally" 87 " wrong on the I2C bus.\n"); 88 return -EIO; 89 } 90 91 if (header.magic != 0xEE3355AA) { 92 /* 93 * read the eeprom using i2c again, 94 * but use only a 1 byte address 95 */ 96 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, 97 (uchar *)&header, sizeof(header))) { 98 puts("Could not read the EEPROM; something " 99 "fundamentally wrong on the I2C bus.\n"); 100 return -EIO; 101 } 102 103 if (header.magic != 0xEE3355AA) { 104 printf("Incorrect magic number (0x%x) in EEPROM\n", 105 header.magic); 106 return -EINVAL; 107 } 108 } 109 110 return 0; 111 } 112 113 /* UART Defines */ 114 #ifdef CONFIG_SPL_BUILD 115 #define UART_RESET (0x1 << 1) 116 #define UART_CLK_RUNNING_MASK 0x1 117 #define UART_SMART_IDLE_EN (0x1 << 0x3) 118 119 static void rtc32k_enable(void) 120 { 121 struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; 122 123 /* 124 * Unlock the RTC's registers. For more details please see the 125 * RTC_SS section of the TRM. In order to unlock we need to 126 * write these specific values (keys) in this order. 127 */ 128 writel(0x83e70b13, &rtc->kick0r); 129 writel(0x95a4f1e0, &rtc->kick1r); 130 131 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 132 writel((1 << 3) | (1 << 6), &rtc->osc); 133 } 134 135 static const struct ddr_data ddr2_data = { 136 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 137 (MT47H128M16RT25E_RD_DQS<<20) | 138 (MT47H128M16RT25E_RD_DQS<<10) | 139 (MT47H128M16RT25E_RD_DQS<<0)), 140 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 141 (MT47H128M16RT25E_WR_DQS<<20) | 142 (MT47H128M16RT25E_WR_DQS<<10) | 143 (MT47H128M16RT25E_WR_DQS<<0)), 144 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 145 (MT47H128M16RT25E_PHY_WRLVL<<20) | 146 (MT47H128M16RT25E_PHY_WRLVL<<10) | 147 (MT47H128M16RT25E_PHY_WRLVL<<0)), 148 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 149 (MT47H128M16RT25E_PHY_GATELVL<<20) | 150 (MT47H128M16RT25E_PHY_GATELVL<<10) | 151 (MT47H128M16RT25E_PHY_GATELVL<<0)), 152 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 153 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 154 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 155 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 156 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 157 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 158 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 159 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 160 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, 161 .datadldiff0 = PHY_DLL_LOCK_DIFF, 162 }; 163 164 static const struct cmd_control ddr2_cmd_ctrl_data = { 165 .cmd0csratio = MT47H128M16RT25E_RATIO, 166 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 167 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 168 169 .cmd1csratio = MT47H128M16RT25E_RATIO, 170 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 171 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 172 173 .cmd2csratio = MT47H128M16RT25E_RATIO, 174 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 175 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 176 }; 177 178 static const struct emif_regs ddr2_emif_reg_data = { 179 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 180 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 181 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 182 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 183 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 184 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 185 }; 186 187 static const struct ddr_data ddr3_data = { 188 .datardsratio0 = MT41J128MJT125_RD_DQS, 189 .datawdsratio0 = MT41J128MJT125_WR_DQS, 190 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 191 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 192 .datadldiff0 = PHY_DLL_LOCK_DIFF, 193 }; 194 195 static const struct cmd_control ddr3_cmd_ctrl_data = { 196 .cmd0csratio = MT41J128MJT125_RATIO, 197 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 198 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 199 200 .cmd1csratio = MT41J128MJT125_RATIO, 201 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 202 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 203 204 .cmd2csratio = MT41J128MJT125_RATIO, 205 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 206 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 207 }; 208 209 static struct emif_regs ddr3_emif_reg_data = { 210 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 211 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 212 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 213 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 214 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 215 .zq_config = MT41J128MJT125_ZQ_CFG, 216 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, 217 }; 218 #endif 219 220 /* 221 * early system init of muxing and clocks. 222 */ 223 void s_init(void) 224 { 225 /* WDT1 is already running when the bootloader gets control 226 * Disable it to avoid "random" resets 227 */ 228 writel(0xAAAA, &wdtimer->wdtwspr); 229 while (readl(&wdtimer->wdtwwps) != 0x0) 230 ; 231 writel(0x5555, &wdtimer->wdtwspr); 232 while (readl(&wdtimer->wdtwwps) != 0x0) 233 ; 234 235 #ifdef CONFIG_SPL_BUILD 236 /* Setup the PLLs and the clocks for the peripherals */ 237 pll_init(); 238 239 /* Enable RTC32K clock */ 240 rtc32k_enable(); 241 242 /* UART softreset */ 243 u32 regVal; 244 245 enable_uart0_pin_mux(); 246 247 regVal = readl(&uart_base->uartsyscfg); 248 regVal |= UART_RESET; 249 writel(regVal, &uart_base->uartsyscfg); 250 while ((readl(&uart_base->uartsyssts) & 251 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 252 ; 253 254 /* Disable smart idle */ 255 regVal = readl(&uart_base->uartsyscfg); 256 regVal |= UART_SMART_IDLE_EN; 257 writel(regVal, &uart_base->uartsyscfg); 258 259 gd = &gdata; 260 261 preloader_console_init(); 262 263 /* Initalize the board header */ 264 enable_i2c0_pin_mux(); 265 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 266 if (read_eeprom() < 0) 267 puts("Could not get board ID.\n"); 268 269 enable_board_pin_mux(&header); 270 if (board_is_evm_sk()) { 271 /* 272 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 273 * This is safe enough to do on older revs. 274 */ 275 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 276 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 277 } 278 279 if (board_is_evm_sk() || board_is_bone_lt()) 280 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 281 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); 282 else 283 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 284 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); 285 #endif 286 } 287 288 /* 289 * Basic board specific setup. Pinmux has been handled already. 290 */ 291 int board_init(void) 292 { 293 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 294 if (read_eeprom() < 0) 295 puts("Could not get board ID.\n"); 296 297 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 298 299 return 0; 300 } 301 302 #ifdef CONFIG_DRIVER_TI_CPSW 303 static void cpsw_control(int enabled) 304 { 305 /* VTP can be added here */ 306 307 return; 308 } 309 310 static struct cpsw_slave_data cpsw_slaves[] = { 311 { 312 .slave_reg_ofs = 0x208, 313 .sliver_reg_ofs = 0xd80, 314 .phy_id = 0, 315 }, 316 { 317 .slave_reg_ofs = 0x308, 318 .sliver_reg_ofs = 0xdc0, 319 .phy_id = 1, 320 }, 321 }; 322 323 static struct cpsw_platform_data cpsw_data = { 324 .mdio_base = AM335X_CPSW_MDIO_BASE, 325 .cpsw_base = AM335X_CPSW_BASE, 326 .mdio_div = 0xff, 327 .channels = 8, 328 .cpdma_reg_ofs = 0x800, 329 .slaves = 1, 330 .slave_data = cpsw_slaves, 331 .ale_reg_ofs = 0xd00, 332 .ale_entries = 1024, 333 .host_port_reg_ofs = 0x108, 334 .hw_stats_reg_ofs = 0x900, 335 .mac_control = (1 << 5), 336 .control = cpsw_control, 337 .host_port_num = 0, 338 .version = CPSW_CTRL_VERSION_2, 339 }; 340 341 int board_eth_init(bd_t *bis) 342 { 343 uint8_t mac_addr[6]; 344 uint32_t mac_hi, mac_lo; 345 346 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 347 debug("<ethaddr> not set. Reading from E-fuse\n"); 348 /* try reading mac address from efuse */ 349 mac_lo = readl(&cdev->macid0l); 350 mac_hi = readl(&cdev->macid0h); 351 mac_addr[0] = mac_hi & 0xFF; 352 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 353 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 354 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 355 mac_addr[4] = mac_lo & 0xFF; 356 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 357 358 if (is_valid_ether_addr(mac_addr)) 359 eth_setenv_enetaddr("ethaddr", mac_addr); 360 else 361 return -1; 362 } 363 364 if (board_is_bone() || board_is_bone_lt()) { 365 writel(MII_MODE_ENABLE, &cdev->miisel); 366 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 367 PHY_INTERFACE_MODE_MII; 368 } else { 369 writel(RGMII_MODE_ENABLE, &cdev->miisel); 370 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 371 PHY_INTERFACE_MODE_RGMII; 372 } 373 374 return cpsw_register(&cpsw_data); 375 } 376 #endif 377