1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <spl.h> 15 #include <serial.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/omap.h> 19 #include <asm/arch/ddr_defs.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/clk_synthesizer.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/sys_proto.h> 25 #include <asm/arch/mem.h> 26 #include <asm/io.h> 27 #include <asm/emif.h> 28 #include <asm/gpio.h> 29 #include <asm/omap_sec_common.h> 30 #include <asm/omap_mmc.h> 31 #include <i2c.h> 32 #include <miiphy.h> 33 #include <cpsw.h> 34 #include <power/tps65217.h> 35 #include <power/tps65910.h> 36 #include <environment.h> 37 #include <watchdog.h> 38 #include <environment.h> 39 #include "../common/board_detect.h" 40 #include "board.h" 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* GPIO that controls power to DDR on EVM-SK */ 45 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 46 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) 47 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) 48 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) 49 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) 50 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) 51 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) 52 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11) 53 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26) 54 55 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 56 57 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT) 58 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT) 59 60 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1) 61 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1) 62 63 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024) 64 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024) 65 66 /* 67 * Read header information from EEPROM into global structure. 68 */ 69 #ifdef CONFIG_TI_I2C_BOARD_DETECT 70 void do_board_detect(void) 71 { 72 enable_i2c0_pin_mux(); 73 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 74 75 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 76 CONFIG_EEPROM_CHIP_ADDRESS)) 77 printf("ti_i2c_eeprom_init failed\n"); 78 } 79 #endif 80 81 #ifndef CONFIG_DM_SERIAL 82 struct serial_device *default_serial_console(void) 83 { 84 if (board_is_icev2()) 85 return &eserial4_device; 86 else 87 return &eserial1_device; 88 } 89 #endif 90 91 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 92 static const struct ddr_data ddr2_data = { 93 .datardsratio0 = MT47H128M16RT25E_RD_DQS, 94 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, 95 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, 96 }; 97 98 static const struct cmd_control ddr2_cmd_ctrl_data = { 99 .cmd0csratio = MT47H128M16RT25E_RATIO, 100 101 .cmd1csratio = MT47H128M16RT25E_RATIO, 102 103 .cmd2csratio = MT47H128M16RT25E_RATIO, 104 }; 105 106 static const struct emif_regs ddr2_emif_reg_data = { 107 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 108 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 109 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 110 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 111 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 112 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 113 }; 114 115 static const struct emif_regs ddr2_evm_emif_reg_data = { 116 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 117 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 118 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 119 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 120 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 121 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, 122 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 123 }; 124 125 static const struct ddr_data ddr3_data = { 126 .datardsratio0 = MT41J128MJT125_RD_DQS, 127 .datawdsratio0 = MT41J128MJT125_WR_DQS, 128 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 129 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 130 }; 131 132 static const struct ddr_data ddr3_beagleblack_data = { 133 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 134 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 135 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 136 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 137 }; 138 139 static const struct ddr_data ddr3_evm_data = { 140 .datardsratio0 = MT41J512M8RH125_RD_DQS, 141 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 142 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 143 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 144 }; 145 146 static const struct ddr_data ddr3_icev2_data = { 147 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, 148 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, 149 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, 150 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, 151 }; 152 153 static const struct cmd_control ddr3_cmd_ctrl_data = { 154 .cmd0csratio = MT41J128MJT125_RATIO, 155 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 156 157 .cmd1csratio = MT41J128MJT125_RATIO, 158 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 159 160 .cmd2csratio = MT41J128MJT125_RATIO, 161 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 162 }; 163 164 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 165 .cmd0csratio = MT41K256M16HA125E_RATIO, 166 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 167 168 .cmd1csratio = MT41K256M16HA125E_RATIO, 169 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 170 171 .cmd2csratio = MT41K256M16HA125E_RATIO, 172 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 173 }; 174 175 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 176 .cmd0csratio = MT41J512M8RH125_RATIO, 177 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 178 179 .cmd1csratio = MT41J512M8RH125_RATIO, 180 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 181 182 .cmd2csratio = MT41J512M8RH125_RATIO, 183 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 184 }; 185 186 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { 187 .cmd0csratio = MT41J128MJT125_RATIO_400MHz, 188 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 189 190 .cmd1csratio = MT41J128MJT125_RATIO_400MHz, 191 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 192 193 .cmd2csratio = MT41J128MJT125_RATIO_400MHz, 194 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 195 }; 196 197 static struct emif_regs ddr3_emif_reg_data = { 198 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 199 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 200 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 201 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 202 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 203 .zq_config = MT41J128MJT125_ZQ_CFG, 204 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 205 PHY_EN_DYN_PWRDN, 206 }; 207 208 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 209 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 210 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 211 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 212 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 213 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 214 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK, 215 .zq_config = MT41K256M16HA125E_ZQ_CFG, 216 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 217 }; 218 219 static struct emif_regs ddr3_evm_emif_reg_data = { 220 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 221 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 222 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 223 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 224 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 225 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, 226 .zq_config = MT41J512M8RH125_ZQ_CFG, 227 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 228 PHY_EN_DYN_PWRDN, 229 }; 230 231 static struct emif_regs ddr3_icev2_emif_reg_data = { 232 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, 233 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, 234 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, 235 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, 236 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, 237 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, 238 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | 239 PHY_EN_DYN_PWRDN, 240 }; 241 242 #ifdef CONFIG_SPL_OS_BOOT 243 int spl_start_uboot(void) 244 { 245 /* break into full u-boot on 'c' */ 246 if (serial_tstc() && serial_getc() == 'c') 247 return 1; 248 249 #ifdef CONFIG_SPL_ENV_SUPPORT 250 env_init(); 251 env_relocate_spec(); 252 if (getenv_yesno("boot_os") != 1) 253 return 1; 254 #endif 255 256 return 0; 257 } 258 #endif 259 260 const struct dpll_params *get_dpll_ddr_params(void) 261 { 262 int ind = get_sys_clk_index(); 263 264 if (board_is_evm_sk()) 265 return &dpll_ddr3_303MHz[ind]; 266 else if (board_is_bone_lt() || board_is_icev2()) 267 return &dpll_ddr3_400MHz[ind]; 268 else if (board_is_evm_15_or_later()) 269 return &dpll_ddr3_303MHz[ind]; 270 else 271 return &dpll_ddr2_266MHz[ind]; 272 } 273 274 static u8 bone_not_connected_to_ac_power(void) 275 { 276 if (board_is_bone()) { 277 uchar pmic_status_reg; 278 if (tps65217_reg_read(TPS65217_STATUS, 279 &pmic_status_reg)) 280 return 1; 281 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 282 puts("No AC power, switching to default OPP\n"); 283 return 1; 284 } 285 } 286 return 0; 287 } 288 289 const struct dpll_params *get_dpll_mpu_params(void) 290 { 291 int ind = get_sys_clk_index(); 292 int freq = am335x_get_efuse_mpu_max_freq(cdev); 293 294 if (bone_not_connected_to_ac_power()) 295 freq = MPUPLL_M_600; 296 297 if (board_is_bone_lt()) 298 freq = MPUPLL_M_1000; 299 300 switch (freq) { 301 case MPUPLL_M_1000: 302 return &dpll_mpu_opp[ind][5]; 303 case MPUPLL_M_800: 304 return &dpll_mpu_opp[ind][4]; 305 case MPUPLL_M_720: 306 return &dpll_mpu_opp[ind][3]; 307 case MPUPLL_M_600: 308 return &dpll_mpu_opp[ind][2]; 309 case MPUPLL_M_500: 310 return &dpll_mpu_opp100; 311 case MPUPLL_M_300: 312 return &dpll_mpu_opp[ind][0]; 313 } 314 315 return &dpll_mpu_opp[ind][0]; 316 } 317 318 static void scale_vcores_bone(int freq) 319 { 320 int usb_cur_lim, mpu_vdd; 321 322 /* 323 * Only perform PMIC configurations if board rev > A1 324 * on Beaglebone White 325 */ 326 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) 327 return; 328 329 if (i2c_probe(TPS65217_CHIP_PM)) 330 return; 331 332 /* 333 * On Beaglebone White we need to ensure we have AC power 334 * before increasing the frequency. 335 */ 336 if (bone_not_connected_to_ac_power()) 337 freq = MPUPLL_M_600; 338 339 /* 340 * Override what we have detected since we know if we have 341 * a Beaglebone Black it supports 1GHz. 342 */ 343 if (board_is_bone_lt()) 344 freq = MPUPLL_M_1000; 345 346 if (freq == MPUPLL_M_1000) { 347 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 348 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 349 } else { 350 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 351 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 352 } 353 354 switch (freq) { 355 case MPUPLL_M_1000: 356 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 357 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 358 break; 359 case MPUPLL_M_800: 360 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 361 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 362 break; 363 case MPUPLL_M_720: 364 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; 365 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 366 break; 367 case MPUPLL_M_600: 368 case MPUPLL_M_500: 369 case MPUPLL_M_300: 370 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; 371 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 372 break; 373 } 374 375 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 376 TPS65217_POWER_PATH, 377 usb_cur_lim, 378 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 379 puts("tps65217_reg_write failure\n"); 380 381 /* Set DCDC3 (CORE) voltage to 1.10V */ 382 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 383 TPS65217_DCDC_VOLT_SEL_1100MV)) { 384 puts("tps65217_voltage_update failure\n"); 385 return; 386 } 387 388 /* Set DCDC2 (MPU) voltage */ 389 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 390 puts("tps65217_voltage_update failure\n"); 391 return; 392 } 393 394 /* 395 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 396 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. 397 */ 398 if (board_is_bone()) { 399 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 400 TPS65217_DEFLS1, 401 TPS65217_LDO_VOLTAGE_OUT_3_3, 402 TPS65217_LDO_MASK)) 403 puts("tps65217_reg_write failure\n"); 404 } else { 405 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 406 TPS65217_DEFLS1, 407 TPS65217_LDO_VOLTAGE_OUT_1_8, 408 TPS65217_LDO_MASK)) 409 puts("tps65217_reg_write failure\n"); 410 } 411 412 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 413 TPS65217_DEFLS2, 414 TPS65217_LDO_VOLTAGE_OUT_3_3, 415 TPS65217_LDO_MASK)) 416 puts("tps65217_reg_write failure\n"); 417 } 418 419 void scale_vcores_generic(int freq) 420 { 421 int sil_rev, mpu_vdd; 422 423 /* 424 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 425 * MPU frequencies we support we use a CORE voltage of 426 * 1.10V. For MPU voltage we need to switch based on 427 * the frequency we are running at. 428 */ 429 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 430 return; 431 432 /* 433 * Depending on MPU clock and PG we will need a different 434 * VDD to drive at that speed. 435 */ 436 sil_rev = readl(&cdev->deviceid) >> 28; 437 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); 438 439 /* Tell the TPS65910 to use i2c */ 440 tps65910_set_i2c_control(); 441 442 /* First update MPU voltage. */ 443 if (tps65910_voltage_update(MPU, mpu_vdd)) 444 return; 445 446 /* Second, update the CORE voltage. */ 447 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0)) 448 return; 449 450 } 451 452 void gpi2c_init(void) 453 { 454 /* When needed to be invoked prior to BSS initialization */ 455 static bool first_time = true; 456 457 if (first_time) { 458 enable_i2c0_pin_mux(); 459 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 460 CONFIG_SYS_OMAP24_I2C_SLAVE); 461 first_time = false; 462 } 463 } 464 465 void scale_vcores(void) 466 { 467 int freq; 468 469 gpi2c_init(); 470 freq = am335x_get_efuse_mpu_max_freq(cdev); 471 472 if (board_is_bone()) 473 scale_vcores_bone(freq); 474 else 475 scale_vcores_generic(freq); 476 } 477 478 void set_uart_mux_conf(void) 479 { 480 #if CONFIG_CONS_INDEX == 1 481 enable_uart0_pin_mux(); 482 #elif CONFIG_CONS_INDEX == 2 483 enable_uart1_pin_mux(); 484 #elif CONFIG_CONS_INDEX == 3 485 enable_uart2_pin_mux(); 486 #elif CONFIG_CONS_INDEX == 4 487 enable_uart3_pin_mux(); 488 #elif CONFIG_CONS_INDEX == 5 489 enable_uart4_pin_mux(); 490 #elif CONFIG_CONS_INDEX == 6 491 enable_uart5_pin_mux(); 492 #endif 493 } 494 495 void set_mux_conf_regs(void) 496 { 497 enable_board_pin_mux(); 498 } 499 500 const struct ctrl_ioregs ioregs_evmsk = { 501 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 502 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 503 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 504 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 505 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 506 }; 507 508 const struct ctrl_ioregs ioregs_bonelt = { 509 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 510 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 511 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 512 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 513 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 514 }; 515 516 const struct ctrl_ioregs ioregs_evm15 = { 517 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 518 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 519 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, 520 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 521 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 522 }; 523 524 const struct ctrl_ioregs ioregs = { 525 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 526 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 527 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 528 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 529 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 530 }; 531 532 void sdram_init(void) 533 { 534 if (board_is_evm_sk()) { 535 /* 536 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 537 * This is safe enough to do on older revs. 538 */ 539 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 540 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 541 } 542 543 if (board_is_icev2()) { 544 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); 545 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); 546 } 547 548 if (board_is_evm_sk()) 549 config_ddr(303, &ioregs_evmsk, &ddr3_data, 550 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 551 else if (board_is_bone_lt()) 552 config_ddr(400, &ioregs_bonelt, 553 &ddr3_beagleblack_data, 554 &ddr3_beagleblack_cmd_ctrl_data, 555 &ddr3_beagleblack_emif_reg_data, 0); 556 else if (board_is_evm_15_or_later()) 557 config_ddr(303, &ioregs_evm15, &ddr3_evm_data, 558 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 559 else if (board_is_icev2()) 560 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, 561 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 562 0); 563 else if (board_is_gp_evm()) 564 config_ddr(266, &ioregs, &ddr2_data, 565 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0); 566 else 567 config_ddr(266, &ioregs, &ddr2_data, 568 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 569 } 570 #endif 571 572 #if !defined(CONFIG_SPL_BUILD) || \ 573 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 574 static void request_and_set_gpio(int gpio, char *name, int val) 575 { 576 int ret; 577 578 ret = gpio_request(gpio, name); 579 if (ret < 0) { 580 printf("%s: Unable to request %s\n", __func__, name); 581 return; 582 } 583 584 ret = gpio_direction_output(gpio, 0); 585 if (ret < 0) { 586 printf("%s: Unable to set %s as output\n", __func__, name); 587 goto err_free_gpio; 588 } 589 590 gpio_set_value(gpio, val); 591 592 return; 593 594 err_free_gpio: 595 gpio_free(gpio); 596 } 597 598 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1); 599 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0); 600 601 /** 602 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock 603 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle 604 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to 605 * give 50MHz output for Eth0 and 1. 606 */ 607 static struct clk_synth cdce913_data = { 608 .id = 0x81, 609 .capacitor = 0x90, 610 .mux = 0x6d, 611 .pdiv2 = 0x2, 612 .pdiv3 = 0x2, 613 }; 614 #endif 615 616 /* 617 * Basic board specific setup. Pinmux has been handled already. 618 */ 619 int board_init(void) 620 { 621 #if defined(CONFIG_HW_WATCHDOG) 622 hw_watchdog_init(); 623 #endif 624 625 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 626 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 627 gpmc_init(); 628 #endif 629 630 #if !defined(CONFIG_SPL_BUILD) || \ 631 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 632 if (board_is_icev2()) { 633 int rv; 634 u32 reg; 635 636 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); 637 /* Make J19 status available on GPIO1_26 */ 638 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL); 639 640 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); 641 /* 642 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using 643 * jumpers near the port. Read the jumper value and set 644 * the pinmux, external mux and PHY clock accordingly. 645 * As jumper line is overridden by PHY RX_DV pin immediately 646 * after bootstrap (power-up/reset), we need to sample 647 * it during PHY reset using GPIO rising edge detection. 648 */ 649 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); 650 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */ 651 reg = readl(GPIO0_RISINGDETECT) | BIT(11); 652 writel(reg, GPIO0_RISINGDETECT); 653 reg = readl(GPIO1_RISINGDETECT) | BIT(26); 654 writel(reg, GPIO1_RISINGDETECT); 655 /* Reset PHYs to capture the Jumper setting */ 656 gpio_set_value(GPIO_PHY_RESET, 0); 657 udelay(2); /* PHY datasheet states 1uS min. */ 658 gpio_set_value(GPIO_PHY_RESET, 1); 659 660 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11); 661 if (reg) { 662 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */ 663 /* RMII mode */ 664 printf("ETH0, CPSW\n"); 665 } else { 666 /* MII mode */ 667 printf("ETH0, PRU\n"); 668 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ 669 } 670 671 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26); 672 if (reg) { 673 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */ 674 /* RMII mode */ 675 printf("ETH1, CPSW\n"); 676 gpio_set_value(GPIO_MUX_MII_CTRL, 1); 677 } else { 678 /* MII mode */ 679 printf("ETH1, PRU\n"); 680 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ 681 } 682 683 /* disable rising edge IRQs */ 684 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11); 685 writel(reg, GPIO0_RISINGDETECT); 686 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26); 687 writel(reg, GPIO1_RISINGDETECT); 688 689 rv = setup_clock_synthesizer(&cdce913_data); 690 if (rv) { 691 printf("Clock synthesizer setup failed %d\n", rv); 692 return rv; 693 } 694 695 /* reset PHYs */ 696 gpio_set_value(GPIO_PHY_RESET, 0); 697 udelay(2); /* PHY datasheet states 1uS min. */ 698 gpio_set_value(GPIO_PHY_RESET, 1); 699 } 700 #endif 701 702 return 0; 703 } 704 705 #ifdef CONFIG_BOARD_LATE_INIT 706 int board_late_init(void) 707 { 708 #if !defined(CONFIG_SPL_BUILD) 709 uint8_t mac_addr[6]; 710 uint32_t mac_hi, mac_lo; 711 #endif 712 713 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 714 char *name = NULL; 715 716 if (board_is_bone_lt()) { 717 /* BeagleBoard.org BeagleBone Black Wireless: */ 718 if (!strncmp(board_ti_get_rev(), "BWA", 3)) { 719 name = "BBBW"; 720 } 721 /* SeeedStudio BeagleBone Green Wireless */ 722 if (!strncmp(board_ti_get_rev(), "GW1", 3)) { 723 name = "BBGW"; 724 } 725 /* BeagleBoard.org BeagleBone Blue */ 726 if (!strncmp(board_ti_get_rev(), "BLA", 3)) { 727 name = "BBBL"; 728 } 729 } 730 731 if (board_is_bbg1()) 732 name = "BBG1"; 733 set_board_info_env(name); 734 735 /* 736 * Default FIT boot on HS devices. Non FIT images are not allowed 737 * on HS devices. 738 */ 739 if (get_device_type() == HS_DEVICE) 740 setenv("boot_fit", "1"); 741 #endif 742 743 #if !defined(CONFIG_SPL_BUILD) 744 /* try reading mac address from efuse */ 745 mac_lo = readl(&cdev->macid0l); 746 mac_hi = readl(&cdev->macid0h); 747 mac_addr[0] = mac_hi & 0xFF; 748 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 749 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 750 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 751 mac_addr[4] = mac_lo & 0xFF; 752 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 753 754 if (!getenv("ethaddr")) { 755 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 756 757 if (is_valid_ethaddr(mac_addr)) 758 eth_setenv_enetaddr("ethaddr", mac_addr); 759 } 760 761 mac_lo = readl(&cdev->macid1l); 762 mac_hi = readl(&cdev->macid1h); 763 mac_addr[0] = mac_hi & 0xFF; 764 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 765 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 766 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 767 mac_addr[4] = mac_lo & 0xFF; 768 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 769 770 if (!getenv("eth1addr")) { 771 if (is_valid_ethaddr(mac_addr)) 772 eth_setenv_enetaddr("eth1addr", mac_addr); 773 } 774 #endif 775 776 return 0; 777 } 778 #endif 779 780 #ifndef CONFIG_DM_ETH 781 782 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 783 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 784 static void cpsw_control(int enabled) 785 { 786 /* VTP can be added here */ 787 788 return; 789 } 790 791 static struct cpsw_slave_data cpsw_slaves[] = { 792 { 793 .slave_reg_ofs = 0x208, 794 .sliver_reg_ofs = 0xd80, 795 .phy_addr = 0, 796 }, 797 { 798 .slave_reg_ofs = 0x308, 799 .sliver_reg_ofs = 0xdc0, 800 .phy_addr = 1, 801 }, 802 }; 803 804 static struct cpsw_platform_data cpsw_data = { 805 .mdio_base = CPSW_MDIO_BASE, 806 .cpsw_base = CPSW_BASE, 807 .mdio_div = 0xff, 808 .channels = 8, 809 .cpdma_reg_ofs = 0x800, 810 .slaves = 1, 811 .slave_data = cpsw_slaves, 812 .ale_reg_ofs = 0xd00, 813 .ale_entries = 1024, 814 .host_port_reg_ofs = 0x108, 815 .hw_stats_reg_ofs = 0x900, 816 .bd_ram_ofs = 0x2000, 817 .mac_control = (1 << 5), 818 .control = cpsw_control, 819 .host_port_num = 0, 820 .version = CPSW_CTRL_VERSION_2, 821 }; 822 #endif 823 824 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ 825 defined(CONFIG_SPL_BUILD)) || \ 826 ((defined(CONFIG_DRIVER_TI_CPSW) || \ 827 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ 828 !defined(CONFIG_SPL_BUILD)) 829 830 /* 831 * This function will: 832 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr 833 * in the environment 834 * Perform fixups to the PHY present on certain boards. We only need this 835 * function in: 836 * - SPL with either CPSW or USB ethernet support 837 * - Full U-Boot, with either CPSW or USB ethernet 838 * Build in only these cases to avoid warnings about unused variables 839 * when we build an SPL that has neither option but full U-Boot will. 840 */ 841 int board_eth_init(bd_t *bis) 842 { 843 int rv, n = 0; 844 #if defined(CONFIG_USB_ETHER) && \ 845 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 846 uint8_t mac_addr[6]; 847 uint32_t mac_hi, mac_lo; 848 849 /* 850 * use efuse mac address for USB ethernet as we know that 851 * both CPSW and USB ethernet will never be active at the same time 852 */ 853 mac_lo = readl(&cdev->macid0l); 854 mac_hi = readl(&cdev->macid0h); 855 mac_addr[0] = mac_hi & 0xFF; 856 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 857 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 858 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 859 mac_addr[4] = mac_lo & 0xFF; 860 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 861 #endif 862 863 864 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 865 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 866 867 #ifdef CONFIG_DRIVER_TI_CPSW 868 if (board_is_bone() || board_is_bone_lt() || 869 board_is_idk()) { 870 writel(MII_MODE_ENABLE, &cdev->miisel); 871 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 872 PHY_INTERFACE_MODE_MII; 873 } else if (board_is_icev2()) { 874 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 875 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 876 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; 877 cpsw_slaves[0].phy_addr = 1; 878 cpsw_slaves[1].phy_addr = 3; 879 } else { 880 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 881 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 882 PHY_INTERFACE_MODE_RGMII; 883 } 884 885 rv = cpsw_register(&cpsw_data); 886 if (rv < 0) 887 printf("Error %d registering CPSW switch\n", rv); 888 else 889 n += rv; 890 #endif 891 892 /* 893 * 894 * CPSW RGMII Internal Delay Mode is not supported in all PVT 895 * operating points. So we must set the TX clock delay feature 896 * in the AR8051 PHY. Since we only support a single ethernet 897 * device in U-Boot, we only do this for the first instance. 898 */ 899 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 900 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 901 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 902 #define AR8051_RGMII_TX_CLK_DLY 0x100 903 904 if (board_is_evm_sk() || board_is_gp_evm()) { 905 const char *devname; 906 devname = miiphy_get_current_dev(); 907 908 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 909 AR8051_DEBUG_RGMII_CLK_DLY_REG); 910 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 911 AR8051_RGMII_TX_CLK_DLY); 912 } 913 #endif 914 #if defined(CONFIG_USB_ETHER) && \ 915 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 916 if (is_valid_ethaddr(mac_addr)) 917 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 918 919 rv = usb_eth_initialize(bis); 920 if (rv < 0) 921 printf("Error %d registering USB_ETHER\n", rv); 922 else 923 n += rv; 924 #endif 925 return n; 926 } 927 #endif 928 929 #endif /* CONFIG_DM_ETH */ 930 931 #ifdef CONFIG_SPL_LOAD_FIT 932 int board_fit_config_name_match(const char *name) 933 { 934 if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) 935 return 0; 936 else if (board_is_bone() && !strcmp(name, "am335x-bone")) 937 return 0; 938 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) 939 return 0; 940 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) 941 return 0; 942 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) 943 return 0; 944 else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) 945 return 0; 946 else 947 return -1; 948 } 949 #endif 950 951 #ifdef CONFIG_TI_SECURE_DEVICE 952 void board_fit_image_post_process(void **p_image, size_t *p_size) 953 { 954 secure_boot_verify_image(p_image, p_size); 955 } 956 #endif 957 958 #if !CONFIG_IS_ENABLED(OF_CONTROL) 959 static const struct omap_hsmmc_plat am335x_mmc0_platdata = { 960 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, 961 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, 962 .cfg.f_min = 400000, 963 .cfg.f_max = 52000000, 964 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, 965 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 966 }; 967 968 U_BOOT_DEVICE(am335x_mmc0) = { 969 .name = "omap_hsmmc", 970 .platdata = &am335x_mmc0_platdata, 971 }; 972 973 static const struct omap_hsmmc_plat am335x_mmc1_platdata = { 974 .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE, 975 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT, 976 .cfg.f_min = 400000, 977 .cfg.f_max = 52000000, 978 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, 979 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 980 }; 981 982 U_BOOT_DEVICE(am335x_mmc1) = { 983 .name = "omap_hsmmc", 984 .platdata = &am335x_mmc1_platdata, 985 }; 986 #endif 987