1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <serial.h> 15 #include <asm/arch/cpu.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/omap.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/clk_synthesizer.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc_host_def.h> 23 #include <asm/arch/sys_proto.h> 24 #include <asm/arch/mem.h> 25 #include <asm/io.h> 26 #include <asm/emif.h> 27 #include <asm/gpio.h> 28 #include <i2c.h> 29 #include <miiphy.h> 30 #include <cpsw.h> 31 #include <power/tps65217.h> 32 #include <power/tps65910.h> 33 #include <environment.h> 34 #include <watchdog.h> 35 #include <environment.h> 36 #include "../common/board_detect.h" 37 #include "board.h" 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 /* GPIO that controls power to DDR on EVM-SK */ 42 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 43 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) 44 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) 45 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) 46 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) 47 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) 48 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) 49 50 #if defined(CONFIG_SPL_BUILD) || \ 51 (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) 52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 53 #endif 54 55 /* 56 * Read header information from EEPROM into global structure. 57 */ 58 static inline int __maybe_unused read_eeprom(void) 59 { 60 return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR); 61 } 62 63 #ifndef CONFIG_DM_SERIAL 64 struct serial_device *default_serial_console(void) 65 { 66 if (board_is_icev2()) 67 return &eserial4_device; 68 else 69 return &eserial1_device; 70 } 71 #endif 72 73 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 74 static const struct ddr_data ddr2_data = { 75 .datardsratio0 = MT47H128M16RT25E_RD_DQS, 76 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, 77 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, 78 }; 79 80 static const struct cmd_control ddr2_cmd_ctrl_data = { 81 .cmd0csratio = MT47H128M16RT25E_RATIO, 82 83 .cmd1csratio = MT47H128M16RT25E_RATIO, 84 85 .cmd2csratio = MT47H128M16RT25E_RATIO, 86 }; 87 88 static const struct emif_regs ddr2_emif_reg_data = { 89 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 90 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 91 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 92 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 93 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 94 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 95 }; 96 97 static const struct ddr_data ddr3_data = { 98 .datardsratio0 = MT41J128MJT125_RD_DQS, 99 .datawdsratio0 = MT41J128MJT125_WR_DQS, 100 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 101 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 102 }; 103 104 static const struct ddr_data ddr3_beagleblack_data = { 105 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 106 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 107 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 108 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 109 }; 110 111 static const struct ddr_data ddr3_evm_data = { 112 .datardsratio0 = MT41J512M8RH125_RD_DQS, 113 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 114 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 115 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 116 }; 117 118 static const struct ddr_data ddr3_icev2_data = { 119 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, 120 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, 121 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, 122 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, 123 }; 124 125 static const struct cmd_control ddr3_cmd_ctrl_data = { 126 .cmd0csratio = MT41J128MJT125_RATIO, 127 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 128 129 .cmd1csratio = MT41J128MJT125_RATIO, 130 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 131 132 .cmd2csratio = MT41J128MJT125_RATIO, 133 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 134 }; 135 136 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 137 .cmd0csratio = MT41K256M16HA125E_RATIO, 138 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 139 140 .cmd1csratio = MT41K256M16HA125E_RATIO, 141 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 142 143 .cmd2csratio = MT41K256M16HA125E_RATIO, 144 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 145 }; 146 147 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 148 .cmd0csratio = MT41J512M8RH125_RATIO, 149 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 150 151 .cmd1csratio = MT41J512M8RH125_RATIO, 152 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 153 154 .cmd2csratio = MT41J512M8RH125_RATIO, 155 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 156 }; 157 158 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { 159 .cmd0csratio = MT41J128MJT125_RATIO_400MHz, 160 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 161 162 .cmd1csratio = MT41J128MJT125_RATIO_400MHz, 163 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 164 165 .cmd2csratio = MT41J128MJT125_RATIO_400MHz, 166 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 167 }; 168 169 static struct emif_regs ddr3_emif_reg_data = { 170 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 171 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 172 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 173 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 174 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 175 .zq_config = MT41J128MJT125_ZQ_CFG, 176 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 177 PHY_EN_DYN_PWRDN, 178 }; 179 180 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 181 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 182 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 183 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 184 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 185 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 186 .zq_config = MT41K256M16HA125E_ZQ_CFG, 187 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 188 }; 189 190 static struct emif_regs ddr3_evm_emif_reg_data = { 191 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 192 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 193 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 194 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 195 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 196 .zq_config = MT41J512M8RH125_ZQ_CFG, 197 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 198 PHY_EN_DYN_PWRDN, 199 }; 200 201 static struct emif_regs ddr3_icev2_emif_reg_data = { 202 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, 203 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, 204 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, 205 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, 206 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, 207 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, 208 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | 209 PHY_EN_DYN_PWRDN, 210 }; 211 212 #ifdef CONFIG_SPL_OS_BOOT 213 int spl_start_uboot(void) 214 { 215 /* break into full u-boot on 'c' */ 216 if (serial_tstc() && serial_getc() == 'c') 217 return 1; 218 219 #ifdef CONFIG_SPL_ENV_SUPPORT 220 env_init(); 221 env_relocate_spec(); 222 if (getenv_yesno("boot_os") != 1) 223 return 1; 224 #endif 225 226 return 0; 227 } 228 #endif 229 230 #define OSC (V_OSCK/1000000) 231 const struct dpll_params dpll_ddr = { 232 266, OSC-1, 1, -1, -1, -1, -1}; 233 const struct dpll_params dpll_ddr_evm_sk = { 234 303, OSC-1, 1, -1, -1, -1, -1}; 235 const struct dpll_params dpll_ddr_bone_black = { 236 400, OSC-1, 1, -1, -1, -1, -1}; 237 238 void am33xx_spl_board_init(void) 239 { 240 int mpu_vdd; 241 242 if (read_eeprom() < 0) 243 puts("Could not get board ID.\n"); 244 245 /* Get the frequency */ 246 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 247 248 if (board_is_bone() || board_is_bone_lt()) { 249 /* BeagleBone PMIC Code */ 250 int usb_cur_lim; 251 252 /* 253 * Only perform PMIC configurations if board rev > A1 254 * on Beaglebone White 255 */ 256 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) 257 return; 258 259 if (i2c_probe(TPS65217_CHIP_PM)) 260 return; 261 262 /* 263 * On Beaglebone White we need to ensure we have AC power 264 * before increasing the frequency. 265 */ 266 if (board_is_bone()) { 267 uchar pmic_status_reg; 268 if (tps65217_reg_read(TPS65217_STATUS, 269 &pmic_status_reg)) 270 return; 271 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 272 puts("No AC power, disabling frequency switch\n"); 273 return; 274 } 275 } 276 277 /* 278 * Override what we have detected since we know if we have 279 * a Beaglebone Black it supports 1GHz. 280 */ 281 if (board_is_bone_lt()) 282 dpll_mpu_opp100.m = MPUPLL_M_1000; 283 284 /* 285 * Increase USB current limit to 1300mA or 1800mA and set 286 * the MPU voltage controller as needed. 287 */ 288 if (dpll_mpu_opp100.m == MPUPLL_M_1000) { 289 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 290 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 291 } else { 292 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 293 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 294 } 295 296 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 297 TPS65217_POWER_PATH, 298 usb_cur_lim, 299 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 300 puts("tps65217_reg_write failure\n"); 301 302 /* Set DCDC3 (CORE) voltage to 1.125V */ 303 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 304 TPS65217_DCDC_VOLT_SEL_1125MV)) { 305 puts("tps65217_voltage_update failure\n"); 306 return; 307 } 308 309 /* Set CORE Frequencies to OPP100 */ 310 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 311 312 /* Set DCDC2 (MPU) voltage */ 313 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 314 puts("tps65217_voltage_update failure\n"); 315 return; 316 } 317 318 /* 319 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 320 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. 321 */ 322 if (board_is_bone()) { 323 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 324 TPS65217_DEFLS1, 325 TPS65217_LDO_VOLTAGE_OUT_3_3, 326 TPS65217_LDO_MASK)) 327 puts("tps65217_reg_write failure\n"); 328 } else { 329 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 330 TPS65217_DEFLS1, 331 TPS65217_LDO_VOLTAGE_OUT_1_8, 332 TPS65217_LDO_MASK)) 333 puts("tps65217_reg_write failure\n"); 334 } 335 336 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 337 TPS65217_DEFLS2, 338 TPS65217_LDO_VOLTAGE_OUT_3_3, 339 TPS65217_LDO_MASK)) 340 puts("tps65217_reg_write failure\n"); 341 } else { 342 int sil_rev; 343 344 /* 345 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 346 * MPU frequencies we support we use a CORE voltage of 347 * 1.1375V. For MPU voltage we need to switch based on 348 * the frequency we are running at. 349 */ 350 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 351 return; 352 353 /* 354 * Depending on MPU clock and PG we will need a different 355 * VDD to drive at that speed. 356 */ 357 sil_rev = readl(&cdev->deviceid) >> 28; 358 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, 359 dpll_mpu_opp100.m); 360 361 /* Tell the TPS65910 to use i2c */ 362 tps65910_set_i2c_control(); 363 364 /* First update MPU voltage. */ 365 if (tps65910_voltage_update(MPU, mpu_vdd)) 366 return; 367 368 /* Second, update the CORE voltage. */ 369 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) 370 return; 371 372 /* Set CORE Frequencies to OPP100 */ 373 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 374 } 375 376 /* Set MPU Frequency to what we detected now that voltages are set */ 377 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 378 } 379 380 const struct dpll_params *get_dpll_ddr_params(void) 381 { 382 enable_i2c0_pin_mux(); 383 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 384 if (read_eeprom() < 0) 385 puts("Could not get board ID.\n"); 386 387 if (board_is_evm_sk()) 388 return &dpll_ddr_evm_sk; 389 else if (board_is_bone_lt() || board_is_icev2()) 390 return &dpll_ddr_bone_black; 391 else if (board_is_evm_15_or_later()) 392 return &dpll_ddr_evm_sk; 393 else 394 return &dpll_ddr; 395 } 396 397 void set_uart_mux_conf(void) 398 { 399 #if CONFIG_CONS_INDEX == 1 400 enable_uart0_pin_mux(); 401 #elif CONFIG_CONS_INDEX == 2 402 enable_uart1_pin_mux(); 403 #elif CONFIG_CONS_INDEX == 3 404 enable_uart2_pin_mux(); 405 #elif CONFIG_CONS_INDEX == 4 406 enable_uart3_pin_mux(); 407 #elif CONFIG_CONS_INDEX == 5 408 enable_uart4_pin_mux(); 409 #elif CONFIG_CONS_INDEX == 6 410 enable_uart5_pin_mux(); 411 #endif 412 } 413 414 void set_mux_conf_regs(void) 415 { 416 if (read_eeprom() < 0) 417 puts("Could not get board ID.\n"); 418 419 enable_board_pin_mux(); 420 } 421 422 const struct ctrl_ioregs ioregs_evmsk = { 423 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 424 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 425 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 426 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 427 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 428 }; 429 430 const struct ctrl_ioregs ioregs_bonelt = { 431 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 432 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 433 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 434 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 435 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 436 }; 437 438 const struct ctrl_ioregs ioregs_evm15 = { 439 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 440 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 441 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, 442 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 443 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 444 }; 445 446 const struct ctrl_ioregs ioregs = { 447 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 448 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 449 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 450 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 451 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 452 }; 453 454 void sdram_init(void) 455 { 456 if (read_eeprom() < 0) 457 puts("Could not get board ID.\n"); 458 459 if (board_is_evm_sk()) { 460 /* 461 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 462 * This is safe enough to do on older revs. 463 */ 464 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 465 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 466 } 467 468 if (board_is_icev2()) { 469 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); 470 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); 471 } 472 473 if (board_is_evm_sk()) 474 config_ddr(303, &ioregs_evmsk, &ddr3_data, 475 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 476 else if (board_is_bone_lt()) 477 config_ddr(400, &ioregs_bonelt, 478 &ddr3_beagleblack_data, 479 &ddr3_beagleblack_cmd_ctrl_data, 480 &ddr3_beagleblack_emif_reg_data, 0); 481 else if (board_is_evm_15_or_later()) 482 config_ddr(303, &ioregs_evm15, &ddr3_evm_data, 483 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 484 else if (board_is_icev2()) 485 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, 486 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 487 0); 488 else 489 config_ddr(266, &ioregs, &ddr2_data, 490 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 491 } 492 #endif 493 494 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 495 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 496 static void request_and_set_gpio(int gpio, char *name) 497 { 498 int ret; 499 500 ret = gpio_request(gpio, name); 501 if (ret < 0) { 502 printf("%s: Unable to request %s\n", __func__, name); 503 return; 504 } 505 506 ret = gpio_direction_output(gpio, 0); 507 if (ret < 0) { 508 printf("%s: Unable to set %s as output\n", __func__, name); 509 goto err_free_gpio; 510 } 511 512 gpio_set_value(gpio, 1); 513 514 return; 515 516 err_free_gpio: 517 gpio_free(gpio); 518 } 519 520 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N); 521 522 /** 523 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock 524 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle 525 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to 526 * give 50MHz output for Eth0 and 1. 527 */ 528 static struct clk_synth cdce913_data = { 529 .id = 0x81, 530 .capacitor = 0x90, 531 .mux = 0x6d, 532 .pdiv2 = 0x2, 533 .pdiv3 = 0x2, 534 }; 535 #endif 536 537 /* 538 * Basic board specific setup. Pinmux has been handled already. 539 */ 540 int board_init(void) 541 { 542 #if defined(CONFIG_HW_WATCHDOG) 543 hw_watchdog_init(); 544 #endif 545 546 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 547 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 548 gpmc_init(); 549 #endif 550 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) 551 int rv; 552 553 if (board_is_icev2()) { 554 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); 555 REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL); 556 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); 557 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); 558 559 rv = setup_clock_synthesizer(&cdce913_data); 560 if (rv) { 561 printf("Clock synthesizer setup failed %d\n", rv); 562 return rv; 563 } 564 } 565 #endif 566 567 return 0; 568 } 569 570 #ifdef CONFIG_BOARD_LATE_INIT 571 int board_late_init(void) 572 { 573 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 574 int rc; 575 char *name = NULL; 576 577 rc = read_eeprom(); 578 if (rc) 579 puts("Could not get board ID.\n"); 580 581 if (board_is_bbg1()) 582 name = "BBG1"; 583 set_board_info_env(name); 584 #endif 585 586 return 0; 587 } 588 #endif 589 590 #ifndef CONFIG_DM_ETH 591 592 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 593 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 594 static void cpsw_control(int enabled) 595 { 596 /* VTP can be added here */ 597 598 return; 599 } 600 601 static struct cpsw_slave_data cpsw_slaves[] = { 602 { 603 .slave_reg_ofs = 0x208, 604 .sliver_reg_ofs = 0xd80, 605 .phy_addr = 0, 606 }, 607 { 608 .slave_reg_ofs = 0x308, 609 .sliver_reg_ofs = 0xdc0, 610 .phy_addr = 1, 611 }, 612 }; 613 614 static struct cpsw_platform_data cpsw_data = { 615 .mdio_base = CPSW_MDIO_BASE, 616 .cpsw_base = CPSW_BASE, 617 .mdio_div = 0xff, 618 .channels = 8, 619 .cpdma_reg_ofs = 0x800, 620 .slaves = 1, 621 .slave_data = cpsw_slaves, 622 .ale_reg_ofs = 0xd00, 623 .ale_entries = 1024, 624 .host_port_reg_ofs = 0x108, 625 .hw_stats_reg_ofs = 0x900, 626 .bd_ram_ofs = 0x2000, 627 .mac_control = (1 << 5), 628 .control = cpsw_control, 629 .host_port_num = 0, 630 .version = CPSW_CTRL_VERSION_2, 631 }; 632 #endif 633 634 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ 635 defined(CONFIG_SPL_BUILD)) || \ 636 ((defined(CONFIG_DRIVER_TI_CPSW) || \ 637 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ 638 !defined(CONFIG_SPL_BUILD)) 639 640 /* 641 * This function will: 642 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr 643 * in the environment 644 * Perform fixups to the PHY present on certain boards. We only need this 645 * function in: 646 * - SPL with either CPSW or USB ethernet support 647 * - Full U-Boot, with either CPSW or USB ethernet 648 * Build in only these cases to avoid warnings about unused variables 649 * when we build an SPL that has neither option but full U-Boot will. 650 */ 651 int board_eth_init(bd_t *bis) 652 { 653 int rv, n = 0; 654 uint8_t mac_addr[6]; 655 uint32_t mac_hi, mac_lo; 656 __maybe_unused struct ti_am_eeprom *header; 657 658 /* try reading mac address from efuse */ 659 mac_lo = readl(&cdev->macid0l); 660 mac_hi = readl(&cdev->macid0h); 661 mac_addr[0] = mac_hi & 0xFF; 662 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 663 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 664 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 665 mac_addr[4] = mac_lo & 0xFF; 666 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 667 668 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 669 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 670 if (!getenv("ethaddr")) { 671 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 672 673 if (is_valid_ethaddr(mac_addr)) 674 eth_setenv_enetaddr("ethaddr", mac_addr); 675 } 676 677 #ifdef CONFIG_DRIVER_TI_CPSW 678 679 mac_lo = readl(&cdev->macid1l); 680 mac_hi = readl(&cdev->macid1h); 681 mac_addr[0] = mac_hi & 0xFF; 682 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 683 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 684 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 685 mac_addr[4] = mac_lo & 0xFF; 686 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 687 688 if (!getenv("eth1addr")) { 689 if (is_valid_ethaddr(mac_addr)) 690 eth_setenv_enetaddr("eth1addr", mac_addr); 691 } 692 693 if (read_eeprom() < 0) 694 puts("Could not get board ID.\n"); 695 696 if (board_is_bone() || board_is_bone_lt() || 697 board_is_idk()) { 698 writel(MII_MODE_ENABLE, &cdev->miisel); 699 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 700 PHY_INTERFACE_MODE_MII; 701 } else if (board_is_icev2()) { 702 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 703 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 704 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; 705 cpsw_slaves[0].phy_addr = 1; 706 cpsw_slaves[1].phy_addr = 3; 707 } else { 708 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 709 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 710 PHY_INTERFACE_MODE_RGMII; 711 } 712 713 rv = cpsw_register(&cpsw_data); 714 if (rv < 0) 715 printf("Error %d registering CPSW switch\n", rv); 716 else 717 n += rv; 718 #endif 719 720 /* 721 * 722 * CPSW RGMII Internal Delay Mode is not supported in all PVT 723 * operating points. So we must set the TX clock delay feature 724 * in the AR8051 PHY. Since we only support a single ethernet 725 * device in U-Boot, we only do this for the first instance. 726 */ 727 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 728 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 729 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 730 #define AR8051_RGMII_TX_CLK_DLY 0x100 731 732 if (board_is_evm_sk() || board_is_gp_evm()) { 733 const char *devname; 734 devname = miiphy_get_current_dev(); 735 736 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 737 AR8051_DEBUG_RGMII_CLK_DLY_REG); 738 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 739 AR8051_RGMII_TX_CLK_DLY); 740 } 741 #endif 742 #if defined(CONFIG_USB_ETHER) && \ 743 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 744 if (is_valid_ethaddr(mac_addr)) 745 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 746 747 rv = usb_eth_initialize(bis); 748 if (rv < 0) 749 printf("Error %d registering USB_ETHER\n", rv); 750 else 751 n += rv; 752 #endif 753 return n; 754 } 755 #endif 756 757 #endif /* CONFIG_DM_ETH */ 758 759 #ifdef CONFIG_SPL_LOAD_FIT 760 int board_fit_config_name_match(const char *name) 761 { 762 if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) 763 return 0; 764 else if (board_is_bone() && !strcmp(name, "am335x-bone")) 765 return 0; 766 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) 767 return 0; 768 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) 769 return 0; 770 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) 771 return 0; 772 else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) 773 return 0; 774 else 775 return -1; 776 } 777 #endif 778