1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <common.h> 20 #include <errno.h> 21 #include <spl.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/hardware.h> 24 #include <asm/arch/omap.h> 25 #include <asm/arch/ddr_defs.h> 26 #include <asm/arch/clock.h> 27 #include <asm/arch/gpio.h> 28 #include <asm/arch/mmc_host_def.h> 29 #include <asm/arch/sys_proto.h> 30 #include <asm/io.h> 31 #include <asm/emif.h> 32 #include <asm/gpio.h> 33 #include <i2c.h> 34 #include <miiphy.h> 35 #include <cpsw.h> 36 #include "board.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 41 #ifdef CONFIG_SPL_BUILD 42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 43 #endif 44 45 /* MII mode defines */ 46 #define MII_MODE_ENABLE 0x0 47 #define RGMII_MODE_ENABLE 0x3A 48 49 /* GPIO that controls power to DDR on EVM-SK */ 50 #define GPIO_DDR_VTT_EN 7 51 52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 53 54 static struct am335x_baseboard_id __attribute__((section (".data"))) header; 55 56 static inline int board_is_bone(void) 57 { 58 return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); 59 } 60 61 static inline int board_is_bone_lt(void) 62 { 63 return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); 64 } 65 66 static inline int board_is_evm_sk(void) 67 { 68 return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); 69 } 70 71 static inline int board_is_idk(void) 72 { 73 return !strncmp(header.config, "SKU#02", 6); 74 } 75 76 static int board_is_gp_evm(void) 77 { 78 return !strncmp("A33515BB", header.name, 8); 79 } 80 81 int board_is_evm_15_or_later(void) 82 { 83 return (!strncmp("A33515BB", header.name, 8) && 84 strncmp("1.5", header.version, 3) <= 0); 85 } 86 87 /* 88 * Read header information from EEPROM into global structure. 89 */ 90 static int read_eeprom(void) 91 { 92 /* Check if baseboard eeprom is available */ 93 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 94 puts("Could not probe the EEPROM; something fundamentally " 95 "wrong on the I2C bus.\n"); 96 return -ENODEV; 97 } 98 99 /* read the eeprom using i2c */ 100 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, 101 sizeof(header))) { 102 puts("Could not read the EEPROM; something fundamentally" 103 " wrong on the I2C bus.\n"); 104 return -EIO; 105 } 106 107 if (header.magic != 0xEE3355AA) { 108 /* 109 * read the eeprom using i2c again, 110 * but use only a 1 byte address 111 */ 112 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, 113 (uchar *)&header, sizeof(header))) { 114 puts("Could not read the EEPROM; something " 115 "fundamentally wrong on the I2C bus.\n"); 116 return -EIO; 117 } 118 119 if (header.magic != 0xEE3355AA) { 120 printf("Incorrect magic number (0x%x) in EEPROM\n", 121 header.magic); 122 return -EINVAL; 123 } 124 } 125 126 return 0; 127 } 128 129 /* UART Defines */ 130 #ifdef CONFIG_SPL_BUILD 131 #define UART_RESET (0x1 << 1) 132 #define UART_CLK_RUNNING_MASK 0x1 133 #define UART_SMART_IDLE_EN (0x1 << 0x3) 134 135 static void rtc32k_enable(void) 136 { 137 struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; 138 139 /* 140 * Unlock the RTC's registers. For more details please see the 141 * RTC_SS section of the TRM. In order to unlock we need to 142 * write these specific values (keys) in this order. 143 */ 144 writel(0x83e70b13, &rtc->kick0r); 145 writel(0x95a4f1e0, &rtc->kick1r); 146 147 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 148 writel((1 << 3) | (1 << 6), &rtc->osc); 149 } 150 151 static const struct ddr_data ddr2_data = { 152 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 153 (MT47H128M16RT25E_RD_DQS<<20) | 154 (MT47H128M16RT25E_RD_DQS<<10) | 155 (MT47H128M16RT25E_RD_DQS<<0)), 156 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 157 (MT47H128M16RT25E_WR_DQS<<20) | 158 (MT47H128M16RT25E_WR_DQS<<10) | 159 (MT47H128M16RT25E_WR_DQS<<0)), 160 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 161 (MT47H128M16RT25E_PHY_WRLVL<<20) | 162 (MT47H128M16RT25E_PHY_WRLVL<<10) | 163 (MT47H128M16RT25E_PHY_WRLVL<<0)), 164 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 165 (MT47H128M16RT25E_PHY_GATELVL<<20) | 166 (MT47H128M16RT25E_PHY_GATELVL<<10) | 167 (MT47H128M16RT25E_PHY_GATELVL<<0)), 168 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 169 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 170 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 171 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 172 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 173 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 174 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 175 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 176 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, 177 .datadldiff0 = PHY_DLL_LOCK_DIFF, 178 }; 179 180 static const struct cmd_control ddr2_cmd_ctrl_data = { 181 .cmd0csratio = MT47H128M16RT25E_RATIO, 182 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 183 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 184 185 .cmd1csratio = MT47H128M16RT25E_RATIO, 186 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 187 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 188 189 .cmd2csratio = MT47H128M16RT25E_RATIO, 190 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 191 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 192 }; 193 194 static const struct emif_regs ddr2_emif_reg_data = { 195 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 196 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 197 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 198 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 199 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 200 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 201 }; 202 203 static const struct ddr_data ddr3_data = { 204 .datardsratio0 = MT41J128MJT125_RD_DQS, 205 .datawdsratio0 = MT41J128MJT125_WR_DQS, 206 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 207 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 208 .datadldiff0 = PHY_DLL_LOCK_DIFF, 209 }; 210 211 static const struct ddr_data ddr3_evm_data = { 212 .datardsratio0 = MT41J512M8RH125_RD_DQS, 213 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 214 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 215 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 216 .datadldiff0 = PHY_DLL_LOCK_DIFF, 217 }; 218 219 static const struct cmd_control ddr3_cmd_ctrl_data = { 220 .cmd0csratio = MT41J128MJT125_RATIO, 221 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 222 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 223 224 .cmd1csratio = MT41J128MJT125_RATIO, 225 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 226 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 227 228 .cmd2csratio = MT41J128MJT125_RATIO, 229 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 230 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 231 }; 232 233 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 234 .cmd0csratio = MT41J512M8RH125_RATIO, 235 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 236 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 237 238 .cmd1csratio = MT41J512M8RH125_RATIO, 239 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 240 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 241 242 .cmd2csratio = MT41J512M8RH125_RATIO, 243 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 244 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 245 }; 246 247 static struct emif_regs ddr3_emif_reg_data = { 248 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 249 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 250 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 251 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 252 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 253 .zq_config = MT41J128MJT125_ZQ_CFG, 254 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, 255 }; 256 257 static struct emif_regs ddr3_evm_emif_reg_data = { 258 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 259 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 260 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 261 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 262 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 263 .zq_config = MT41J512M8RH125_ZQ_CFG, 264 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY, 265 }; 266 #endif 267 268 /* 269 * early system init of muxing and clocks. 270 */ 271 void s_init(void) 272 { 273 /* WDT1 is already running when the bootloader gets control 274 * Disable it to avoid "random" resets 275 */ 276 writel(0xAAAA, &wdtimer->wdtwspr); 277 while (readl(&wdtimer->wdtwwps) != 0x0) 278 ; 279 writel(0x5555, &wdtimer->wdtwspr); 280 while (readl(&wdtimer->wdtwwps) != 0x0) 281 ; 282 283 #ifdef CONFIG_SPL_BUILD 284 /* Setup the PLLs and the clocks for the peripherals */ 285 pll_init(); 286 287 /* Enable RTC32K clock */ 288 rtc32k_enable(); 289 290 /* UART softreset */ 291 u32 regVal; 292 293 #ifdef CONFIG_SERIAL1 294 enable_uart0_pin_mux(); 295 #endif /* CONFIG_SERIAL1 */ 296 #ifdef CONFIG_SERIAL2 297 enable_uart1_pin_mux(); 298 #endif /* CONFIG_SERIAL2 */ 299 #ifdef CONFIG_SERIAL3 300 enable_uart2_pin_mux(); 301 #endif /* CONFIG_SERIAL3 */ 302 #ifdef CONFIG_SERIAL4 303 enable_uart3_pin_mux(); 304 #endif /* CONFIG_SERIAL4 */ 305 #ifdef CONFIG_SERIAL5 306 enable_uart4_pin_mux(); 307 #endif /* CONFIG_SERIAL5 */ 308 #ifdef CONFIG_SERIAL6 309 enable_uart5_pin_mux(); 310 #endif /* CONFIG_SERIAL6 */ 311 312 regVal = readl(&uart_base->uartsyscfg); 313 regVal |= UART_RESET; 314 writel(regVal, &uart_base->uartsyscfg); 315 while ((readl(&uart_base->uartsyssts) & 316 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 317 ; 318 319 /* Disable smart idle */ 320 regVal = readl(&uart_base->uartsyscfg); 321 regVal |= UART_SMART_IDLE_EN; 322 writel(regVal, &uart_base->uartsyscfg); 323 324 gd = &gdata; 325 326 preloader_console_init(); 327 328 /* Initalize the board header */ 329 enable_i2c0_pin_mux(); 330 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 331 if (read_eeprom() < 0) 332 puts("Could not get board ID.\n"); 333 334 enable_board_pin_mux(&header); 335 if (board_is_evm_sk()) { 336 /* 337 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 338 * This is safe enough to do on older revs. 339 */ 340 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 341 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 342 } 343 344 if (board_is_evm_sk() || board_is_bone_lt()) 345 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 346 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); 347 else if (board_is_evm_15_or_later()) 348 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, 349 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data); 350 else 351 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 352 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); 353 #endif 354 } 355 356 /* 357 * Basic board specific setup. Pinmux has been handled already. 358 */ 359 int board_init(void) 360 { 361 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 362 if (read_eeprom() < 0) 363 puts("Could not get board ID.\n"); 364 365 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 366 367 gpmc_init(); 368 369 return 0; 370 } 371 372 #ifdef CONFIG_BOARD_LATE_INIT 373 int board_late_init(void) 374 { 375 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 376 char safe_string[HDR_NAME_LEN + 1]; 377 378 /* Now set variables based on the header. */ 379 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 380 safe_string[sizeof(header.name)] = 0; 381 setenv("board_name", safe_string); 382 383 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 384 safe_string[sizeof(header.version)] = 0; 385 setenv("board_rev", safe_string); 386 #endif 387 388 return 0; 389 } 390 #endif 391 392 #ifdef CONFIG_DRIVER_TI_CPSW 393 static void cpsw_control(int enabled) 394 { 395 /* VTP can be added here */ 396 397 return; 398 } 399 400 static struct cpsw_slave_data cpsw_slaves[] = { 401 { 402 .slave_reg_ofs = 0x208, 403 .sliver_reg_ofs = 0xd80, 404 .phy_id = 0, 405 }, 406 { 407 .slave_reg_ofs = 0x308, 408 .sliver_reg_ofs = 0xdc0, 409 .phy_id = 1, 410 }, 411 }; 412 413 static struct cpsw_platform_data cpsw_data = { 414 .mdio_base = AM335X_CPSW_MDIO_BASE, 415 .cpsw_base = AM335X_CPSW_BASE, 416 .mdio_div = 0xff, 417 .channels = 8, 418 .cpdma_reg_ofs = 0x800, 419 .slaves = 1, 420 .slave_data = cpsw_slaves, 421 .ale_reg_ofs = 0xd00, 422 .ale_entries = 1024, 423 .host_port_reg_ofs = 0x108, 424 .hw_stats_reg_ofs = 0x900, 425 .mac_control = (1 << 5), 426 .control = cpsw_control, 427 .host_port_num = 0, 428 .version = CPSW_CTRL_VERSION_2, 429 }; 430 #endif 431 432 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 433 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 434 int board_eth_init(bd_t *bis) 435 { 436 int rv, n = 0; 437 #ifdef CONFIG_DRIVER_TI_CPSW 438 uint8_t mac_addr[6]; 439 uint32_t mac_hi, mac_lo; 440 441 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 442 printf("<ethaddr> not set. Reading from E-fuse\n"); 443 /* try reading mac address from efuse */ 444 mac_lo = readl(&cdev->macid0l); 445 mac_hi = readl(&cdev->macid0h); 446 mac_addr[0] = mac_hi & 0xFF; 447 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 448 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 449 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 450 mac_addr[4] = mac_lo & 0xFF; 451 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 452 453 if (is_valid_ether_addr(mac_addr)) 454 eth_setenv_enetaddr("ethaddr", mac_addr); 455 else 456 goto try_usbether; 457 } 458 459 if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { 460 writel(MII_MODE_ENABLE, &cdev->miisel); 461 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 462 PHY_INTERFACE_MODE_MII; 463 } else { 464 writel(RGMII_MODE_ENABLE, &cdev->miisel); 465 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 466 PHY_INTERFACE_MODE_RGMII; 467 } 468 469 rv = cpsw_register(&cpsw_data); 470 if (rv < 0) 471 printf("Error %d registering CPSW switch\n", rv); 472 else 473 n += rv; 474 475 /* 476 * 477 * CPSW RGMII Internal Delay Mode is not supported in all PVT 478 * operating points. So we must set the TX clock delay feature 479 * in the AR8051 PHY. Since we only support a single ethernet 480 * device in U-Boot, we only do this for the first instance. 481 */ 482 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 483 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 484 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 485 #define AR8051_RGMII_TX_CLK_DLY 0x100 486 487 if (board_is_evm_sk() || board_is_gp_evm()) { 488 const char *devname; 489 devname = miiphy_get_current_dev(); 490 491 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 492 AR8051_DEBUG_RGMII_CLK_DLY_REG); 493 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 494 AR8051_RGMII_TX_CLK_DLY); 495 } 496 #endif 497 try_usbether: 498 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) 499 rv = usb_eth_initialize(bis); 500 if (rv < 0) 501 printf("Error %d registering USB_ETHER\n", rv); 502 else 503 n += rv; 504 #endif 505 return n; 506 } 507 #endif 508