1 /* 2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/soc.h> 11 #include <linux/mbus.h> 12 #ifdef CONFIG_NET 13 #include <netdev.h> 14 #endif 15 #include "theadorable.h" 16 17 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" 18 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780 23 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0 24 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0)) 25 26 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f 27 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c 28 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000 29 30 /* DDR3 static configuration */ 31 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { 32 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */ 33 {0x00001404, 0x30000800}, /* Dunit Control Low Register */ 34 {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */ 35 {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */ 36 {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */ 37 {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */ 38 {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */ 39 {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */ 40 {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */ 41 42 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ 43 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ 44 {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */ 45 {0x000014A8, 0x00000101}, /* AXI Control Register */ 46 47 /* 48 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the 49 * training sequence 50 */ 51 {0x000200e8, 0x3fff0e01}, 52 {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */ 53 54 {0x0001504, 0x7fffffe1}, /* CS0 Size */ 55 {0x000150C, 0x00000000}, /* CS1 Size */ 56 {0x0001514, 0x00000000}, /* CS2 Size */ 57 {0x000151C, 0x00000000}, /* CS3 Size */ 58 59 {0x00020220, 0x00000007}, /* Reserved */ 60 61 {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */ 62 {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */ 63 64 {0x000015D0, 0x00000650}, /* MR0 */ 65 {0x000015D4, 0x00000044}, /* MR1 */ 66 {0x000015D8, 0x00000010}, /* MR2 */ 67 {0x000015DC, 0x00000000}, /* MR3 */ 68 {0x000015E0, 0x00000001}, 69 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ 70 {0x000015EC, 0xf800a225}, /* DDR PHY */ 71 72 /* Recommended Settings from Marvell for 4 x 16 bit devices: */ 73 {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/ 74 {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */ 75 76 {0x0, 0x0} 77 }; 78 79 static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = { 80 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL}, 81 }; 82 83 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; 84 85 /* 86 * Lane0 - PCIE0.0 X1 (to WIFI Module) 87 * Lane5 - SATA0 88 * Lane6 - SATA1 89 * Lane7 - SGMII0 (to Ethernet Phy) 90 * Lane8-11 - PCIE2.0 X4 (to PEX Switch) 91 * all other lanes are disabled 92 */ 93 MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { 94 { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111, 95 { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, 96 PEX_BUS_DISABLED }, 97 0x0060, serdes_change_m_phy 98 }, 99 }; 100 101 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) 102 { 103 /* Only one mode supported for this board */ 104 return &board_ddr_modes[0]; 105 } 106 107 MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) 108 { 109 return &theadorable_serdes_cfg[0]; 110 } 111 112 int board_early_init_f(void) 113 { 114 /* Configure MPP */ 115 writel(0x00000000, MVEBU_MPP_BASE + 0x00); 116 writel(0x03300000, MVEBU_MPP_BASE + 0x04); 117 writel(0x00000033, MVEBU_MPP_BASE + 0x08); 118 writel(0x00000000, MVEBU_MPP_BASE + 0x0c); 119 writel(0x11110000, MVEBU_MPP_BASE + 0x10); 120 writel(0x00221100, MVEBU_MPP_BASE + 0x14); 121 writel(0x00000000, MVEBU_MPP_BASE + 0x18); 122 writel(0x00000000, MVEBU_MPP_BASE + 0x1c); 123 writel(0x00000000, MVEBU_MPP_BASE + 0x20); 124 125 /* Configure GPIO */ 126 writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 127 writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 128 writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 129 writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 130 writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); 131 writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); 132 133 return 0; 134 } 135 136 int board_init(void) 137 { 138 /* adress of boot parameters */ 139 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 140 141 /* 142 * Map SPI devices via MBUS so that they can be accessed via 143 * the SPI direct access mode 144 */ 145 mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE, 146 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1); 147 mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE, 148 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2); 149 150 return 0; 151 } 152 153 int checkboard(void) 154 { 155 puts("Board: theadorable\n"); 156 157 board_fpga_add(); 158 159 return 0; 160 } 161 162 #ifdef CONFIG_NET 163 int board_eth_init(bd_t *bis) 164 { 165 cpu_eth_init(bis); /* Built in controller(s) come first */ 166 return pci_eth_init(bis); 167 } 168 #endif 169 170 int board_video_init(void) 171 { 172 struct mvebu_lcd_info lcd_info; 173 174 /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */ 175 lcd_info.fb_base = gd->ram_size; 176 lcd_info.x_res = 240; 177 lcd_info.x_fp = 1; 178 lcd_info.x_bp = 45; 179 lcd_info.y_res = 320; 180 lcd_info.y_fp = 1; 181 lcd_info.y_bp = 3; 182 183 return mvebu_lcd_register_init(&lcd_info); 184 } 185