1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <common.h> 7 #include <altera.h> 8 #include <errno.h> 9 #include <asm/gpio.h> 10 #include <asm/io.h> 11 #include <asm/arch/cpu.h> 12 #include <asm/arch/soc.h> 13 #include <asm/arch-mvebu/spi.h> 14 #include "theadorable.h" 15 16 /* 17 * FPGA programming support 18 */ 19 static int fpga_pre_fn(int cookie) 20 { 21 int gpio_config = COOKIE2CONFIG(cookie); 22 int gpio_done = COOKIE2DONE(cookie); 23 int ret; 24 25 debug("%s (%d): cookie=%08x gpio_config=%d gpio_done=%d\n", 26 __func__, __LINE__, cookie, gpio_config, gpio_done); 27 28 /* Configure config pin */ 29 /* Set to output */ 30 ret = gpio_request(gpio_config, "CONFIG"); 31 if (ret < 0) 32 return ret; 33 gpio_direction_output(gpio_config, 1); 34 35 /* Configure done pin */ 36 /* Set to input */ 37 ret = gpio_request(gpio_done, "DONE"); 38 if (ret < 0) 39 return ret; 40 41 gpio_direction_input(gpio_done); 42 43 return 0; 44 } 45 46 static int fpga_config_fn(int assert, int flush, int cookie) 47 { 48 int gpio_config = COOKIE2CONFIG(cookie); 49 50 debug("%s (%d): cookie=%08x gpio_config=%d\n", 51 __func__, __LINE__, cookie, gpio_config); 52 53 if (assert) 54 gpio_set_value(gpio_config, 1); 55 else 56 gpio_set_value(gpio_config, 0); 57 58 return 0; 59 } 60 61 static int fpga_write_fn(const void *buf, size_t len, int flush, int cookie) 62 { 63 int spi_bus = COOKIE2SPI_BUS(cookie); 64 int spi_dev = COOKIE2SPI_DEV(cookie); 65 struct kwspi_registers *reg; 66 u32 control_reg; 67 u32 config_reg; 68 void *dst; 69 70 /* 71 * Write data to FPGA attached to SPI bus via SPI direct write. 72 * This results in the fastest and easiest way to program the 73 * bitstream into the FPGA. 74 */ 75 debug("%s (%d): cookie=%08x spi_bus=%d spi_dev=%d\n", 76 __func__, __LINE__, cookie, spi_bus, spi_dev); 77 78 if (spi_bus == 0) { 79 reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10600); 80 dst = (void *)SPI_BUS0_DEV1_BASE; 81 } else { 82 reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10680); 83 dst = (void *)SPI_BUS1_DEV2_BASE; 84 } 85 86 /* Configure SPI controller for direct access mode */ 87 control_reg = readl(®->ctrl); 88 config_reg = readl(®->cfg); 89 writel(0x00000214, ®->cfg); /* 27MHz clock */ 90 writel(0x00000000, ®->dw_cfg); /* don't de-asset CS */ 91 writel(KWSPI_CSN_ACT, ®->ctrl); /* activate CS */ 92 93 /* Copy data to the SPI direct mapped window */ 94 memcpy(dst, buf, len); 95 96 /* Restore original register values */ 97 writel(control_reg, ®->ctrl); 98 writel(config_reg, ®->cfg); 99 100 return 0; 101 } 102 103 /* Returns the state of CONF_DONE Pin */ 104 static int fpga_done_fn(int cookie) 105 { 106 int gpio_done = COOKIE2DONE(cookie); 107 unsigned long ts; 108 109 debug("%s (%d): cookie=%08x gpio_done=%d\n", 110 __func__, __LINE__, cookie, gpio_done); 111 112 ts = get_timer(0); 113 do { 114 if (gpio_get_value(gpio_done)) 115 return 0; 116 } while (get_timer(ts) < 1000); 117 118 /* timeout so return error */ 119 return -ENODEV; 120 } 121 122 static altera_board_specific_func stratixv_fns = { 123 .pre = fpga_pre_fn, 124 .config = fpga_config_fn, 125 .write = fpga_write_fn, 126 .done = fpga_done_fn, 127 }; 128 129 static Altera_desc altera_fpga[] = { 130 { 131 /* Family */ 132 Altera_StratixV, 133 /* Interface type */ 134 passive_serial, 135 /* No limitation as additional data will be ignored */ 136 -1, 137 /* Device function table */ 138 (void *)&stratixv_fns, 139 /* Base interface address specified in driver */ 140 NULL, 141 /* Cookie implementation */ 142 /* 143 * In this 32bit word the following information is coded: 144 * Bit 31 ... Bit 0 145 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin 146 */ 147 FPGA_COOKIE(0, 1, 26, 7) 148 }, 149 { 150 /* Family */ 151 Altera_StratixV, 152 /* Interface type */ 153 passive_serial, 154 /* No limitation as additional data will be ignored */ 155 -1, 156 /* Device function table */ 157 (void *)&stratixv_fns, 158 /* Base interface address specified in driver */ 159 NULL, 160 /* Cookie implementation */ 161 /* 162 * In this 32bit word the following information is coded: 163 * Bit 31 ... Bit 0 164 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin 165 */ 166 FPGA_COOKIE(1, 2, 29, 9) 167 }, 168 }; 169 170 /* Add device descriptor to FPGA device table */ 171 void board_fpga_add(void) 172 { 173 int i; 174 175 fpga_init(); 176 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 177 fpga_add(fpga_altera, &altera_fpga[i]); 178 } 179