1 /*
2  * Altera SoCFPGA SDRAM configuration
3  *
4  * SPDX-License-Identifier:    BSD-3-Clause
5  */
6 #ifndef __SDRAM_CONFIG_H
7 #define __SDRAM_CONFIG_H
8 
9 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
10 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
11 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
12 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
13 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
18 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			7
19 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
20 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
21 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
22 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			15
23 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			120
24 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
25 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
26 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
27 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
28 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
29 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
34 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
35 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
36 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
37 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
38 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
39 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
40 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
41 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
42 #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
44 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
45 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
46 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
47 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
48 #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
49 #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
50 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
51 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
52 #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
53 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
54 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
55 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
56 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
57 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
58 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
59 
60 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
61 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
62 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
63 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
64 #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
65 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
66 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
67 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
68 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
69 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
70 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
71 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
72 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
73 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
74 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
75 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
76 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED	0x1
77 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED	0x1
78 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED	0x3
79 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x311
80 
81 /* Sequencer auto configuration */
82 #define RW_MGR_ACTIVATE_0_AND_1 0x0D
83 #define RW_MGR_ACTIVATE_0_AND_1_WAIT1   0x0E
84 #define RW_MGR_ACTIVATE_0_AND_1_WAIT2   0x10
85 #define RW_MGR_ACTIVATE_1       0x0F
86 #define RW_MGR_CLEAR_DQS_ENABLE 0x49
87 #define RW_MGR_GUARANTEED_READ  0x4C
88 #define RW_MGR_GUARANTEED_READ_CONT     0x54
89 #define RW_MGR_GUARANTEED_WRITE 0x18
90 #define RW_MGR_GUARANTEED_WRITE_WAIT0   0x1B
91 #define RW_MGR_GUARANTEED_WRITE_WAIT1   0x1F
92 #define RW_MGR_GUARANTEED_WRITE_WAIT2   0x19
93 #define RW_MGR_GUARANTEED_WRITE_WAIT3   0x1D
94 #define RW_MGR_IDLE     0x00
95 #define RW_MGR_IDLE_LOOP1       0x7B
96 #define RW_MGR_IDLE_LOOP2       0x7A
97 #define RW_MGR_INIT_RESET_0_CKE_0       0x6F
98 #define RW_MGR_INIT_RESET_1_CKE_0       0x74
99 #define RW_MGR_LFSR_WR_RD_BANK_0        0x22
100 #define RW_MGR_LFSR_WR_RD_BANK_0_DATA   0x25
101 #define RW_MGR_LFSR_WR_RD_BANK_0_DQS    0x24
102 #define RW_MGR_LFSR_WR_RD_BANK_0_NOP    0x23
103 #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT   0x32
104 #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1   0x21
105 #define RW_MGR_LFSR_WR_RD_DM_BANK_0     0x36
106 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA        0x39
107 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
108 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
109 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT        0x46
110 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1        0x35
111 #define RW_MGR_MRS0_DLL_RESET   0x02
112 #define RW_MGR_MRS0_DLL_RESET_MIRR      0x08
113 #define RW_MGR_MRS0_USER        0x07
114 #define RW_MGR_MRS0_USER_MIRR   0x0C
115 #define RW_MGR_MRS1     0x03
116 #define RW_MGR_MRS1_MIRR        0x09
117 #define RW_MGR_MRS2     0x04
118 #define RW_MGR_MRS2_MIRR        0x0A
119 #define RW_MGR_MRS3     0x05
120 #define RW_MGR_MRS3_MIRR        0x0B
121 #define RW_MGR_PRECHARGE_ALL    0x12
122 #define RW_MGR_READ_B2B 0x59
123 #define RW_MGR_READ_B2B_WAIT1   0x61
124 #define RW_MGR_READ_B2B_WAIT2   0x6B
125 #define RW_MGR_REFRESH_ALL      0x14
126 #define RW_MGR_RETURN   0x01
127 #define RW_MGR_SGLE_READ        0x7D
128 #define RW_MGR_ZQCL     0x06
129 
130 /* Sequencer defines configuration */
131 #define AFI_RATE_RATIO  1
132 #define CALIB_LFIFO_OFFSET      8
133 #define CALIB_VFIFO_OFFSET      6
134 #define ENABLE_SUPER_QUICK_CALIBRATION  0
135 #define IO_DELAY_PER_DCHAIN_TAP 25
136 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP  25
137 #define IO_DELAY_PER_OPA_TAP    312
138 #define IO_DLL_CHAIN_LENGTH     8
139 #define IO_DQDQS_OUT_PHASE_MAX  0
140 #define IO_DQS_EN_DELAY_MAX     31
141 #define IO_DQS_EN_DELAY_OFFSET  0
142 #define IO_DQS_EN_PHASE_MAX     7
143 #define IO_DQS_IN_DELAY_MAX     31
144 #define IO_DQS_IN_RESERVE       4
145 #define IO_DQS_OUT_RESERVE      4
146 #define IO_IO_IN_DELAY_MAX      31
147 #define IO_IO_OUT1_DELAY_MAX    31
148 #define IO_IO_OUT2_DELAY_MAX    0
149 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS  0
150 #define MAX_LATENCY_COUNT_WIDTH 5
151 #define READ_VALID_FIFO_SIZE    16
152 #define REG_FILE_INIT_SEQ_SIGNATURE     0x5555048d
153 #define RW_MGR_MEM_ADDRESS_MIRRORING    0
154 #define RW_MGR_MEM_DATA_MASK_WIDTH      4
155 #define RW_MGR_MEM_DATA_WIDTH   32
156 #define RW_MGR_MEM_DQ_PER_READ_DQS      8
157 #define RW_MGR_MEM_DQ_PER_WRITE_DQS     8
158 #define RW_MGR_MEM_IF_READ_DQS_WIDTH    4
159 #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH   4
160 #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM        1
161 #define RW_MGR_MEM_NUMBER_OF_RANKS      1
162 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS  1
163 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
164 #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
165 #define TINIT_CNTR0_VAL 99
166 #define TINIT_CNTR1_VAL 32
167 #define TINIT_CNTR2_VAL 32
168 #define TRESET_CNTR0_VAL        99
169 #define TRESET_CNTR1_VAL        99
170 #define TRESET_CNTR2_VAL        10
171 
172 /* Sequencer ac_rom_init configuration */
173 const u32 ac_rom_init[] = {
174 	0x20700000,
175 	0x20780000,
176 	0x10080431,
177 	0x10080530,
178 	0x10090044,
179 	0x100a0010,
180 	0x100b0000,
181 	0x10380400,
182 	0x10080449,
183 	0x100804c8,
184 	0x100a0024,
185 	0x10090008,
186 	0x100b0000,
187 	0x30780000,
188 	0x38780000,
189 	0x30780000,
190 	0x10680000,
191 	0x106b0000,
192 	0x10280400,
193 	0x10480000,
194 	0x1c980000,
195 	0x1c9b0000,
196 	0x1c980008,
197 	0x1c9b0008,
198 	0x38f80000,
199 	0x3cf80000,
200 	0x38780000,
201 	0x18180000,
202 	0x18980000,
203 	0x13580000,
204 	0x135b0000,
205 	0x13580008,
206 	0x135b0008,
207 	0x33780000,
208 	0x10580008,
209 	0x10780000
210 };
211 
212 /* Sequencer inst_rom_init configuration */
213 const u32 inst_rom_init[] = {
214 	0x80000,
215 	0x80680,
216 	0x8180,
217 	0x8200,
218 	0x8280,
219 	0x8300,
220 	0x8380,
221 	0x8100,
222 	0x8480,
223 	0x8500,
224 	0x8580,
225 	0x8600,
226 	0x8400,
227 	0x800,
228 	0x8680,
229 	0x880,
230 	0xa680,
231 	0x80680,
232 	0x900,
233 	0x80680,
234 	0x980,
235 	0xa680,
236 	0x8680,
237 	0x80680,
238 	0xb68,
239 	0xcce8,
240 	0xae8,
241 	0x8ce8,
242 	0xb88,
243 	0xec88,
244 	0xa08,
245 	0xac88,
246 	0x80680,
247 	0xce00,
248 	0xcd80,
249 	0xe700,
250 	0xc00,
251 	0x20ce0,
252 	0x20ce0,
253 	0x20ce0,
254 	0x20ce0,
255 	0xd00,
256 	0x680,
257 	0x680,
258 	0x680,
259 	0x680,
260 	0x60e80,
261 	0x61080,
262 	0x61080,
263 	0x61080,
264 	0xa680,
265 	0x8680,
266 	0x80680,
267 	0xce00,
268 	0xcd80,
269 	0xe700,
270 	0xc00,
271 	0x30ce0,
272 	0x30ce0,
273 	0x30ce0,
274 	0x30ce0,
275 	0xd00,
276 	0x680,
277 	0x680,
278 	0x680,
279 	0x680,
280 	0x70e80,
281 	0x71080,
282 	0x71080,
283 	0x71080,
284 	0xa680,
285 	0x8680,
286 	0x80680,
287 	0x1158,
288 	0x6d8,
289 	0x80680,
290 	0x1168,
291 	0x7e8,
292 	0x7e8,
293 	0x87e8,
294 	0x40fe8,
295 	0x410e8,
296 	0x410e8,
297 	0x410e8,
298 	0x1168,
299 	0x7e8,
300 	0x7e8,
301 	0xa7e8,
302 	0x80680,
303 	0x40e88,
304 	0x41088,
305 	0x41088,
306 	0x41088,
307 	0x40f68,
308 	0x410e8,
309 	0x410e8,
310 	0x410e8,
311 	0xa680,
312 	0x40fe8,
313 	0x410e8,
314 	0x410e8,
315 	0x410e8,
316 	0x41008,
317 	0x41088,
318 	0x41088,
319 	0x41088,
320 	0x1100,
321 	0xc680,
322 	0x8680,
323 	0xe680,
324 	0x80680,
325 	0x0,
326 	0x8000,
327 	0xa000,
328 	0xc000,
329 	0x80000,
330 	0x80,
331 	0x8080,
332 	0xa080,
333 	0xc080,
334 	0x80080,
335 	0x9180,
336 	0x8680,
337 	0xa680,
338 	0x80680,
339 	0x40f08,
340 	0x80680
341 };
342 #endif /*#ifndef__SDRAM_CONFIG_H */
343