11fdabeddSStefano Babic /* 21fdabeddSStefano Babic * Copyright (C) 2011 Stefano Babic <sbabic@denx.de> 31fdabeddSStefano Babic * 41fdabeddSStefano Babic * Author: Hardy Weng <hardy.weng@technexion.com> 51fdabeddSStefano Babic * 61fdabeddSStefano Babic * Copyright (C) 2010 TechNexion Ltd. 71fdabeddSStefano Babic * 81fdabeddSStefano Babic * This program is free software; you can redistribute it and/or modify 91fdabeddSStefano Babic * it under the terms of the GNU General Public License as published by 101fdabeddSStefano Babic * the Free Software Foundation; either version 2 of the License, or 111fdabeddSStefano Babic * (at your option) any later version. 121fdabeddSStefano Babic * 131fdabeddSStefano Babic * This program is distributed in the hope that it will be useful, 141fdabeddSStefano Babic * but WITHOUT ANY WARRANTY; without even the implied warranty of 151fdabeddSStefano Babic * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 161fdabeddSStefano Babic * GNU General Public License for more details. 171fdabeddSStefano Babic * 181fdabeddSStefano Babic * You should have received a copy of the GNU General Public License 191fdabeddSStefano Babic * along with this program; if not, write to the Free Software 201fdabeddSStefano Babic * Foundation, Inc. 211fdabeddSStefano Babic */ 221fdabeddSStefano Babic 231fdabeddSStefano Babic #ifndef _MT_VENTOUX_H_ 241fdabeddSStefano Babic #define _MT_VENTOUX_H_ 251fdabeddSStefano Babic 261fdabeddSStefano Babic const omap3_sysinfo sysinfo = { 271fdabeddSStefano Babic DDR_DISCRETE, 281fdabeddSStefano Babic "Teejet MT_VENTOUX Board", 291fdabeddSStefano Babic "NAND", 301fdabeddSStefano Babic }; 311fdabeddSStefano Babic 321fdabeddSStefano Babic /* FPGA CS1 configuration */ 331fdabeddSStefano Babic #define FPGA_GPMC_CONFIG1 0x00001200 34c2afbb50SStefano Babic #define FPGA_GPMC_CONFIG2 0x00161f00 35c2afbb50SStefano Babic #define FPGA_GPMC_CONFIG3 0x00040400 36c2afbb50SStefano Babic #define FPGA_GPMC_CONFIG4 0x120c1f08 37c2afbb50SStefano Babic #define FPGA_GPMC_CONFIG5 0x001e161f 38c2afbb50SStefano Babic #define FPGA_GPMC_CONFIG6 0x96080fcf 391fdabeddSStefano Babic 401fdabeddSStefano Babic #define FPGA_BASE_ADDR 0x20000000 411fdabeddSStefano Babic 421fdabeddSStefano Babic /* 431fdabeddSStefano Babic * IEN - Input Enable 441fdabeddSStefano Babic * IDIS - Input Disable 451fdabeddSStefano Babic * PTD - Pull type Down 461fdabeddSStefano Babic * PTU - Pull type Up 471fdabeddSStefano Babic * DIS - Pull type selection is inactive 481fdabeddSStefano Babic * EN - Pull type selection is active 491fdabeddSStefano Babic * M0 - Mode 0 501fdabeddSStefano Babic * The commented string gives the final mux configuration for that pin 511fdabeddSStefano Babic */ 521fdabeddSStefano Babic #define MUX_MT_VENTOUX() \ 531fdabeddSStefano Babic /* SDRC */\ 541fdabeddSStefano Babic MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ 551fdabeddSStefano Babic MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ 561fdabeddSStefano Babic MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ 571fdabeddSStefano Babic MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ 581fdabeddSStefano Babic MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ 591fdabeddSStefano Babic MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ 601fdabeddSStefano Babic MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ 611fdabeddSStefano Babic MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ 621fdabeddSStefano Babic MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ 631fdabeddSStefano Babic MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ 641fdabeddSStefano Babic MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ 651fdabeddSStefano Babic MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ 661fdabeddSStefano Babic MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ 671fdabeddSStefano Babic MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ 681fdabeddSStefano Babic MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ 691fdabeddSStefano Babic MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ 701fdabeddSStefano Babic MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ 711fdabeddSStefano Babic MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ 721fdabeddSStefano Babic MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ 731fdabeddSStefano Babic MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ 741fdabeddSStefano Babic MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ 751fdabeddSStefano Babic MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ 761fdabeddSStefano Babic MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ 771fdabeddSStefano Babic MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ 781fdabeddSStefano Babic MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ 791fdabeddSStefano Babic MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ 801fdabeddSStefano Babic MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ 811fdabeddSStefano Babic MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ 821fdabeddSStefano Babic MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ 831fdabeddSStefano Babic MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ 841fdabeddSStefano Babic MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ 851fdabeddSStefano Babic MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ 861fdabeddSStefano Babic MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ 871fdabeddSStefano Babic MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ 881fdabeddSStefano Babic MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ 891fdabeddSStefano Babic MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ 901fdabeddSStefano Babic MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ 911fdabeddSStefano Babic MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ 921fdabeddSStefano Babic MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ 931fdabeddSStefano Babic MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ 941fdabeddSStefano Babic MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ 951fdabeddSStefano Babic MUX_VAL(CP(SDRC_CKE0), (M0)) \ 961fdabeddSStefano Babic MUX_VAL(CP(SDRC_CKE1), (M0)) \ 971fdabeddSStefano Babic MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ 981fdabeddSStefano Babic MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ 991fdabeddSStefano Babic /* GPMC */\ 1001fdabeddSStefano Babic MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 1011fdabeddSStefano Babic MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 1021fdabeddSStefano Babic MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 1031fdabeddSStefano Babic MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 1041fdabeddSStefano Babic MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 1051fdabeddSStefano Babic MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 1061fdabeddSStefano Babic MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 1071fdabeddSStefano Babic MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 1081fdabeddSStefano Babic MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 1091fdabeddSStefano Babic MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ 1101fdabeddSStefano Babic MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ 1111fdabeddSStefano Babic MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ 1121fdabeddSStefano Babic MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ 1131fdabeddSStefano Babic MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ 1141fdabeddSStefano Babic MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ 1151fdabeddSStefano Babic MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ 1161fdabeddSStefano Babic MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ 1171fdabeddSStefano Babic MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ 1181fdabeddSStefano Babic MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ 1191fdabeddSStefano Babic MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ 1201fdabeddSStefano Babic MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ 1211fdabeddSStefano Babic MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ 1221fdabeddSStefano Babic MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ 1231fdabeddSStefano Babic MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ 1241fdabeddSStefano Babic MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ 1251fdabeddSStefano Babic MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ 1261fdabeddSStefano Babic MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ 1271fdabeddSStefano Babic MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \ 1281fdabeddSStefano Babic MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\ 1291fdabeddSStefano Babic MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\ 1301fdabeddSStefano Babic MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \ 1311fdabeddSStefano Babic /* GPIO 55 : NFS */\ 1321fdabeddSStefano Babic MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \ 1331fdabeddSStefano Babic MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \ 1341fdabeddSStefano Babic MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \ 1351fdabeddSStefano Babic MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ 1361fdabeddSStefano Babic MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ 1371fdabeddSStefano Babic MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ 1381fdabeddSStefano Babic MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ 1391fdabeddSStefano Babic MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ 1401fdabeddSStefano Babic MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ 1411fdabeddSStefano Babic MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \ 1421fdabeddSStefano Babic /*GPIO_62: FPGA_RESET */ \ 1431fdabeddSStefano Babic MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \ 1441fdabeddSStefano Babic MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \ 145*e40f6c4aSStefano Babic MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ 146*e40f6c4aSStefano Babic /* GPIO_64*/ \ 1471fdabeddSStefano Babic MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ 1481fdabeddSStefano Babic /* DSS */\ 1491fdabeddSStefano Babic MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ 1501fdabeddSStefano Babic MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ 1511fdabeddSStefano Babic MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ 1521fdabeddSStefano Babic MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ 1531fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ 1541fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ 1551fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ 1561fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ 1571fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ 1581fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ 1591fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ 1601fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ 1611fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ 1621fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ 1631fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ 1641fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ 1651fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ 1661fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ 1671fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ 1681fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ 1691fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ 1701fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ 1711fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ 1721fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ 1731fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ 1741fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ 1751fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ 1761fdabeddSStefano Babic MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ 1771fdabeddSStefano Babic /* CAMERA */\ 1781fdabeddSStefano Babic MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ 1791fdabeddSStefano Babic MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ 1801fdabeddSStefano Babic MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ 1811fdabeddSStefano Babic MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ 1821fdabeddSStefano Babic /* MMC */\ 1831fdabeddSStefano Babic MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ 1841fdabeddSStefano Babic MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ 1851fdabeddSStefano Babic MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ 1861fdabeddSStefano Babic MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ 1871fdabeddSStefano Babic MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ 1881fdabeddSStefano Babic MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ 1891fdabeddSStefano Babic MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ 1901fdabeddSStefano Babic /* GPIO_126: CardDetect */\ 1911fdabeddSStefano Babic MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ 1921fdabeddSStefano Babic MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ 193*e40f6c4aSStefano Babic /*GPIO_128 */ \ 1941fdabeddSStefano Babic MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ 1951fdabeddSStefano Babic \ 1961fdabeddSStefano Babic MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ 1971fdabeddSStefano Babic MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\ 1981fdabeddSStefano Babic MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\ 1991fdabeddSStefano Babic MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\ 2001fdabeddSStefano Babic MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\ 2011fdabeddSStefano Babic MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\ 2021fdabeddSStefano Babic MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \ 2031fdabeddSStefano Babic MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ 2041fdabeddSStefano Babic MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ 2051fdabeddSStefano Babic /* GPIO_138: LCD_ENVD */\ 2061fdabeddSStefano Babic MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ 2071fdabeddSStefano Babic /* GPIO_139: LCD_PON */\ 2081fdabeddSStefano Babic /* McBSP */\ 2091fdabeddSStefano Babic MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ 2101fdabeddSStefano Babic MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ 2111fdabeddSStefano Babic MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ 2121fdabeddSStefano Babic MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ 2131fdabeddSStefano Babic MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ 2141fdabeddSStefano Babic MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ 2151fdabeddSStefano Babic MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ 2161fdabeddSStefano Babic \ 2171fdabeddSStefano Babic MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \ 2181fdabeddSStefano Babic /* GPIO_116: FPGA_PROG */ \ 2191fdabeddSStefano Babic MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \ 2201fdabeddSStefano Babic /* GPIO_117: FPGA_CCLK */ \ 2211fdabeddSStefano Babic MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \ 2221fdabeddSStefano Babic /* GPIO_118: FPGA_DIN */ \ 2231fdabeddSStefano Babic MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \ 2241fdabeddSStefano Babic /* GPIO_119: FPGA_INIT */ \ 2251fdabeddSStefano Babic \ 2261fdabeddSStefano Babic MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ 2271fdabeddSStefano Babic /* GPIO_140: speaker #mute */\ 2281fdabeddSStefano Babic MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ 2291fdabeddSStefano Babic /* GPIO_141: Buzz Hi */\ 2301fdabeddSStefano Babic MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ 2311fdabeddSStefano Babic MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \ 2321fdabeddSStefano Babic \ 2331fdabeddSStefano Babic MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \ 2341fdabeddSStefano Babic /*GPIO_152: Ignition Sense */ \ 235*e40f6c4aSStefano Babic MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \ 2361fdabeddSStefano Babic /*GPIO_153: Power Button Sense */ \ 2371fdabeddSStefano Babic MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \ 2381fdabeddSStefano Babic /* GPIO_154: FPGA_DONE */ \ 2391fdabeddSStefano Babic MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \ 2401fdabeddSStefano Babic /* GPIO_155: CA8_irq */ \ 2411fdabeddSStefano Babic /* UART */\ 2421fdabeddSStefano Babic MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ 2431fdabeddSStefano Babic MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \ 2441fdabeddSStefano Babic /* GPIO_149: USB status 2 */\ 2451fdabeddSStefano Babic MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \ 2461fdabeddSStefano Babic /* GPIO_150: USB status 1 */\ 2471fdabeddSStefano Babic \ 2481fdabeddSStefano Babic MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ 249*e40f6c4aSStefano Babic MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \ 250*e40f6c4aSStefano Babic /* gpt9_pwm */\ 251*e40f6c4aSStefano Babic MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \ 252*e40f6c4aSStefano Babic /* gpt10_pwm */\ 253*e40f6c4aSStefano Babic MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \ 254*e40f6c4aSStefano Babic /* gpt8_pwm */\ 255*e40f6c4aSStefano Babic MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \ 256*e40f6c4aSStefano Babic /* gpt11_pwm */\ 2571fdabeddSStefano Babic \ 2581fdabeddSStefano Babic MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \ 2591fdabeddSStefano Babic /*GPIO_163 : TS_PENIRQ*/ \ 2601fdabeddSStefano Babic MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \ 2611fdabeddSStefano Babic /*GPIO_164 : MMC */\ 2621fdabeddSStefano Babic MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ 2631fdabeddSStefano Babic MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ 2641fdabeddSStefano Babic /* I2C */\ 2651fdabeddSStefano Babic MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ 2661fdabeddSStefano Babic MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ 2671fdabeddSStefano Babic MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ 2681fdabeddSStefano Babic MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ 2691fdabeddSStefano Babic MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ 2701fdabeddSStefano Babic MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ 2711fdabeddSStefano Babic MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ 2721fdabeddSStefano Babic MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ 2731fdabeddSStefano Babic /* McSPI */\ 2741fdabeddSStefano Babic MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ 2751fdabeddSStefano Babic MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ 2761fdabeddSStefano Babic MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ 2771fdabeddSStefano Babic MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ 2781fdabeddSStefano Babic MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ 2791fdabeddSStefano Babic MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\ 2801fdabeddSStefano Babic MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \ 2811fdabeddSStefano Babic \ 2821fdabeddSStefano Babic MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ 2831fdabeddSStefano Babic MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ 2841fdabeddSStefano Babic MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ 2851fdabeddSStefano Babic MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ 2861fdabeddSStefano Babic MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \ 2871fdabeddSStefano Babic /* CCDC */\ 288*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \ 289*e40f6c4aSStefano Babic /* GPIO94 */\ 2901fdabeddSStefano Babic MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \ 2911fdabeddSStefano Babic /* GPIO95: #Enable Output */\ 292*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \ 293*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \ 2941fdabeddSStefano Babic MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \ 2951fdabeddSStefano Babic /* GPIO 99: #SOM_PWR_OFF */\ 296*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \ 2971fdabeddSStefano Babic MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \ 2981fdabeddSStefano Babic /* GPIO_100: #power out */\ 299*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \ 300*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \ 301*e40f6c4aSStefano Babic /* GPIO_102 */\ 302*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \ 303*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \ 304*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \ 305*e40f6c4aSStefano Babic MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \ 3061fdabeddSStefano Babic /* RMII */\ 3071fdabeddSStefano Babic MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ 3081fdabeddSStefano Babic MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ 3091fdabeddSStefano Babic MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ 3101fdabeddSStefano Babic MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ 3111fdabeddSStefano Babic MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ 3121fdabeddSStefano Babic MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ 3131fdabeddSStefano Babic MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ 3141fdabeddSStefano Babic MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ 3151fdabeddSStefano Babic MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ 3161fdabeddSStefano Babic MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ 3171fdabeddSStefano Babic /* HECC */\ 3181fdabeddSStefano Babic MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ 3191fdabeddSStefano Babic MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ 3201fdabeddSStefano Babic /* HSUSB */\ 3211fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ 3221fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \ 3231fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ 3241fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \ 3251fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ 3261fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ 3271fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ 3281fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ 3291fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ 3301fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ 3311fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ 3321fdabeddSStefano Babic MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ 3331fdabeddSStefano Babic MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ 3341fdabeddSStefano Babic /* HDQ */\ 3351fdabeddSStefano Babic MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ 3361fdabeddSStefano Babic /* GPIO_170: auto update */\ 3371fdabeddSStefano Babic /* Control and debug */\ 3381fdabeddSStefano Babic MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ 3391fdabeddSStefano Babic MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ 3401fdabeddSStefano Babic MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ 3411fdabeddSStefano Babic MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ 3421fdabeddSStefano Babic /* - GPIO30 */\ 3431fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ 3441fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ 3451fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ 3461fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ 3471fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ 3481fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ 3491fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ 3501fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ 3511fdabeddSStefano Babic MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ 3521fdabeddSStefano Babic \ 3531fdabeddSStefano Babic MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ 354*e40f6c4aSStefano Babic MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \ 355*e40f6c4aSStefano Babic /* gpio_10 */\ 3561fdabeddSStefano Babic MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ 3571fdabeddSStefano Babic /* JTAG */\ 3581fdabeddSStefano Babic MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ 3591fdabeddSStefano Babic MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ 3601fdabeddSStefano Babic MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ 3611fdabeddSStefano Babic MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ 3621fdabeddSStefano Babic MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \ 3631fdabeddSStefano Babic MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \ 3641fdabeddSStefano Babic /* ETK (ES2 onwards) */\ 3651fdabeddSStefano Babic MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ 3661fdabeddSStefano Babic /* hsusb1_stp */ \ 3671fdabeddSStefano Babic MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ 3681fdabeddSStefano Babic /* hsusb1_clk */\ 3691fdabeddSStefano Babic MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \ 3701fdabeddSStefano Babic MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \ 3711fdabeddSStefano Babic MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \ 3721fdabeddSStefano Babic MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \ 3731fdabeddSStefano Babic MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \ 3741fdabeddSStefano Babic MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \ 3751fdabeddSStefano Babic MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \ 3761fdabeddSStefano Babic MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \ 3771fdabeddSStefano Babic MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ 3781fdabeddSStefano Babic MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ 379*e40f6c4aSStefano Babic MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \ 380*e40f6c4aSStefano Babic /* gpio_24 */\ 3811fdabeddSStefano Babic MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \ 382*e40f6c4aSStefano Babic MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ 383*e40f6c4aSStefano Babic /* gpio_26 */\ 3841fdabeddSStefano Babic MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \ 385*e40f6c4aSStefano Babic MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ 386*e40f6c4aSStefano Babic MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ 387*e40f6c4aSStefano Babic /* gpio_29 */\ 3881fdabeddSStefano Babic /* Die to Die */\ 3891fdabeddSStefano Babic MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ 3901fdabeddSStefano Babic MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ 3911fdabeddSStefano Babic MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ 3921fdabeddSStefano Babic MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ 3931fdabeddSStefano Babic MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ 3941fdabeddSStefano Babic MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ 3951fdabeddSStefano Babic MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ 3961fdabeddSStefano Babic MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ 3971fdabeddSStefano Babic MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ 3981fdabeddSStefano Babic MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ 3991fdabeddSStefano Babic MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ 4001fdabeddSStefano Babic MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ 4011fdabeddSStefano Babic MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ 4021fdabeddSStefano Babic MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ 4031fdabeddSStefano Babic MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ 4041fdabeddSStefano Babic MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ 4051fdabeddSStefano Babic MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ 4061fdabeddSStefano Babic MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ 4071fdabeddSStefano Babic MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ 4081fdabeddSStefano Babic MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ 4091fdabeddSStefano Babic MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ 4101fdabeddSStefano Babic MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ 4111fdabeddSStefano Babic MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ 4121fdabeddSStefano Babic MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ 4131fdabeddSStefano Babic MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ 4141fdabeddSStefano Babic MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ 4151fdabeddSStefano Babic MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ 4161fdabeddSStefano Babic MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ 4171fdabeddSStefano Babic MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ 4181fdabeddSStefano Babic MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ 4191fdabeddSStefano Babic 4201fdabeddSStefano Babic #endif 421