1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc. 20 */ 21 22 #include <common.h> 23 #include <netdev.h> 24 #include <malloc.h> 25 #include <fpga.h> 26 #include <video_fb.h> 27 #include <asm/io.h> 28 #include <asm/arch/mem.h> 29 #include <asm/arch/mux.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/omap_gpio.h> 32 #include <asm/arch/mmc_host_def.h> 33 #include <asm/arch/dss.h> 34 #include <asm/arch/clock.h> 35 #include <i2c.h> 36 #include <spartan3.h> 37 #include <asm/gpio.h> 38 #ifdef CONFIG_USB_EHCI 39 #include <usb.h> 40 #include <asm/ehci-omap.h> 41 #endif 42 #include "mt_ventoux.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 #define BUZZER 140 47 #define SPEAKER 141 48 #define USB1_PWR 127 49 #define USB2_PWR 149 50 51 #ifndef CONFIG_FPGA 52 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" 53 #endif 54 55 #define FPGA_RESET 62 56 #define FPGA_PROG 116 57 #define FPGA_CCLK 117 58 #define FPGA_DIN 118 59 #define FPGA_INIT 119 60 #define FPGA_DONE 154 61 62 #define LCD_PWR 138 63 #define LCD_PON_PIN 139 64 65 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 66 static struct { 67 u32 xres; 68 u32 yres; 69 } panel_resolution[] = { 70 { 480, 272 }, 71 { 800, 480 } 72 }; 73 74 static struct panel_config lcd_cfg[] = { 75 { 76 .timing_h = PANEL_TIMING_H(40, 5, 2), 77 .timing_v = PANEL_TIMING_V(8, 8, 2), 78 .pol_freq = 0x00003000, /* Pol Freq */ 79 .divisor = 0x00010033, /* 9 Mhz Pixel Clock */ 80 .panel_type = 0x01, /* TFT */ 81 .data_lines = 0x03, /* 24 Bit RGB */ 82 .load_mode = 0x02, /* Frame Mode */ 83 .panel_color = 0, 84 .gfx_format = GFXFORMAT_RGB24_UNPACKED, 85 }, 86 { 87 .timing_h = PANEL_TIMING_H(20, 192, 4), 88 .timing_v = PANEL_TIMING_V(2, 20, 10), 89 .pol_freq = 0x00004000, /* Pol Freq */ 90 .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ 91 .panel_type = 0x01, /* TFT */ 92 .data_lines = 0x03, /* 24 Bit RGB */ 93 .load_mode = 0x02, /* Frame Mode */ 94 .panel_color = 0, 95 .gfx_format = GFXFORMAT_RGB24_UNPACKED, 96 } 97 }; 98 #endif 99 100 /* Timing definitions for FPGA */ 101 static const u32 gpmc_fpga[] = { 102 FPGA_GPMC_CONFIG1, 103 FPGA_GPMC_CONFIG2, 104 FPGA_GPMC_CONFIG3, 105 FPGA_GPMC_CONFIG4, 106 FPGA_GPMC_CONFIG5, 107 FPGA_GPMC_CONFIG6, 108 }; 109 110 #ifdef CONFIG_USB_EHCI 111 static struct omap_usbhs_board_data usbhs_bdata = { 112 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 113 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 114 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 115 }; 116 117 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 118 { 119 return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); 120 } 121 122 int ehci_hcd_stop(int index) 123 { 124 return omap_ehci_hcd_stop(); 125 } 126 #endif 127 128 129 static inline void fpga_reset(int nassert) 130 { 131 gpio_set_value(FPGA_RESET, !nassert); 132 } 133 134 int fpga_pgm_fn(int nassert, int nflush, int cookie) 135 { 136 debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__); 137 138 gpio_set_value(FPGA_PROG, !nassert); 139 140 return nassert; 141 } 142 143 int fpga_init_fn(int cookie) 144 { 145 return !gpio_get_value(FPGA_INIT); 146 } 147 148 int fpga_done_fn(int cookie) 149 { 150 return gpio_get_value(FPGA_DONE); 151 } 152 153 int fpga_pre_config_fn(int cookie) 154 { 155 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); 156 157 /* Setting GPIOs for programming Mode */ 158 gpio_request(FPGA_RESET, "FPGA_RESET"); 159 gpio_direction_output(FPGA_RESET, 1); 160 gpio_request(FPGA_PROG, "FPGA_PROG"); 161 gpio_direction_output(FPGA_PROG, 1); 162 gpio_request(FPGA_CCLK, "FPGA_CCLK"); 163 gpio_direction_output(FPGA_CCLK, 1); 164 gpio_request(FPGA_DIN, "FPGA_DIN"); 165 gpio_direction_output(FPGA_DIN, 0); 166 gpio_request(FPGA_INIT, "FPGA_INIT"); 167 gpio_direction_input(FPGA_INIT); 168 gpio_request(FPGA_DONE, "FPGA_DONE"); 169 gpio_direction_input(FPGA_DONE); 170 171 /* Be sure that signal are deasserted */ 172 gpio_set_value(FPGA_RESET, 1); 173 gpio_set_value(FPGA_PROG, 1); 174 175 return 0; 176 } 177 178 int fpga_post_config_fn(int cookie) 179 { 180 debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); 181 182 fpga_reset(true); 183 udelay(100); 184 fpga_reset(false); 185 186 return 0; 187 } 188 189 /* Write program to the FPGA */ 190 int fpga_wr_fn(int nassert_write, int flush, int cookie) 191 { 192 gpio_set_value(FPGA_DIN, nassert_write); 193 194 return nassert_write; 195 } 196 197 int fpga_clk_fn(int assert_clk, int flush, int cookie) 198 { 199 gpio_set_value(FPGA_CCLK, assert_clk); 200 201 return assert_clk; 202 } 203 204 Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { 205 fpga_pre_config_fn, 206 fpga_pgm_fn, 207 fpga_clk_fn, 208 fpga_init_fn, 209 fpga_done_fn, 210 fpga_wr_fn, 211 fpga_post_config_fn, 212 }; 213 214 Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, 215 (void *)&mt_ventoux_fpga_fns, 0); 216 217 /* Initialize the FPGA */ 218 static void mt_ventoux_init_fpga(void) 219 { 220 fpga_pre_config_fn(0); 221 222 /* Setting CS1 for FPGA access */ 223 enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1], 224 FPGA_BASE_ADDR, GPMC_SIZE_128M); 225 226 fpga_init(); 227 fpga_add(fpga_xilinx, &fpga); 228 } 229 230 /* 231 * Routine: board_init 232 * Description: Early hardware init. 233 */ 234 int board_init(void) 235 { 236 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 237 238 /* boot param addr */ 239 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 240 241 mt_ventoux_init_fpga(); 242 243 /* GPIO_140: speaker #mute */ 244 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) 245 /* GPIO_141: Buzz Hi */ 246 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) 247 248 /* Turning off the buzzer */ 249 gpio_request(BUZZER, "BUZZER_MUTE"); 250 gpio_request(SPEAKER, "SPEAKER"); 251 gpio_direction_output(BUZZER, 0); 252 gpio_direction_output(SPEAKER, 0); 253 254 /* Activate USB power */ 255 gpio_request(USB1_PWR, "USB1_PWR"); 256 gpio_request(USB2_PWR, "USB2_PWR"); 257 gpio_direction_output(USB1_PWR, 1); 258 gpio_direction_output(USB2_PWR, 1); 259 260 return 0; 261 } 262 263 #ifndef CONFIG_SPL_BUILD 264 int misc_init_r(void) 265 { 266 char *eth_addr; 267 struct tam3517_module_info info; 268 int ret; 269 270 TAM3517_READ_EEPROM(&info, ret); 271 dieid_num_r(); 272 273 if (ret) 274 return 0; 275 eth_addr = getenv("ethaddr"); 276 if (!eth_addr) 277 TAM3517_READ_MAC_FROM_EEPROM(&info); 278 279 TAM3517_PRINT_SOM_INFO(&info); 280 return 0; 281 } 282 #endif 283 284 /* 285 * Routine: set_muxconf_regs 286 * Description: Setting up the configuration Mux registers specific to the 287 * hardware. Many pins need to be moved from protect to primary 288 * mode. 289 */ 290 void set_muxconf_regs(void) 291 { 292 MUX_MT_VENTOUX(); 293 } 294 295 /* 296 * Initializes on-chip ethernet controllers. 297 * to override, implement board_eth_init() 298 */ 299 int board_eth_init(bd_t *bis) 300 { 301 davinci_emac_initialize(); 302 return 0; 303 } 304 305 #if defined(CONFIG_OMAP_HSMMC) && \ 306 !defined(CONFIG_SPL_BUILD) 307 int board_mmc_init(bd_t *bis) 308 { 309 return omap_mmc_init(0, 0, 0, -1, -1); 310 } 311 #endif 312 313 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 314 int board_video_init(void) 315 { 316 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 317 struct panel_config *panel = &lcd_cfg[0]; 318 char *s; 319 u32 index = 0; 320 321 void *fb; 322 323 fb = (void *)0x88000000; 324 325 s = getenv("panel"); 326 if (s) { 327 index = simple_strtoul(s, NULL, 10); 328 if (index < ARRAY_SIZE(lcd_cfg)) 329 panel = &lcd_cfg[index]; 330 else 331 return 0; 332 } 333 334 panel->frame_buffer = fb; 335 printf("Panel: %dx%d\n", panel_resolution[index].xres, 336 panel_resolution[index].yres); 337 panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | 338 (panel_resolution[index].xres - 1); 339 340 gpio_request(LCD_PWR, "LCD Power"); 341 gpio_request(LCD_PON_PIN, "LCD Pon"); 342 gpio_direction_output(LCD_PWR, 0); 343 gpio_direction_output(LCD_PON_PIN, 1); 344 345 346 setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); 347 setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); 348 349 omap3_dss_panel_config(panel); 350 omap3_dss_enable(); 351 352 return 0; 353 } 354 #endif 355