1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc. 20 */ 21 22 #include <common.h> 23 #include <netdev.h> 24 #include <malloc.h> 25 #include <fpga.h> 26 #include <video_fb.h> 27 #include <asm/io.h> 28 #include <asm/arch/mem.h> 29 #include <asm/arch/mux.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/omap_gpio.h> 32 #include <asm/arch/mmc_host_def.h> 33 #include <asm/arch/dss.h> 34 #include <asm/arch/clocks.h> 35 #include <i2c.h> 36 #include <spartan3.h> 37 #include <asm/gpio.h> 38 #ifdef CONFIG_USB_EHCI 39 #include <usb.h> 40 #include <asm/ehci-omap.h> 41 #endif 42 #include "mt_ventoux.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 #define BUZZER 140 47 #define SPEAKER 141 48 #define USB1_PWR 127 49 #define USB2_PWR 149 50 51 #ifndef CONFIG_FPGA 52 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" 53 #endif 54 55 #define FPGA_RESET 62 56 #define FPGA_PROG 116 57 #define FPGA_CCLK 117 58 #define FPGA_DIN 118 59 #define FPGA_INIT 119 60 #define FPGA_DONE 154 61 62 #define LCD_PWR 138 63 #define LCD_PON_PIN 139 64 65 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 66 static struct { 67 u32 xres; 68 u32 yres; 69 } panel_resolution[] = { 70 { 480, 272 }, 71 { 800, 480 } 72 }; 73 74 static struct panel_config lcd_cfg[] = { 75 { 76 .timing_h = PANEL_TIMING_H(4, 8, 41), 77 .timing_v = PANEL_TIMING_V(2, 4, 10), 78 .pol_freq = 0x00000000, /* Pol Freq */ 79 .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ 80 .panel_type = 0x01, /* TFT */ 81 .data_lines = 0x03, /* 24 Bit RGB */ 82 .load_mode = 0x02, /* Frame Mode */ 83 .panel_color = 0, 84 }, 85 { 86 .timing_h = PANEL_TIMING_H(20, 192, 4), 87 .timing_v = PANEL_TIMING_V(2, 20, 10), 88 .pol_freq = 0x00004000, /* Pol Freq */ 89 .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ 90 .panel_type = 0x01, /* TFT */ 91 .data_lines = 0x03, /* 24 Bit RGB */ 92 .load_mode = 0x02, /* Frame Mode */ 93 .panel_color = 0, 94 } 95 }; 96 #endif 97 98 /* Timing definitions for FPGA */ 99 static const u32 gpmc_fpga[] = { 100 FPGA_GPMC_CONFIG1, 101 FPGA_GPMC_CONFIG2, 102 FPGA_GPMC_CONFIG3, 103 FPGA_GPMC_CONFIG4, 104 FPGA_GPMC_CONFIG5, 105 FPGA_GPMC_CONFIG6, 106 }; 107 108 #ifdef CONFIG_USB_EHCI 109 static struct omap_usbhs_board_data usbhs_bdata = { 110 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 111 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 112 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 113 }; 114 115 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 116 { 117 return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); 118 } 119 120 int ehci_hcd_stop(int index) 121 { 122 return omap_ehci_hcd_stop(); 123 } 124 #endif 125 126 127 static inline void fpga_reset(int nassert) 128 { 129 gpio_set_value(FPGA_RESET, !nassert); 130 } 131 132 int fpga_pgm_fn(int nassert, int nflush, int cookie) 133 { 134 debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__); 135 136 gpio_set_value(FPGA_PROG, !nassert); 137 138 return nassert; 139 } 140 141 int fpga_init_fn(int cookie) 142 { 143 return !gpio_get_value(FPGA_INIT); 144 } 145 146 int fpga_done_fn(int cookie) 147 { 148 return gpio_get_value(FPGA_DONE); 149 } 150 151 int fpga_pre_config_fn(int cookie) 152 { 153 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); 154 155 /* Setting GPIOs for programming Mode */ 156 gpio_request(FPGA_RESET, "FPGA_RESET"); 157 gpio_direction_output(FPGA_RESET, 1); 158 gpio_request(FPGA_PROG, "FPGA_PROG"); 159 gpio_direction_output(FPGA_PROG, 1); 160 gpio_request(FPGA_CCLK, "FPGA_CCLK"); 161 gpio_direction_output(FPGA_CCLK, 1); 162 gpio_request(FPGA_DIN, "FPGA_DIN"); 163 gpio_direction_output(FPGA_DIN, 0); 164 gpio_request(FPGA_INIT, "FPGA_INIT"); 165 gpio_direction_input(FPGA_INIT); 166 gpio_request(FPGA_DONE, "FPGA_DONE"); 167 gpio_direction_input(FPGA_DONE); 168 169 /* Be sure that signal are deasserted */ 170 gpio_set_value(FPGA_RESET, 1); 171 gpio_set_value(FPGA_PROG, 1); 172 173 return 0; 174 } 175 176 int fpga_post_config_fn(int cookie) 177 { 178 debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); 179 180 fpga_reset(TRUE); 181 udelay(100); 182 fpga_reset(FALSE); 183 184 return 0; 185 } 186 187 /* Write program to the FPGA */ 188 int fpga_wr_fn(int nassert_write, int flush, int cookie) 189 { 190 gpio_set_value(FPGA_DIN, nassert_write); 191 192 return nassert_write; 193 } 194 195 int fpga_clk_fn(int assert_clk, int flush, int cookie) 196 { 197 gpio_set_value(FPGA_CCLK, assert_clk); 198 199 return assert_clk; 200 } 201 202 Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { 203 fpga_pre_config_fn, 204 fpga_pgm_fn, 205 fpga_clk_fn, 206 fpga_init_fn, 207 fpga_done_fn, 208 fpga_wr_fn, 209 fpga_post_config_fn, 210 }; 211 212 Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, 213 (void *)&mt_ventoux_fpga_fns, 0); 214 215 /* Initialize the FPGA */ 216 static void mt_ventoux_init_fpga(void) 217 { 218 fpga_pre_config_fn(0); 219 220 /* Setting CS1 for FPGA access */ 221 enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1], 222 FPGA_BASE_ADDR, GPMC_SIZE_128M); 223 224 fpga_init(); 225 fpga_add(fpga_xilinx, &fpga); 226 } 227 228 /* 229 * Routine: board_init 230 * Description: Early hardware init. 231 */ 232 int board_init(void) 233 { 234 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 235 236 /* boot param addr */ 237 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 238 239 mt_ventoux_init_fpga(); 240 241 /* GPIO_140: speaker #mute */ 242 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) 243 /* GPIO_141: Buzz Hi */ 244 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) 245 246 /* Turning off the buzzer */ 247 gpio_request(BUZZER, "BUZZER_MUTE"); 248 gpio_request(SPEAKER, "SPEAKER"); 249 gpio_direction_output(BUZZER, 0); 250 gpio_direction_output(SPEAKER, 0); 251 252 /* Activate USB power */ 253 gpio_request(USB1_PWR, "USB1_PWR"); 254 gpio_request(USB2_PWR, "USB2_PWR"); 255 gpio_direction_output(USB1_PWR, 1); 256 gpio_direction_output(USB2_PWR, 1); 257 258 return 0; 259 } 260 261 int misc_init_r(void) 262 { 263 char *eth_addr; 264 265 dieid_num_r(); 266 267 eth_addr = getenv("ethaddr"); 268 if (eth_addr) 269 return 0; 270 271 #ifndef CONFIG_SPL_BUILD 272 TAM3517_READ_MAC_FROM_EEPROM; 273 #endif 274 return 0; 275 } 276 277 /* 278 * Routine: set_muxconf_regs 279 * Description: Setting up the configuration Mux registers specific to the 280 * hardware. Many pins need to be moved from protect to primary 281 * mode. 282 */ 283 void set_muxconf_regs(void) 284 { 285 MUX_MT_VENTOUX(); 286 } 287 288 /* 289 * Initializes on-chip ethernet controllers. 290 * to override, implement board_eth_init() 291 */ 292 int board_eth_init(bd_t *bis) 293 { 294 davinci_emac_initialize(); 295 return 0; 296 } 297 298 #if defined(CONFIG_OMAP_HSMMC) && \ 299 !defined(CONFIG_SPL_BUILD) 300 int board_mmc_init(bd_t *bis) 301 { 302 return omap_mmc_init(0, 0, 0); 303 } 304 #endif 305 306 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 307 int board_video_init(void) 308 { 309 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 310 struct panel_config *panel = &lcd_cfg[0]; 311 char *s; 312 u32 index = 0; 313 314 void *fb; 315 316 fb = (void *)0x88000000; 317 318 s = getenv("panel"); 319 if (s) { 320 index = simple_strtoul(s, NULL, 10); 321 if (index < ARRAY_SIZE(lcd_cfg)) 322 panel = &lcd_cfg[index]; 323 else 324 return 0; 325 } 326 327 panel->frame_buffer = fb; 328 printf("Panel: %dx%d\n", panel_resolution[index].xres, 329 panel_resolution[index].yres); 330 panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | 331 (panel_resolution[index].xres - 1); 332 333 gpio_request(LCD_PWR, "LCD Power"); 334 gpio_request(LCD_PON_PIN, "LCD Pon"); 335 gpio_direction_output(LCD_PWR, 0); 336 gpio_direction_output(LCD_PON_PIN, 1); 337 338 339 setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); 340 setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); 341 342 omap3_dss_panel_config(panel); 343 omap3_dss_enable(); 344 345 return 0; 346 } 347 #endif 348