1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc. 20 */ 21 22 #include <common.h> 23 #include <netdev.h> 24 #include <malloc.h> 25 #include <fpga.h> 26 #include <video_fb.h> 27 #include <asm/io.h> 28 #include <asm/arch/mem.h> 29 #include <asm/arch/mux.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/omap_gpio.h> 32 #include <asm/arch/mmc_host_def.h> 33 #include <asm/arch/dss.h> 34 #include <asm/arch/clocks.h> 35 #include <i2c.h> 36 #include <spartan3.h> 37 #include <asm/gpio.h> 38 #ifdef CONFIG_USB_EHCI 39 #include <usb.h> 40 #include <asm/ehci-omap.h> 41 #endif 42 #include "mt_ventoux.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 #define BUZZER 140 47 #define SPEAKER 141 48 49 #ifndef CONFIG_FPGA 50 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" 51 #endif 52 53 #define FPGA_RESET 62 54 #define FPGA_PROG 116 55 #define FPGA_CCLK 117 56 #define FPGA_DIN 118 57 #define FPGA_INIT 119 58 #define FPGA_DONE 154 59 60 #define LCD_PWR 138 61 #define LCD_PON_PIN 139 62 63 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 64 static struct { 65 u32 xres; 66 u32 yres; 67 } panel_resolution[] = { 68 { 480, 272 }, 69 { 800, 480 } 70 }; 71 72 static struct panel_config lcd_cfg[] = { 73 { 74 .timing_h = PANEL_TIMING_H(4, 8, 41), 75 .timing_v = PANEL_TIMING_V(2, 4, 10), 76 .pol_freq = 0x00000000, /* Pol Freq */ 77 .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ 78 .panel_type = 0x01, /* TFT */ 79 .data_lines = 0x03, /* 24 Bit RGB */ 80 .load_mode = 0x02, /* Frame Mode */ 81 .panel_color = 0, 82 }, 83 { 84 .timing_h = PANEL_TIMING_H(20, 192, 4), 85 .timing_v = PANEL_TIMING_V(2, 20, 10), 86 .pol_freq = 0x00004000, /* Pol Freq */ 87 .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ 88 .panel_type = 0x01, /* TFT */ 89 .data_lines = 0x03, /* 24 Bit RGB */ 90 .load_mode = 0x02, /* Frame Mode */ 91 .panel_color = 0, 92 } 93 }; 94 #endif 95 96 /* Timing definitions for FPGA */ 97 static const u32 gpmc_fpga[] = { 98 FPGA_GPMC_CONFIG1, 99 FPGA_GPMC_CONFIG2, 100 FPGA_GPMC_CONFIG3, 101 FPGA_GPMC_CONFIG4, 102 FPGA_GPMC_CONFIG5, 103 FPGA_GPMC_CONFIG6, 104 }; 105 106 #ifdef CONFIG_USB_EHCI 107 static struct omap_usbhs_board_data usbhs_bdata = { 108 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 109 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 110 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 111 }; 112 113 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 114 { 115 return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); 116 } 117 118 int ehci_hcd_stop(int index) 119 { 120 return omap_ehci_hcd_stop(); 121 } 122 #endif 123 124 125 static inline void fpga_reset(int nassert) 126 { 127 gpio_set_value(FPGA_RESET, !nassert); 128 } 129 130 int fpga_pgm_fn(int nassert, int nflush, int cookie) 131 { 132 debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__); 133 134 gpio_set_value(FPGA_PROG, !nassert); 135 136 return nassert; 137 } 138 139 int fpga_init_fn(int cookie) 140 { 141 return !gpio_get_value(FPGA_INIT); 142 } 143 144 int fpga_done_fn(int cookie) 145 { 146 return gpio_get_value(FPGA_DONE); 147 } 148 149 int fpga_pre_config_fn(int cookie) 150 { 151 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); 152 153 /* Setting GPIOs for programming Mode */ 154 gpio_request(FPGA_RESET, "FPGA_RESET"); 155 gpio_direction_output(FPGA_RESET, 1); 156 gpio_request(FPGA_PROG, "FPGA_PROG"); 157 gpio_direction_output(FPGA_PROG, 1); 158 gpio_request(FPGA_CCLK, "FPGA_CCLK"); 159 gpio_direction_output(FPGA_CCLK, 1); 160 gpio_request(FPGA_DIN, "FPGA_DIN"); 161 gpio_direction_output(FPGA_DIN, 0); 162 gpio_request(FPGA_INIT, "FPGA_INIT"); 163 gpio_direction_input(FPGA_INIT); 164 gpio_request(FPGA_DONE, "FPGA_DONE"); 165 gpio_direction_input(FPGA_DONE); 166 167 /* Be sure that signal are deasserted */ 168 gpio_set_value(FPGA_RESET, 1); 169 gpio_set_value(FPGA_PROG, 1); 170 171 return 0; 172 } 173 174 int fpga_post_config_fn(int cookie) 175 { 176 debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); 177 178 fpga_reset(TRUE); 179 udelay(100); 180 fpga_reset(FALSE); 181 182 return 0; 183 } 184 185 /* Write program to the FPGA */ 186 int fpga_wr_fn(int nassert_write, int flush, int cookie) 187 { 188 gpio_set_value(FPGA_DIN, nassert_write); 189 190 return nassert_write; 191 } 192 193 int fpga_clk_fn(int assert_clk, int flush, int cookie) 194 { 195 gpio_set_value(FPGA_CCLK, assert_clk); 196 197 return assert_clk; 198 } 199 200 Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { 201 fpga_pre_config_fn, 202 fpga_pgm_fn, 203 fpga_clk_fn, 204 fpga_init_fn, 205 fpga_done_fn, 206 fpga_wr_fn, 207 fpga_post_config_fn, 208 }; 209 210 Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, 211 (void *)&mt_ventoux_fpga_fns, 0); 212 213 /* Initialize the FPGA */ 214 static void mt_ventoux_init_fpga(void) 215 { 216 fpga_pre_config_fn(0); 217 218 /* Setting CS1 for FPGA access */ 219 enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1], 220 FPGA_BASE_ADDR, GPMC_SIZE_128M); 221 222 fpga_init(); 223 fpga_add(fpga_xilinx, &fpga); 224 } 225 226 /* 227 * Routine: board_init 228 * Description: Early hardware init. 229 */ 230 int board_init(void) 231 { 232 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 233 234 /* boot param addr */ 235 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 236 237 mt_ventoux_init_fpga(); 238 239 /* GPIO_140: speaker #mute */ 240 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) 241 /* GPIO_141: Buzz Hi */ 242 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) 243 244 /* Turning off the buzzer */ 245 gpio_request(BUZZER, "BUZZER_MUTE"); 246 gpio_request(SPEAKER, "SPEAKER"); 247 gpio_direction_output(BUZZER, 0); 248 gpio_direction_output(SPEAKER, 0); 249 250 return 0; 251 } 252 253 int misc_init_r(void) 254 { 255 char *eth_addr; 256 257 dieid_num_r(); 258 259 eth_addr = getenv("ethaddr"); 260 if (eth_addr) 261 return 0; 262 263 #ifndef CONFIG_SPL_BUILD 264 TAM3517_READ_MAC_FROM_EEPROM; 265 #endif 266 return 0; 267 } 268 269 /* 270 * Routine: set_muxconf_regs 271 * Description: Setting up the configuration Mux registers specific to the 272 * hardware. Many pins need to be moved from protect to primary 273 * mode. 274 */ 275 void set_muxconf_regs(void) 276 { 277 MUX_MT_VENTOUX(); 278 } 279 280 /* 281 * Initializes on-chip ethernet controllers. 282 * to override, implement board_eth_init() 283 */ 284 int board_eth_init(bd_t *bis) 285 { 286 davinci_emac_initialize(); 287 return 0; 288 } 289 290 #if defined(CONFIG_OMAP_HSMMC) && \ 291 !defined(CONFIG_SPL_BUILD) 292 int board_mmc_init(bd_t *bis) 293 { 294 return omap_mmc_init(0, 0, 0); 295 } 296 #endif 297 298 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 299 int board_video_init(void) 300 { 301 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 302 struct panel_config *panel = &lcd_cfg[0]; 303 char *s; 304 u32 index = 0; 305 306 void *fb; 307 308 fb = (void *)0x88000000; 309 310 s = getenv("panel"); 311 if (s) { 312 index = simple_strtoul(s, NULL, 10); 313 if (index < ARRAY_SIZE(lcd_cfg)) 314 panel = &lcd_cfg[index]; 315 else 316 return 0; 317 } 318 319 panel->frame_buffer = fb; 320 printf("Panel: %dx%d\n", panel_resolution[index].xres, 321 panel_resolution[index].yres); 322 panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | 323 (panel_resolution[index].xres - 1); 324 325 gpio_request(LCD_PWR, "LCD Power"); 326 gpio_request(LCD_PON_PIN, "LCD Pon"); 327 gpio_direction_output(LCD_PWR, 0); 328 gpio_direction_output(LCD_PON_PIN, 1); 329 330 331 setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); 332 setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); 333 334 omap3_dss_panel_config(panel); 335 omap3_dss_enable(); 336 337 return 0; 338 } 339 #endif 340