11fdabeddSStefano Babic /* 21fdabeddSStefano Babic * Copyright (C) 2011 31fdabeddSStefano Babic * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 41fdabeddSStefano Babic * 51fdabeddSStefano Babic * Copyright (C) 2009 TechNexion Ltd. 61fdabeddSStefano Babic * 71fdabeddSStefano Babic * This program is free software; you can redistribute it and/or modify 81fdabeddSStefano Babic * it under the terms of the GNU General Public License as published by 91fdabeddSStefano Babic * the Free Software Foundation; either version 2 of the License, or 101fdabeddSStefano Babic * (at your option) any later version. 111fdabeddSStefano Babic * 121fdabeddSStefano Babic * This program is distributed in the hope that it will be useful, 131fdabeddSStefano Babic * but WITHOUT ANY WARRANTY; without even the implied warranty of 141fdabeddSStefano Babic * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 151fdabeddSStefano Babic * GNU General Public License for more details. 161fdabeddSStefano Babic * 171fdabeddSStefano Babic * You should have received a copy of the GNU General Public License 181fdabeddSStefano Babic * along with this program; if not, write to the Free Software 191fdabeddSStefano Babic * Foundation, Inc. 201fdabeddSStefano Babic */ 211fdabeddSStefano Babic 221fdabeddSStefano Babic #include <common.h> 231fdabeddSStefano Babic #include <netdev.h> 2462986875SStefano Babic #include <malloc.h> 251fdabeddSStefano Babic #include <fpga.h> 2662986875SStefano Babic #include <video_fb.h> 271fdabeddSStefano Babic #include <asm/io.h> 281fdabeddSStefano Babic #include <asm/arch/mem.h> 291fdabeddSStefano Babic #include <asm/arch/mux.h> 301fdabeddSStefano Babic #include <asm/arch/sys_proto.h> 311fdabeddSStefano Babic #include <asm/omap_gpio.h> 321fdabeddSStefano Babic #include <asm/arch/mmc_host_def.h> 3362986875SStefano Babic #include <asm/arch/dss.h> 3462986875SStefano Babic #include <asm/arch/clocks.h> 351fdabeddSStefano Babic #include <i2c.h> 361fdabeddSStefano Babic #include <spartan3.h> 371fdabeddSStefano Babic #include <asm/gpio.h> 381fdabeddSStefano Babic #ifdef CONFIG_USB_EHCI 391fdabeddSStefano Babic #include <usb.h> 401fdabeddSStefano Babic #include <asm/ehci-omap.h> 411fdabeddSStefano Babic #endif 421fdabeddSStefano Babic #include "mt_ventoux.h" 431fdabeddSStefano Babic 441fdabeddSStefano Babic DECLARE_GLOBAL_DATA_PTR; 451fdabeddSStefano Babic 46ff530fc7SStefano Babic #define BUZZER 140 47ff530fc7SStefano Babic #define SPEAKER 141 48*9f670540SStefano Babic #define USB1_PWR 127 49*9f670540SStefano Babic #define USB2_PWR 149 50ff530fc7SStefano Babic 511fdabeddSStefano Babic #ifndef CONFIG_FPGA 521fdabeddSStefano Babic #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" 531fdabeddSStefano Babic #endif 541fdabeddSStefano Babic 551fdabeddSStefano Babic #define FPGA_RESET 62 561fdabeddSStefano Babic #define FPGA_PROG 116 571fdabeddSStefano Babic #define FPGA_CCLK 117 581fdabeddSStefano Babic #define FPGA_DIN 118 591fdabeddSStefano Babic #define FPGA_INIT 119 601fdabeddSStefano Babic #define FPGA_DONE 154 611fdabeddSStefano Babic 6262986875SStefano Babic #define LCD_PWR 138 6362986875SStefano Babic #define LCD_PON_PIN 139 6462986875SStefano Babic 6562986875SStefano Babic #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 6662986875SStefano Babic static struct { 6762986875SStefano Babic u32 xres; 6862986875SStefano Babic u32 yres; 6962986875SStefano Babic } panel_resolution[] = { 7062986875SStefano Babic { 480, 272 }, 7162986875SStefano Babic { 800, 480 } 7262986875SStefano Babic }; 7362986875SStefano Babic 7462986875SStefano Babic static struct panel_config lcd_cfg[] = { 7562986875SStefano Babic { 7662986875SStefano Babic .timing_h = PANEL_TIMING_H(4, 8, 41), 7762986875SStefano Babic .timing_v = PANEL_TIMING_V(2, 4, 10), 7862986875SStefano Babic .pol_freq = 0x00000000, /* Pol Freq */ 7962986875SStefano Babic .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ 8062986875SStefano Babic .panel_type = 0x01, /* TFT */ 8162986875SStefano Babic .data_lines = 0x03, /* 24 Bit RGB */ 8262986875SStefano Babic .load_mode = 0x02, /* Frame Mode */ 8362986875SStefano Babic .panel_color = 0, 8462986875SStefano Babic }, 8562986875SStefano Babic { 8662986875SStefano Babic .timing_h = PANEL_TIMING_H(20, 192, 4), 8762986875SStefano Babic .timing_v = PANEL_TIMING_V(2, 20, 10), 8862986875SStefano Babic .pol_freq = 0x00004000, /* Pol Freq */ 8962986875SStefano Babic .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ 9062986875SStefano Babic .panel_type = 0x01, /* TFT */ 9162986875SStefano Babic .data_lines = 0x03, /* 24 Bit RGB */ 9262986875SStefano Babic .load_mode = 0x02, /* Frame Mode */ 9362986875SStefano Babic .panel_color = 0, 9462986875SStefano Babic } 9562986875SStefano Babic }; 9662986875SStefano Babic #endif 9762986875SStefano Babic 981fdabeddSStefano Babic /* Timing definitions for FPGA */ 991fdabeddSStefano Babic static const u32 gpmc_fpga[] = { 1001fdabeddSStefano Babic FPGA_GPMC_CONFIG1, 1011fdabeddSStefano Babic FPGA_GPMC_CONFIG2, 1021fdabeddSStefano Babic FPGA_GPMC_CONFIG3, 1031fdabeddSStefano Babic FPGA_GPMC_CONFIG4, 1041fdabeddSStefano Babic FPGA_GPMC_CONFIG5, 1051fdabeddSStefano Babic FPGA_GPMC_CONFIG6, 1061fdabeddSStefano Babic }; 1071fdabeddSStefano Babic 1081fdabeddSStefano Babic #ifdef CONFIG_USB_EHCI 1091fdabeddSStefano Babic static struct omap_usbhs_board_data usbhs_bdata = { 1101fdabeddSStefano Babic .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 1111fdabeddSStefano Babic .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 1121fdabeddSStefano Babic .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 1131fdabeddSStefano Babic }; 1141fdabeddSStefano Babic 115676ae068SLucas Stach int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 1161fdabeddSStefano Babic { 117676ae068SLucas Stach return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); 1181fdabeddSStefano Babic } 1191fdabeddSStefano Babic 120676ae068SLucas Stach int ehci_hcd_stop(int index) 1211fdabeddSStefano Babic { 1221fdabeddSStefano Babic return omap_ehci_hcd_stop(); 1231fdabeddSStefano Babic } 1241fdabeddSStefano Babic #endif 1251fdabeddSStefano Babic 1261fdabeddSStefano Babic 1271fdabeddSStefano Babic static inline void fpga_reset(int nassert) 1281fdabeddSStefano Babic { 1291fdabeddSStefano Babic gpio_set_value(FPGA_RESET, !nassert); 1301fdabeddSStefano Babic } 1311fdabeddSStefano Babic 1321fdabeddSStefano Babic int fpga_pgm_fn(int nassert, int nflush, int cookie) 1331fdabeddSStefano Babic { 1341fdabeddSStefano Babic debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__); 1351fdabeddSStefano Babic 1361fdabeddSStefano Babic gpio_set_value(FPGA_PROG, !nassert); 1371fdabeddSStefano Babic 1381fdabeddSStefano Babic return nassert; 1391fdabeddSStefano Babic } 1401fdabeddSStefano Babic 1411fdabeddSStefano Babic int fpga_init_fn(int cookie) 1421fdabeddSStefano Babic { 1431fdabeddSStefano Babic return !gpio_get_value(FPGA_INIT); 1441fdabeddSStefano Babic } 1451fdabeddSStefano Babic 1461fdabeddSStefano Babic int fpga_done_fn(int cookie) 1471fdabeddSStefano Babic { 1481fdabeddSStefano Babic return gpio_get_value(FPGA_DONE); 1491fdabeddSStefano Babic } 1501fdabeddSStefano Babic 1511fdabeddSStefano Babic int fpga_pre_config_fn(int cookie) 1521fdabeddSStefano Babic { 1531fdabeddSStefano Babic debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); 1541fdabeddSStefano Babic 1551fdabeddSStefano Babic /* Setting GPIOs for programming Mode */ 1561fdabeddSStefano Babic gpio_request(FPGA_RESET, "FPGA_RESET"); 1571fdabeddSStefano Babic gpio_direction_output(FPGA_RESET, 1); 1581fdabeddSStefano Babic gpio_request(FPGA_PROG, "FPGA_PROG"); 1591fdabeddSStefano Babic gpio_direction_output(FPGA_PROG, 1); 1601fdabeddSStefano Babic gpio_request(FPGA_CCLK, "FPGA_CCLK"); 1611fdabeddSStefano Babic gpio_direction_output(FPGA_CCLK, 1); 1621fdabeddSStefano Babic gpio_request(FPGA_DIN, "FPGA_DIN"); 1631fdabeddSStefano Babic gpio_direction_output(FPGA_DIN, 0); 1641fdabeddSStefano Babic gpio_request(FPGA_INIT, "FPGA_INIT"); 1651fdabeddSStefano Babic gpio_direction_input(FPGA_INIT); 1661fdabeddSStefano Babic gpio_request(FPGA_DONE, "FPGA_DONE"); 1671fdabeddSStefano Babic gpio_direction_input(FPGA_DONE); 1681fdabeddSStefano Babic 1691fdabeddSStefano Babic /* Be sure that signal are deasserted */ 1701fdabeddSStefano Babic gpio_set_value(FPGA_RESET, 1); 1711fdabeddSStefano Babic gpio_set_value(FPGA_PROG, 1); 1721fdabeddSStefano Babic 1731fdabeddSStefano Babic return 0; 1741fdabeddSStefano Babic } 1751fdabeddSStefano Babic 1761fdabeddSStefano Babic int fpga_post_config_fn(int cookie) 1771fdabeddSStefano Babic { 1781fdabeddSStefano Babic debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); 1791fdabeddSStefano Babic 1801fdabeddSStefano Babic fpga_reset(TRUE); 1811fdabeddSStefano Babic udelay(100); 1821fdabeddSStefano Babic fpga_reset(FALSE); 1831fdabeddSStefano Babic 1841fdabeddSStefano Babic return 0; 1851fdabeddSStefano Babic } 1861fdabeddSStefano Babic 1871fdabeddSStefano Babic /* Write program to the FPGA */ 1881fdabeddSStefano Babic int fpga_wr_fn(int nassert_write, int flush, int cookie) 1891fdabeddSStefano Babic { 1901fdabeddSStefano Babic gpio_set_value(FPGA_DIN, nassert_write); 1911fdabeddSStefano Babic 1921fdabeddSStefano Babic return nassert_write; 1931fdabeddSStefano Babic } 1941fdabeddSStefano Babic 1951fdabeddSStefano Babic int fpga_clk_fn(int assert_clk, int flush, int cookie) 1961fdabeddSStefano Babic { 1971fdabeddSStefano Babic gpio_set_value(FPGA_CCLK, assert_clk); 1981fdabeddSStefano Babic 1991fdabeddSStefano Babic return assert_clk; 2001fdabeddSStefano Babic } 2011fdabeddSStefano Babic 2021fdabeddSStefano Babic Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { 2031fdabeddSStefano Babic fpga_pre_config_fn, 2041fdabeddSStefano Babic fpga_pgm_fn, 2051fdabeddSStefano Babic fpga_clk_fn, 2061fdabeddSStefano Babic fpga_init_fn, 2071fdabeddSStefano Babic fpga_done_fn, 2081fdabeddSStefano Babic fpga_wr_fn, 2091fdabeddSStefano Babic fpga_post_config_fn, 2101fdabeddSStefano Babic }; 2111fdabeddSStefano Babic 2121fdabeddSStefano Babic Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, 2131fdabeddSStefano Babic (void *)&mt_ventoux_fpga_fns, 0); 2141fdabeddSStefano Babic 2151fdabeddSStefano Babic /* Initialize the FPGA */ 2161fdabeddSStefano Babic static void mt_ventoux_init_fpga(void) 2171fdabeddSStefano Babic { 2181fdabeddSStefano Babic fpga_pre_config_fn(0); 2191fdabeddSStefano Babic 2201fdabeddSStefano Babic /* Setting CS1 for FPGA access */ 2211fdabeddSStefano Babic enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1], 2221fdabeddSStefano Babic FPGA_BASE_ADDR, GPMC_SIZE_128M); 2231fdabeddSStefano Babic 2241fdabeddSStefano Babic fpga_init(); 2251fdabeddSStefano Babic fpga_add(fpga_xilinx, &fpga); 2261fdabeddSStefano Babic } 2271fdabeddSStefano Babic 2281fdabeddSStefano Babic /* 2291fdabeddSStefano Babic * Routine: board_init 2301fdabeddSStefano Babic * Description: Early hardware init. 2311fdabeddSStefano Babic */ 2321fdabeddSStefano Babic int board_init(void) 2331fdabeddSStefano Babic { 2341fdabeddSStefano Babic gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 2351fdabeddSStefano Babic 2361fdabeddSStefano Babic /* boot param addr */ 2371fdabeddSStefano Babic gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 2381fdabeddSStefano Babic 2391fdabeddSStefano Babic mt_ventoux_init_fpga(); 2401fdabeddSStefano Babic 241ff530fc7SStefano Babic /* GPIO_140: speaker #mute */ 242ff530fc7SStefano Babic MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) 243ff530fc7SStefano Babic /* GPIO_141: Buzz Hi */ 244ff530fc7SStefano Babic MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) 245ff530fc7SStefano Babic 246ff530fc7SStefano Babic /* Turning off the buzzer */ 247ff530fc7SStefano Babic gpio_request(BUZZER, "BUZZER_MUTE"); 248ff530fc7SStefano Babic gpio_request(SPEAKER, "SPEAKER"); 249ff530fc7SStefano Babic gpio_direction_output(BUZZER, 0); 250ff530fc7SStefano Babic gpio_direction_output(SPEAKER, 0); 251ff530fc7SStefano Babic 252*9f670540SStefano Babic /* Activate USB power */ 253*9f670540SStefano Babic gpio_request(USB1_PWR, "USB1_PWR"); 254*9f670540SStefano Babic gpio_request(USB2_PWR, "USB2_PWR"); 255*9f670540SStefano Babic gpio_direction_output(USB1_PWR, 1); 256*9f670540SStefano Babic gpio_direction_output(USB2_PWR, 1); 257*9f670540SStefano Babic 2581fdabeddSStefano Babic return 0; 2591fdabeddSStefano Babic } 2601fdabeddSStefano Babic 2619d5fc239SStefano Babic int misc_init_r(void) 2629d5fc239SStefano Babic { 2639d5fc239SStefano Babic char *eth_addr; 2649d5fc239SStefano Babic 2659d5fc239SStefano Babic dieid_num_r(); 2669d5fc239SStefano Babic 2679d5fc239SStefano Babic eth_addr = getenv("ethaddr"); 2689d5fc239SStefano Babic if (eth_addr) 2699d5fc239SStefano Babic return 0; 2709d5fc239SStefano Babic 2719d5fc239SStefano Babic #ifndef CONFIG_SPL_BUILD 2729d5fc239SStefano Babic TAM3517_READ_MAC_FROM_EEPROM; 2739d5fc239SStefano Babic #endif 2749d5fc239SStefano Babic return 0; 2759d5fc239SStefano Babic } 2769d5fc239SStefano Babic 2771fdabeddSStefano Babic /* 2781fdabeddSStefano Babic * Routine: set_muxconf_regs 2791fdabeddSStefano Babic * Description: Setting up the configuration Mux registers specific to the 2801fdabeddSStefano Babic * hardware. Many pins need to be moved from protect to primary 2811fdabeddSStefano Babic * mode. 2821fdabeddSStefano Babic */ 2831fdabeddSStefano Babic void set_muxconf_regs(void) 2841fdabeddSStefano Babic { 2851fdabeddSStefano Babic MUX_MT_VENTOUX(); 2861fdabeddSStefano Babic } 2871fdabeddSStefano Babic 2881fdabeddSStefano Babic /* 2891fdabeddSStefano Babic * Initializes on-chip ethernet controllers. 2901fdabeddSStefano Babic * to override, implement board_eth_init() 2911fdabeddSStefano Babic */ 2921fdabeddSStefano Babic int board_eth_init(bd_t *bis) 2931fdabeddSStefano Babic { 2941fdabeddSStefano Babic davinci_emac_initialize(); 2951fdabeddSStefano Babic return 0; 2961fdabeddSStefano Babic } 2971fdabeddSStefano Babic 2981fdabeddSStefano Babic #if defined(CONFIG_OMAP_HSMMC) && \ 2991fdabeddSStefano Babic !defined(CONFIG_SPL_BUILD) 3001fdabeddSStefano Babic int board_mmc_init(bd_t *bis) 3011fdabeddSStefano Babic { 302bbbc1ae9SJonathan Solnit return omap_mmc_init(0, 0, 0); 3031fdabeddSStefano Babic } 3041fdabeddSStefano Babic #endif 30562986875SStefano Babic 30662986875SStefano Babic #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 30762986875SStefano Babic int board_video_init(void) 30862986875SStefano Babic { 30962986875SStefano Babic struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 31062986875SStefano Babic struct panel_config *panel = &lcd_cfg[0]; 31162986875SStefano Babic char *s; 31262986875SStefano Babic u32 index = 0; 31362986875SStefano Babic 31462986875SStefano Babic void *fb; 31562986875SStefano Babic 31662986875SStefano Babic fb = (void *)0x88000000; 31762986875SStefano Babic 31862986875SStefano Babic s = getenv("panel"); 31962986875SStefano Babic if (s) { 32062986875SStefano Babic index = simple_strtoul(s, NULL, 10); 32162986875SStefano Babic if (index < ARRAY_SIZE(lcd_cfg)) 32262986875SStefano Babic panel = &lcd_cfg[index]; 32362986875SStefano Babic else 32462986875SStefano Babic return 0; 32562986875SStefano Babic } 32662986875SStefano Babic 32762986875SStefano Babic panel->frame_buffer = fb; 32862986875SStefano Babic printf("Panel: %dx%d\n", panel_resolution[index].xres, 32962986875SStefano Babic panel_resolution[index].yres); 33062986875SStefano Babic panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | 33162986875SStefano Babic (panel_resolution[index].xres - 1); 33262986875SStefano Babic 33362986875SStefano Babic gpio_request(LCD_PWR, "LCD Power"); 33462986875SStefano Babic gpio_request(LCD_PON_PIN, "LCD Pon"); 33562986875SStefano Babic gpio_direction_output(LCD_PWR, 0); 33662986875SStefano Babic gpio_direction_output(LCD_PON_PIN, 1); 33762986875SStefano Babic 33862986875SStefano Babic 33962986875SStefano Babic setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); 34062986875SStefano Babic setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); 34162986875SStefano Babic 34262986875SStefano Babic omap3_dss_panel_config(panel); 34362986875SStefano Babic omap3_dss_enable(); 34462986875SStefano Babic 34562986875SStefano Babic return 0; 34662986875SStefano Babic } 34762986875SStefano Babic #endif 348