11fdabeddSStefano Babic /* 21fdabeddSStefano Babic * Copyright (C) 2011 31fdabeddSStefano Babic * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 41fdabeddSStefano Babic * 51fdabeddSStefano Babic * Copyright (C) 2009 TechNexion Ltd. 61fdabeddSStefano Babic * 71fdabeddSStefano Babic * This program is free software; you can redistribute it and/or modify 81fdabeddSStefano Babic * it under the terms of the GNU General Public License as published by 91fdabeddSStefano Babic * the Free Software Foundation; either version 2 of the License, or 101fdabeddSStefano Babic * (at your option) any later version. 111fdabeddSStefano Babic * 121fdabeddSStefano Babic * This program is distributed in the hope that it will be useful, 131fdabeddSStefano Babic * but WITHOUT ANY WARRANTY; without even the implied warranty of 141fdabeddSStefano Babic * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 151fdabeddSStefano Babic * GNU General Public License for more details. 161fdabeddSStefano Babic * 171fdabeddSStefano Babic * You should have received a copy of the GNU General Public License 181fdabeddSStefano Babic * along with this program; if not, write to the Free Software 191fdabeddSStefano Babic * Foundation, Inc. 201fdabeddSStefano Babic */ 211fdabeddSStefano Babic 221fdabeddSStefano Babic #include <common.h> 231fdabeddSStefano Babic #include <netdev.h> 2462986875SStefano Babic #include <malloc.h> 251fdabeddSStefano Babic #include <fpga.h> 2662986875SStefano Babic #include <video_fb.h> 271fdabeddSStefano Babic #include <asm/io.h> 281fdabeddSStefano Babic #include <asm/arch/mem.h> 291fdabeddSStefano Babic #include <asm/arch/mux.h> 301fdabeddSStefano Babic #include <asm/arch/sys_proto.h> 311fdabeddSStefano Babic #include <asm/omap_gpio.h> 321fdabeddSStefano Babic #include <asm/arch/mmc_host_def.h> 3362986875SStefano Babic #include <asm/arch/dss.h> 3462986875SStefano Babic #include <asm/arch/clocks.h> 351fdabeddSStefano Babic #include <i2c.h> 361fdabeddSStefano Babic #include <spartan3.h> 371fdabeddSStefano Babic #include <asm/gpio.h> 381fdabeddSStefano Babic #ifdef CONFIG_USB_EHCI 391fdabeddSStefano Babic #include <usb.h> 401fdabeddSStefano Babic #include <asm/ehci-omap.h> 411fdabeddSStefano Babic #endif 421fdabeddSStefano Babic #include "mt_ventoux.h" 431fdabeddSStefano Babic 441fdabeddSStefano Babic DECLARE_GLOBAL_DATA_PTR; 451fdabeddSStefano Babic 46ff530fc7SStefano Babic #define BUZZER 140 47ff530fc7SStefano Babic #define SPEAKER 141 48ff530fc7SStefano Babic 491fdabeddSStefano Babic #ifndef CONFIG_FPGA 501fdabeddSStefano Babic #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled" 511fdabeddSStefano Babic #endif 521fdabeddSStefano Babic 531fdabeddSStefano Babic #define FPGA_RESET 62 541fdabeddSStefano Babic #define FPGA_PROG 116 551fdabeddSStefano Babic #define FPGA_CCLK 117 561fdabeddSStefano Babic #define FPGA_DIN 118 571fdabeddSStefano Babic #define FPGA_INIT 119 581fdabeddSStefano Babic #define FPGA_DONE 154 591fdabeddSStefano Babic 6062986875SStefano Babic #define LCD_PWR 138 6162986875SStefano Babic #define LCD_PON_PIN 139 6262986875SStefano Babic 6362986875SStefano Babic #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 6462986875SStefano Babic static struct { 6562986875SStefano Babic u32 xres; 6662986875SStefano Babic u32 yres; 6762986875SStefano Babic } panel_resolution[] = { 6862986875SStefano Babic { 480, 272 }, 6962986875SStefano Babic { 800, 480 } 7062986875SStefano Babic }; 7162986875SStefano Babic 7262986875SStefano Babic static struct panel_config lcd_cfg[] = { 7362986875SStefano Babic { 7462986875SStefano Babic .timing_h = PANEL_TIMING_H(4, 8, 41), 7562986875SStefano Babic .timing_v = PANEL_TIMING_V(2, 4, 10), 7662986875SStefano Babic .pol_freq = 0x00000000, /* Pol Freq */ 7762986875SStefano Babic .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ 7862986875SStefano Babic .panel_type = 0x01, /* TFT */ 7962986875SStefano Babic .data_lines = 0x03, /* 24 Bit RGB */ 8062986875SStefano Babic .load_mode = 0x02, /* Frame Mode */ 8162986875SStefano Babic .panel_color = 0, 8262986875SStefano Babic }, 8362986875SStefano Babic { 8462986875SStefano Babic .timing_h = PANEL_TIMING_H(20, 192, 4), 8562986875SStefano Babic .timing_v = PANEL_TIMING_V(2, 20, 10), 8662986875SStefano Babic .pol_freq = 0x00004000, /* Pol Freq */ 8762986875SStefano Babic .divisor = 0x0001000E, /* 36Mhz Pixel Clock */ 8862986875SStefano Babic .panel_type = 0x01, /* TFT */ 8962986875SStefano Babic .data_lines = 0x03, /* 24 Bit RGB */ 9062986875SStefano Babic .load_mode = 0x02, /* Frame Mode */ 9162986875SStefano Babic .panel_color = 0, 9262986875SStefano Babic } 9362986875SStefano Babic }; 9462986875SStefano Babic #endif 9562986875SStefano Babic 961fdabeddSStefano Babic /* Timing definitions for FPGA */ 971fdabeddSStefano Babic static const u32 gpmc_fpga[] = { 981fdabeddSStefano Babic FPGA_GPMC_CONFIG1, 991fdabeddSStefano Babic FPGA_GPMC_CONFIG2, 1001fdabeddSStefano Babic FPGA_GPMC_CONFIG3, 1011fdabeddSStefano Babic FPGA_GPMC_CONFIG4, 1021fdabeddSStefano Babic FPGA_GPMC_CONFIG5, 1031fdabeddSStefano Babic FPGA_GPMC_CONFIG6, 1041fdabeddSStefano Babic }; 1051fdabeddSStefano Babic 1061fdabeddSStefano Babic #ifdef CONFIG_USB_EHCI 1071fdabeddSStefano Babic static struct omap_usbhs_board_data usbhs_bdata = { 1081fdabeddSStefano Babic .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 1091fdabeddSStefano Babic .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 1101fdabeddSStefano Babic .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 1111fdabeddSStefano Babic }; 1121fdabeddSStefano Babic 113*676ae068SLucas Stach int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) 1141fdabeddSStefano Babic { 115*676ae068SLucas Stach return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); 1161fdabeddSStefano Babic } 1171fdabeddSStefano Babic 118*676ae068SLucas Stach int ehci_hcd_stop(int index) 1191fdabeddSStefano Babic { 1201fdabeddSStefano Babic return omap_ehci_hcd_stop(); 1211fdabeddSStefano Babic } 1221fdabeddSStefano Babic #endif 1231fdabeddSStefano Babic 1241fdabeddSStefano Babic 1251fdabeddSStefano Babic static inline void fpga_reset(int nassert) 1261fdabeddSStefano Babic { 1271fdabeddSStefano Babic gpio_set_value(FPGA_RESET, !nassert); 1281fdabeddSStefano Babic } 1291fdabeddSStefano Babic 1301fdabeddSStefano Babic int fpga_pgm_fn(int nassert, int nflush, int cookie) 1311fdabeddSStefano Babic { 1321fdabeddSStefano Babic debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__); 1331fdabeddSStefano Babic 1341fdabeddSStefano Babic gpio_set_value(FPGA_PROG, !nassert); 1351fdabeddSStefano Babic 1361fdabeddSStefano Babic return nassert; 1371fdabeddSStefano Babic } 1381fdabeddSStefano Babic 1391fdabeddSStefano Babic int fpga_init_fn(int cookie) 1401fdabeddSStefano Babic { 1411fdabeddSStefano Babic return !gpio_get_value(FPGA_INIT); 1421fdabeddSStefano Babic } 1431fdabeddSStefano Babic 1441fdabeddSStefano Babic int fpga_done_fn(int cookie) 1451fdabeddSStefano Babic { 1461fdabeddSStefano Babic return gpio_get_value(FPGA_DONE); 1471fdabeddSStefano Babic } 1481fdabeddSStefano Babic 1491fdabeddSStefano Babic int fpga_pre_config_fn(int cookie) 1501fdabeddSStefano Babic { 1511fdabeddSStefano Babic debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); 1521fdabeddSStefano Babic 1531fdabeddSStefano Babic /* Setting GPIOs for programming Mode */ 1541fdabeddSStefano Babic gpio_request(FPGA_RESET, "FPGA_RESET"); 1551fdabeddSStefano Babic gpio_direction_output(FPGA_RESET, 1); 1561fdabeddSStefano Babic gpio_request(FPGA_PROG, "FPGA_PROG"); 1571fdabeddSStefano Babic gpio_direction_output(FPGA_PROG, 1); 1581fdabeddSStefano Babic gpio_request(FPGA_CCLK, "FPGA_CCLK"); 1591fdabeddSStefano Babic gpio_direction_output(FPGA_CCLK, 1); 1601fdabeddSStefano Babic gpio_request(FPGA_DIN, "FPGA_DIN"); 1611fdabeddSStefano Babic gpio_direction_output(FPGA_DIN, 0); 1621fdabeddSStefano Babic gpio_request(FPGA_INIT, "FPGA_INIT"); 1631fdabeddSStefano Babic gpio_direction_input(FPGA_INIT); 1641fdabeddSStefano Babic gpio_request(FPGA_DONE, "FPGA_DONE"); 1651fdabeddSStefano Babic gpio_direction_input(FPGA_DONE); 1661fdabeddSStefano Babic 1671fdabeddSStefano Babic /* Be sure that signal are deasserted */ 1681fdabeddSStefano Babic gpio_set_value(FPGA_RESET, 1); 1691fdabeddSStefano Babic gpio_set_value(FPGA_PROG, 1); 1701fdabeddSStefano Babic 1711fdabeddSStefano Babic return 0; 1721fdabeddSStefano Babic } 1731fdabeddSStefano Babic 1741fdabeddSStefano Babic int fpga_post_config_fn(int cookie) 1751fdabeddSStefano Babic { 1761fdabeddSStefano Babic debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); 1771fdabeddSStefano Babic 1781fdabeddSStefano Babic fpga_reset(TRUE); 1791fdabeddSStefano Babic udelay(100); 1801fdabeddSStefano Babic fpga_reset(FALSE); 1811fdabeddSStefano Babic 1821fdabeddSStefano Babic return 0; 1831fdabeddSStefano Babic } 1841fdabeddSStefano Babic 1851fdabeddSStefano Babic /* Write program to the FPGA */ 1861fdabeddSStefano Babic int fpga_wr_fn(int nassert_write, int flush, int cookie) 1871fdabeddSStefano Babic { 1881fdabeddSStefano Babic gpio_set_value(FPGA_DIN, nassert_write); 1891fdabeddSStefano Babic 1901fdabeddSStefano Babic return nassert_write; 1911fdabeddSStefano Babic } 1921fdabeddSStefano Babic 1931fdabeddSStefano Babic int fpga_clk_fn(int assert_clk, int flush, int cookie) 1941fdabeddSStefano Babic { 1951fdabeddSStefano Babic gpio_set_value(FPGA_CCLK, assert_clk); 1961fdabeddSStefano Babic 1971fdabeddSStefano Babic return assert_clk; 1981fdabeddSStefano Babic } 1991fdabeddSStefano Babic 2001fdabeddSStefano Babic Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { 2011fdabeddSStefano Babic fpga_pre_config_fn, 2021fdabeddSStefano Babic fpga_pgm_fn, 2031fdabeddSStefano Babic fpga_clk_fn, 2041fdabeddSStefano Babic fpga_init_fn, 2051fdabeddSStefano Babic fpga_done_fn, 2061fdabeddSStefano Babic fpga_wr_fn, 2071fdabeddSStefano Babic fpga_post_config_fn, 2081fdabeddSStefano Babic }; 2091fdabeddSStefano Babic 2101fdabeddSStefano Babic Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, 2111fdabeddSStefano Babic (void *)&mt_ventoux_fpga_fns, 0); 2121fdabeddSStefano Babic 2131fdabeddSStefano Babic /* Initialize the FPGA */ 2141fdabeddSStefano Babic static void mt_ventoux_init_fpga(void) 2151fdabeddSStefano Babic { 2161fdabeddSStefano Babic fpga_pre_config_fn(0); 2171fdabeddSStefano Babic 2181fdabeddSStefano Babic /* Setting CS1 for FPGA access */ 2191fdabeddSStefano Babic enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1], 2201fdabeddSStefano Babic FPGA_BASE_ADDR, GPMC_SIZE_128M); 2211fdabeddSStefano Babic 2221fdabeddSStefano Babic fpga_init(); 2231fdabeddSStefano Babic fpga_add(fpga_xilinx, &fpga); 2241fdabeddSStefano Babic } 2251fdabeddSStefano Babic 2261fdabeddSStefano Babic /* 2271fdabeddSStefano Babic * Routine: board_init 2281fdabeddSStefano Babic * Description: Early hardware init. 2291fdabeddSStefano Babic */ 2301fdabeddSStefano Babic int board_init(void) 2311fdabeddSStefano Babic { 2321fdabeddSStefano Babic gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 2331fdabeddSStefano Babic 2341fdabeddSStefano Babic /* boot param addr */ 2351fdabeddSStefano Babic gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 2361fdabeddSStefano Babic 2371fdabeddSStefano Babic mt_ventoux_init_fpga(); 2381fdabeddSStefano Babic 239ff530fc7SStefano Babic /* GPIO_140: speaker #mute */ 240ff530fc7SStefano Babic MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) 241ff530fc7SStefano Babic /* GPIO_141: Buzz Hi */ 242ff530fc7SStefano Babic MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) 243ff530fc7SStefano Babic 244ff530fc7SStefano Babic /* Turning off the buzzer */ 245ff530fc7SStefano Babic gpio_request(BUZZER, "BUZZER_MUTE"); 246ff530fc7SStefano Babic gpio_request(SPEAKER, "SPEAKER"); 247ff530fc7SStefano Babic gpio_direction_output(BUZZER, 0); 248ff530fc7SStefano Babic gpio_direction_output(SPEAKER, 0); 249ff530fc7SStefano Babic 2501fdabeddSStefano Babic return 0; 2511fdabeddSStefano Babic } 2521fdabeddSStefano Babic 2539d5fc239SStefano Babic int misc_init_r(void) 2549d5fc239SStefano Babic { 2559d5fc239SStefano Babic char *eth_addr; 2569d5fc239SStefano Babic 2579d5fc239SStefano Babic dieid_num_r(); 2589d5fc239SStefano Babic 2599d5fc239SStefano Babic eth_addr = getenv("ethaddr"); 2609d5fc239SStefano Babic if (eth_addr) 2619d5fc239SStefano Babic return 0; 2629d5fc239SStefano Babic 2639d5fc239SStefano Babic #ifndef CONFIG_SPL_BUILD 2649d5fc239SStefano Babic TAM3517_READ_MAC_FROM_EEPROM; 2659d5fc239SStefano Babic #endif 2669d5fc239SStefano Babic return 0; 2679d5fc239SStefano Babic } 2689d5fc239SStefano Babic 2691fdabeddSStefano Babic /* 2701fdabeddSStefano Babic * Routine: set_muxconf_regs 2711fdabeddSStefano Babic * Description: Setting up the configuration Mux registers specific to the 2721fdabeddSStefano Babic * hardware. Many pins need to be moved from protect to primary 2731fdabeddSStefano Babic * mode. 2741fdabeddSStefano Babic */ 2751fdabeddSStefano Babic void set_muxconf_regs(void) 2761fdabeddSStefano Babic { 2771fdabeddSStefano Babic MUX_MT_VENTOUX(); 2781fdabeddSStefano Babic } 2791fdabeddSStefano Babic 2801fdabeddSStefano Babic /* 2811fdabeddSStefano Babic * Initializes on-chip ethernet controllers. 2821fdabeddSStefano Babic * to override, implement board_eth_init() 2831fdabeddSStefano Babic */ 2841fdabeddSStefano Babic int board_eth_init(bd_t *bis) 2851fdabeddSStefano Babic { 2861fdabeddSStefano Babic davinci_emac_initialize(); 2871fdabeddSStefano Babic return 0; 2881fdabeddSStefano Babic } 2891fdabeddSStefano Babic 2901fdabeddSStefano Babic #if defined(CONFIG_OMAP_HSMMC) && \ 2911fdabeddSStefano Babic !defined(CONFIG_SPL_BUILD) 2921fdabeddSStefano Babic int board_mmc_init(bd_t *bis) 2931fdabeddSStefano Babic { 294bbbc1ae9SJonathan Solnit return omap_mmc_init(0, 0, 0); 2951fdabeddSStefano Babic } 2961fdabeddSStefano Babic #endif 29762986875SStefano Babic 29862986875SStefano Babic #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) 29962986875SStefano Babic int board_video_init(void) 30062986875SStefano Babic { 30162986875SStefano Babic struct prcm *prcm_base = (struct prcm *)PRCM_BASE; 30262986875SStefano Babic struct panel_config *panel = &lcd_cfg[0]; 30362986875SStefano Babic char *s; 30462986875SStefano Babic u32 index = 0; 30562986875SStefano Babic 30662986875SStefano Babic void *fb; 30762986875SStefano Babic 30862986875SStefano Babic fb = (void *)0x88000000; 30962986875SStefano Babic 31062986875SStefano Babic s = getenv("panel"); 31162986875SStefano Babic if (s) { 31262986875SStefano Babic index = simple_strtoul(s, NULL, 10); 31362986875SStefano Babic if (index < ARRAY_SIZE(lcd_cfg)) 31462986875SStefano Babic panel = &lcd_cfg[index]; 31562986875SStefano Babic else 31662986875SStefano Babic return 0; 31762986875SStefano Babic } 31862986875SStefano Babic 31962986875SStefano Babic panel->frame_buffer = fb; 32062986875SStefano Babic printf("Panel: %dx%d\n", panel_resolution[index].xres, 32162986875SStefano Babic panel_resolution[index].yres); 32262986875SStefano Babic panel->lcd_size = (panel_resolution[index].yres - 1) << 16 | 32362986875SStefano Babic (panel_resolution[index].xres - 1); 32462986875SStefano Babic 32562986875SStefano Babic gpio_request(LCD_PWR, "LCD Power"); 32662986875SStefano Babic gpio_request(LCD_PON_PIN, "LCD Pon"); 32762986875SStefano Babic gpio_direction_output(LCD_PWR, 0); 32862986875SStefano Babic gpio_direction_output(LCD_PON_PIN, 1); 32962986875SStefano Babic 33062986875SStefano Babic 33162986875SStefano Babic setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON); 33262986875SStefano Babic setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON); 33362986875SStefano Babic 33462986875SStefano Babic omap3_dss_panel_config(panel); 33562986875SStefano Babic omap3_dss_enable(); 33662986875SStefano Babic 33762986875SStefano Babic return 0; 33862986875SStefano Babic } 33962986875SStefano Babic #endif 340