1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
21fdabeddSStefano Babic /*
31fdabeddSStefano Babic * Copyright (C) 2011
41fdabeddSStefano Babic * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
51fdabeddSStefano Babic *
61fdabeddSStefano Babic * Copyright (C) 2009 TechNexion Ltd.
71fdabeddSStefano Babic */
81fdabeddSStefano Babic
91fdabeddSStefano Babic #include <common.h>
101fdabeddSStefano Babic #include <netdev.h>
1162986875SStefano Babic #include <malloc.h>
121fdabeddSStefano Babic #include <fpga.h>
1362986875SStefano Babic #include <video_fb.h>
141fdabeddSStefano Babic #include <asm/io.h>
151fdabeddSStefano Babic #include <asm/arch/mem.h>
161fdabeddSStefano Babic #include <asm/arch/mux.h>
171fdabeddSStefano Babic #include <asm/arch/sys_proto.h>
181fdabeddSStefano Babic #include <asm/omap_gpio.h>
191fdabeddSStefano Babic #include <asm/arch/mmc_host_def.h>
2062986875SStefano Babic #include <asm/arch/dss.h>
21af1d002fSLokesh Vutla #include <asm/arch/clock.h>
221fdabeddSStefano Babic #include <i2c.h>
231fdabeddSStefano Babic #include <spartan3.h>
241fdabeddSStefano Babic #include <asm/gpio.h>
258850c5d5STom Rini #ifdef CONFIG_USB_EHCI_HCD
261fdabeddSStefano Babic #include <usb.h>
271fdabeddSStefano Babic #include <asm/ehci-omap.h>
281fdabeddSStefano Babic #endif
291fdabeddSStefano Babic #include "mt_ventoux.h"
301fdabeddSStefano Babic
311fdabeddSStefano Babic DECLARE_GLOBAL_DATA_PTR;
321fdabeddSStefano Babic
33ff530fc7SStefano Babic #define BUZZER 140
34ff530fc7SStefano Babic #define SPEAKER 141
359f670540SStefano Babic #define USB1_PWR 127
369f670540SStefano Babic #define USB2_PWR 149
37ff530fc7SStefano Babic
381fdabeddSStefano Babic #ifndef CONFIG_FPGA
391fdabeddSStefano Babic #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
401fdabeddSStefano Babic #endif
411fdabeddSStefano Babic
421fdabeddSStefano Babic #define FPGA_RESET 62
431fdabeddSStefano Babic #define FPGA_PROG 116
441fdabeddSStefano Babic #define FPGA_CCLK 117
451fdabeddSStefano Babic #define FPGA_DIN 118
461fdabeddSStefano Babic #define FPGA_INIT 119
471fdabeddSStefano Babic #define FPGA_DONE 154
481fdabeddSStefano Babic
4962986875SStefano Babic #define LCD_PWR 138
5062986875SStefano Babic #define LCD_PON_PIN 139
5162986875SStefano Babic
5262986875SStefano Babic #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
5362986875SStefano Babic static struct {
5462986875SStefano Babic u32 xres;
5562986875SStefano Babic u32 yres;
5662986875SStefano Babic } panel_resolution[] = {
5762986875SStefano Babic { 480, 272 },
5862986875SStefano Babic { 800, 480 }
5962986875SStefano Babic };
6062986875SStefano Babic
6162986875SStefano Babic static struct panel_config lcd_cfg[] = {
6262986875SStefano Babic {
63fe2d59a1SStefano Babic .timing_h = PANEL_TIMING_H(40, 5, 2),
64fe2d59a1SStefano Babic .timing_v = PANEL_TIMING_V(8, 8, 2),
65fe2d59a1SStefano Babic .pol_freq = 0x00003000, /* Pol Freq */
66fe2d59a1SStefano Babic .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
6762986875SStefano Babic .panel_type = 0x01, /* TFT */
6862986875SStefano Babic .data_lines = 0x03, /* 24 Bit RGB */
6962986875SStefano Babic .load_mode = 0x02, /* Frame Mode */
7062986875SStefano Babic .panel_color = 0,
71bcc6cc9bSNikita Kiryanov .gfx_format = GFXFORMAT_RGB24_UNPACKED,
7262986875SStefano Babic },
7362986875SStefano Babic {
7462986875SStefano Babic .timing_h = PANEL_TIMING_H(20, 192, 4),
7562986875SStefano Babic .timing_v = PANEL_TIMING_V(2, 20, 10),
7662986875SStefano Babic .pol_freq = 0x00004000, /* Pol Freq */
7762986875SStefano Babic .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
7862986875SStefano Babic .panel_type = 0x01, /* TFT */
7962986875SStefano Babic .data_lines = 0x03, /* 24 Bit RGB */
8062986875SStefano Babic .load_mode = 0x02, /* Frame Mode */
8162986875SStefano Babic .panel_color = 0,
82bcc6cc9bSNikita Kiryanov .gfx_format = GFXFORMAT_RGB24_UNPACKED,
8362986875SStefano Babic }
8462986875SStefano Babic };
8562986875SStefano Babic #endif
8662986875SStefano Babic
871fdabeddSStefano Babic /* Timing definitions for FPGA */
881fdabeddSStefano Babic static const u32 gpmc_fpga[] = {
891fdabeddSStefano Babic FPGA_GPMC_CONFIG1,
901fdabeddSStefano Babic FPGA_GPMC_CONFIG2,
911fdabeddSStefano Babic FPGA_GPMC_CONFIG3,
921fdabeddSStefano Babic FPGA_GPMC_CONFIG4,
931fdabeddSStefano Babic FPGA_GPMC_CONFIG5,
941fdabeddSStefano Babic FPGA_GPMC_CONFIG6,
951fdabeddSStefano Babic };
961fdabeddSStefano Babic
978850c5d5STom Rini #ifdef CONFIG_USB_EHCI_HCD
981fdabeddSStefano Babic static struct omap_usbhs_board_data usbhs_bdata = {
991fdabeddSStefano Babic .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
1001fdabeddSStefano Babic .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
1011fdabeddSStefano Babic .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
1021fdabeddSStefano Babic };
1031fdabeddSStefano Babic
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)104127efc4fSTroy Kisky int ehci_hcd_init(int index, enum usb_init_type init,
105127efc4fSTroy Kisky struct ehci_hccr **hccr, struct ehci_hcor **hcor)
1061fdabeddSStefano Babic {
10716297cfbSMateusz Zalega return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
1081fdabeddSStefano Babic }
1091fdabeddSStefano Babic
ehci_hcd_stop(int index)110676ae068SLucas Stach int ehci_hcd_stop(int index)
1111fdabeddSStefano Babic {
1121fdabeddSStefano Babic return omap_ehci_hcd_stop();
1131fdabeddSStefano Babic }
1141fdabeddSStefano Babic #endif
1151fdabeddSStefano Babic
1161fdabeddSStefano Babic
fpga_reset(int nassert)1171fdabeddSStefano Babic static inline void fpga_reset(int nassert)
1181fdabeddSStefano Babic {
1191fdabeddSStefano Babic gpio_set_value(FPGA_RESET, !nassert);
1201fdabeddSStefano Babic }
1211fdabeddSStefano Babic
fpga_pgm_fn(int nassert,int nflush,int cookie)1221fdabeddSStefano Babic int fpga_pgm_fn(int nassert, int nflush, int cookie)
1231fdabeddSStefano Babic {
1241fdabeddSStefano Babic debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
1251fdabeddSStefano Babic
1261fdabeddSStefano Babic gpio_set_value(FPGA_PROG, !nassert);
1271fdabeddSStefano Babic
1281fdabeddSStefano Babic return nassert;
1291fdabeddSStefano Babic }
1301fdabeddSStefano Babic
fpga_init_fn(int cookie)1311fdabeddSStefano Babic int fpga_init_fn(int cookie)
1321fdabeddSStefano Babic {
1331fdabeddSStefano Babic return !gpio_get_value(FPGA_INIT);
1341fdabeddSStefano Babic }
1351fdabeddSStefano Babic
fpga_done_fn(int cookie)1361fdabeddSStefano Babic int fpga_done_fn(int cookie)
1371fdabeddSStefano Babic {
1381fdabeddSStefano Babic return gpio_get_value(FPGA_DONE);
1391fdabeddSStefano Babic }
1401fdabeddSStefano Babic
fpga_pre_config_fn(int cookie)1411fdabeddSStefano Babic int fpga_pre_config_fn(int cookie)
1421fdabeddSStefano Babic {
1431fdabeddSStefano Babic debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
1441fdabeddSStefano Babic
1451fdabeddSStefano Babic /* Setting GPIOs for programming Mode */
1461fdabeddSStefano Babic gpio_request(FPGA_RESET, "FPGA_RESET");
1471fdabeddSStefano Babic gpio_direction_output(FPGA_RESET, 1);
1481fdabeddSStefano Babic gpio_request(FPGA_PROG, "FPGA_PROG");
1491fdabeddSStefano Babic gpio_direction_output(FPGA_PROG, 1);
1501fdabeddSStefano Babic gpio_request(FPGA_CCLK, "FPGA_CCLK");
1511fdabeddSStefano Babic gpio_direction_output(FPGA_CCLK, 1);
1521fdabeddSStefano Babic gpio_request(FPGA_DIN, "FPGA_DIN");
1531fdabeddSStefano Babic gpio_direction_output(FPGA_DIN, 0);
1541fdabeddSStefano Babic gpio_request(FPGA_INIT, "FPGA_INIT");
1551fdabeddSStefano Babic gpio_direction_input(FPGA_INIT);
1561fdabeddSStefano Babic gpio_request(FPGA_DONE, "FPGA_DONE");
1571fdabeddSStefano Babic gpio_direction_input(FPGA_DONE);
1581fdabeddSStefano Babic
1591fdabeddSStefano Babic /* Be sure that signal are deasserted */
1601fdabeddSStefano Babic gpio_set_value(FPGA_RESET, 1);
1611fdabeddSStefano Babic gpio_set_value(FPGA_PROG, 1);
1621fdabeddSStefano Babic
1631fdabeddSStefano Babic return 0;
1641fdabeddSStefano Babic }
1651fdabeddSStefano Babic
fpga_post_config_fn(int cookie)1661fdabeddSStefano Babic int fpga_post_config_fn(int cookie)
1671fdabeddSStefano Babic {
1681fdabeddSStefano Babic debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
1691fdabeddSStefano Babic
170472d5460SYork Sun fpga_reset(true);
1711fdabeddSStefano Babic udelay(100);
172472d5460SYork Sun fpga_reset(false);
1731fdabeddSStefano Babic
1741fdabeddSStefano Babic return 0;
1751fdabeddSStefano Babic }
1761fdabeddSStefano Babic
1771fdabeddSStefano Babic /* Write program to the FPGA */
fpga_wr_fn(int nassert_write,int flush,int cookie)1781fdabeddSStefano Babic int fpga_wr_fn(int nassert_write, int flush, int cookie)
1791fdabeddSStefano Babic {
1801fdabeddSStefano Babic gpio_set_value(FPGA_DIN, nassert_write);
1811fdabeddSStefano Babic
1821fdabeddSStefano Babic return nassert_write;
1831fdabeddSStefano Babic }
1841fdabeddSStefano Babic
fpga_clk_fn(int assert_clk,int flush,int cookie)1851fdabeddSStefano Babic int fpga_clk_fn(int assert_clk, int flush, int cookie)
1861fdabeddSStefano Babic {
1871fdabeddSStefano Babic gpio_set_value(FPGA_CCLK, assert_clk);
1881fdabeddSStefano Babic
1891fdabeddSStefano Babic return assert_clk;
1901fdabeddSStefano Babic }
1911fdabeddSStefano Babic
1922a6e3869SMichal Simek xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
1931fdabeddSStefano Babic fpga_pre_config_fn,
1941fdabeddSStefano Babic fpga_pgm_fn,
1951fdabeddSStefano Babic fpga_clk_fn,
1961fdabeddSStefano Babic fpga_init_fn,
1971fdabeddSStefano Babic fpga_done_fn,
1981fdabeddSStefano Babic fpga_wr_fn,
1991fdabeddSStefano Babic fpga_post_config_fn,
2001fdabeddSStefano Babic };
2011fdabeddSStefano Babic
202f8c1be98SMichal Simek xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
2031fdabeddSStefano Babic (void *)&mt_ventoux_fpga_fns, 0);
2041fdabeddSStefano Babic
2051fdabeddSStefano Babic /* Initialize the FPGA */
mt_ventoux_init_fpga(void)2061fdabeddSStefano Babic static void mt_ventoux_init_fpga(void)
2071fdabeddSStefano Babic {
2081fdabeddSStefano Babic fpga_pre_config_fn(0);
2091fdabeddSStefano Babic
2101fdabeddSStefano Babic /* Setting CS1 for FPGA access */
2111fdabeddSStefano Babic enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
2121fdabeddSStefano Babic FPGA_BASE_ADDR, GPMC_SIZE_128M);
2131fdabeddSStefano Babic
2141fdabeddSStefano Babic fpga_init();
2151fdabeddSStefano Babic fpga_add(fpga_xilinx, &fpga);
2161fdabeddSStefano Babic }
2171fdabeddSStefano Babic
2181fdabeddSStefano Babic /*
2191fdabeddSStefano Babic * Routine: board_init
2201fdabeddSStefano Babic * Description: Early hardware init.
2211fdabeddSStefano Babic */
board_init(void)2221fdabeddSStefano Babic int board_init(void)
2231fdabeddSStefano Babic {
2241fdabeddSStefano Babic gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
2251fdabeddSStefano Babic
2261fdabeddSStefano Babic /* boot param addr */
2271fdabeddSStefano Babic gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
2281fdabeddSStefano Babic
2291fdabeddSStefano Babic mt_ventoux_init_fpga();
2301fdabeddSStefano Babic
231ff530fc7SStefano Babic /* GPIO_140: speaker #mute */
232ff530fc7SStefano Babic MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
233ff530fc7SStefano Babic /* GPIO_141: Buzz Hi */
234ff530fc7SStefano Babic MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
235ff530fc7SStefano Babic
236ff530fc7SStefano Babic /* Turning off the buzzer */
237ff530fc7SStefano Babic gpio_request(BUZZER, "BUZZER_MUTE");
238ff530fc7SStefano Babic gpio_request(SPEAKER, "SPEAKER");
239ff530fc7SStefano Babic gpio_direction_output(BUZZER, 0);
240ff530fc7SStefano Babic gpio_direction_output(SPEAKER, 0);
241ff530fc7SStefano Babic
2429f670540SStefano Babic /* Activate USB power */
2439f670540SStefano Babic gpio_request(USB1_PWR, "USB1_PWR");
2449f670540SStefano Babic gpio_request(USB2_PWR, "USB2_PWR");
2459f670540SStefano Babic gpio_direction_output(USB1_PWR, 1);
2469f670540SStefano Babic gpio_direction_output(USB2_PWR, 1);
2479f670540SStefano Babic
2481fdabeddSStefano Babic return 0;
2491fdabeddSStefano Babic }
2501fdabeddSStefano Babic
25131f5b651SStefano Babic #ifndef CONFIG_SPL_BUILD
misc_init_r(void)2529d5fc239SStefano Babic int misc_init_r(void)
2539d5fc239SStefano Babic {
2549d5fc239SStefano Babic char *eth_addr;
25531f5b651SStefano Babic struct tam3517_module_info info;
25631f5b651SStefano Babic int ret;
2579d5fc239SStefano Babic
25831f5b651SStefano Babic TAM3517_READ_EEPROM(&info, ret);
259679f82c3SPaul Kocialkowski omap_die_id_display();
2609d5fc239SStefano Babic
26131f5b651SStefano Babic if (ret)
2629d5fc239SStefano Babic return 0;
26300caae6dSSimon Glass eth_addr = env_get("ethaddr");
26431f5b651SStefano Babic if (!eth_addr)
26531f5b651SStefano Babic TAM3517_READ_MAC_FROM_EEPROM(&info);
2669d5fc239SStefano Babic
26731f5b651SStefano Babic TAM3517_PRINT_SOM_INFO(&info);
2689d5fc239SStefano Babic return 0;
2699d5fc239SStefano Babic }
27031f5b651SStefano Babic #endif
2719d5fc239SStefano Babic
2721fdabeddSStefano Babic /*
2731fdabeddSStefano Babic * Routine: set_muxconf_regs
2741fdabeddSStefano Babic * Description: Setting up the configuration Mux registers specific to the
2751fdabeddSStefano Babic * hardware. Many pins need to be moved from protect to primary
2761fdabeddSStefano Babic * mode.
2771fdabeddSStefano Babic */
set_muxconf_regs(void)2781fdabeddSStefano Babic void set_muxconf_regs(void)
2791fdabeddSStefano Babic {
2801fdabeddSStefano Babic MUX_MT_VENTOUX();
2811fdabeddSStefano Babic }
2821fdabeddSStefano Babic
2831fdabeddSStefano Babic /*
2841fdabeddSStefano Babic * Initializes on-chip ethernet controllers.
2851fdabeddSStefano Babic * to override, implement board_eth_init()
2861fdabeddSStefano Babic */
board_eth_init(bd_t * bis)2871fdabeddSStefano Babic int board_eth_init(bd_t *bis)
2881fdabeddSStefano Babic {
2891fdabeddSStefano Babic davinci_emac_initialize();
2901fdabeddSStefano Babic return 0;
2911fdabeddSStefano Babic }
2921fdabeddSStefano Babic
2931d2c0506SMasahiro Yamada #if defined(CONFIG_MMC_OMAP_HS) && \
2941fdabeddSStefano Babic !defined(CONFIG_SPL_BUILD)
board_mmc_init(bd_t * bis)2951fdabeddSStefano Babic int board_mmc_init(bd_t *bis)
2961fdabeddSStefano Babic {
297e3913f56SNikita Kiryanov return omap_mmc_init(0, 0, 0, -1, -1);
2981fdabeddSStefano Babic }
2991fdabeddSStefano Babic #endif
30062986875SStefano Babic
30162986875SStefano Babic #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
board_video_init(void)30262986875SStefano Babic int board_video_init(void)
30362986875SStefano Babic {
30462986875SStefano Babic struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
30562986875SStefano Babic struct panel_config *panel = &lcd_cfg[0];
30662986875SStefano Babic char *s;
30762986875SStefano Babic u32 index = 0;
30862986875SStefano Babic
30962986875SStefano Babic void *fb;
31062986875SStefano Babic
31162986875SStefano Babic fb = (void *)0x88000000;
31262986875SStefano Babic
31300caae6dSSimon Glass s = env_get("panel");
31462986875SStefano Babic if (s) {
31562986875SStefano Babic index = simple_strtoul(s, NULL, 10);
31662986875SStefano Babic if (index < ARRAY_SIZE(lcd_cfg))
31762986875SStefano Babic panel = &lcd_cfg[index];
31862986875SStefano Babic else
31962986875SStefano Babic return 0;
32062986875SStefano Babic }
32162986875SStefano Babic
32262986875SStefano Babic panel->frame_buffer = fb;
32362986875SStefano Babic printf("Panel: %dx%d\n", panel_resolution[index].xres,
32462986875SStefano Babic panel_resolution[index].yres);
32562986875SStefano Babic panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
32662986875SStefano Babic (panel_resolution[index].xres - 1);
32762986875SStefano Babic
32862986875SStefano Babic gpio_request(LCD_PWR, "LCD Power");
32962986875SStefano Babic gpio_request(LCD_PON_PIN, "LCD Pon");
33062986875SStefano Babic gpio_direction_output(LCD_PWR, 0);
33162986875SStefano Babic gpio_direction_output(LCD_PON_PIN, 1);
33262986875SStefano Babic
33362986875SStefano Babic
33462986875SStefano Babic setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
33562986875SStefano Babic setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
33662986875SStefano Babic
33762986875SStefano Babic omap3_dss_panel_config(panel);
33862986875SStefano Babic omap3_dss_enable();
33962986875SStefano Babic
34062986875SStefano Babic return 0;
34162986875SStefano Babic }
34262986875SStefano Babic #endif
343