1 /* 2 * (C) Copyright 2015 Savoir-faire Linux Inc. 3 * 4 * Derived from MX51EVK code by 5 * Freescale Semiconductor, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/iomux-mx51.h> 15 #include <asm/errno.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/arch/clock.h> 19 #include <asm/imx-common/mx5_video.h> 20 #include <mmc.h> 21 #include <fsl_esdhc.h> 22 #include <mc13892.h> 23 24 #include "ts4800.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #ifdef CONFIG_FSL_ESDHC 29 struct fsl_esdhc_cfg esdhc_cfg[2] = { 30 {MMC_SDHC1_BASE_ADDR}, 31 {MMC_SDHC2_BASE_ADDR}, 32 }; 33 #endif 34 35 int dram_init(void) 36 { 37 /* dram_init must store complete ramsize in gd->ram_size */ 38 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 39 PHYS_SDRAM_1_SIZE); 40 return 0; 41 } 42 43 u32 get_board_rev(void) 44 { 45 u32 rev = get_cpu_rev(); 46 if (!gpio_get_value(IMX_GPIO_NR(1, 22))) 47 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; 48 return rev; 49 } 50 51 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) 52 53 static void setup_iomux_uart(void) 54 { 55 static const iomux_v3_cfg_t uart_pads[] = { 56 MX51_PAD_UART1_RXD__UART1_RXD, 57 MX51_PAD_UART1_TXD__UART1_TXD, 58 NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL), 59 NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL), 60 }; 61 62 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 63 } 64 65 #ifdef CONFIG_FSL_ESDHC 66 int board_mmc_getcd(struct mmc *mmc) 67 { 68 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 69 int ret; 70 71 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0, 72 NO_PAD_CTRL)); 73 gpio_direction_input(IMX_GPIO_NR(1, 0)); 74 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, 75 NO_PAD_CTRL)); 76 gpio_direction_input(IMX_GPIO_NR(1, 6)); 77 78 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 79 ret = !gpio_get_value(IMX_GPIO_NR(1, 0)); 80 else 81 ret = !gpio_get_value(IMX_GPIO_NR(1, 6)); 82 83 return ret; 84 } 85 86 int board_mmc_init(bd_t *bis) 87 { 88 static const iomux_v3_cfg_t sd1_pads[] = { 89 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | 90 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), 91 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | 92 PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), 93 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | 94 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), 95 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | 96 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), 97 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | 98 PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), 99 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | 100 PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), 101 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), 102 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), 103 }; 104 105 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 106 107 imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); 108 109 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 110 } 111 #endif 112 113 int board_early_init_f(void) 114 { 115 setup_iomux_uart(); 116 117 return 0; 118 } 119 120 int board_init(void) 121 { 122 /* address of boot parameters */ 123 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 124 125 return 0; 126 } 127 128 /* 129 * Do not overwrite the console 130 * Use always serial for U-Boot console 131 */ 132 int overwrite_console(void) 133 { 134 return 1; 135 } 136 137 int checkboard(void) 138 { 139 puts("Board: TS4800\n"); 140 141 return 0; 142 } 143 144 void hw_watchdog_reset(void) 145 { 146 struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE); 147 /* feed the watchdog for another 10s */ 148 writew(0x2, &wtd->feed); 149 } 150 151 void hw_watchdog_init(void) 152 { 153 return; 154 } 155