1 /* 2 * Copyright (C) 2017 NXP Semiconductors 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/crm_regs.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/mx7-pins.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/gpio.h> 13 #include <asm/imx-common/iomux-v3.h> 14 #include <asm/imx-common/mxc_i2c.h> 15 #include <asm/io.h> 16 #include <common.h> 17 #include <fsl_esdhc.h> 18 #include <i2c.h> 19 #include <miiphy.h> 20 #include <mmc.h> 21 #include <netdev.h> 22 #include <usb.h> 23 #include <power/pmic.h> 24 #include <power/pfuze3000_pmic.h> 25 #include "../../freescale/common/pfuze.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 30 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 31 32 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 33 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 34 35 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 36 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 37 38 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 39 40 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 41 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) 42 43 #ifdef CONFIG_SYS_I2C_MXC 44 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 45 /* I2C4 for PMIC */ 46 static struct i2c_pads_info i2c_pad_info4 = { 47 .scl = { 48 .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC, 49 .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC, 50 .gp = IMX_GPIO_NR(6, 16), 51 }, 52 .sda = { 53 .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC, 54 .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC, 55 .gp = IMX_GPIO_NR(6, 17), 56 }, 57 }; 58 #endif 59 60 int dram_init(void) 61 { 62 gd->ram_size = PHYS_SDRAM_SIZE; 63 64 return 0; 65 } 66 67 #ifdef CONFIG_POWER 68 #define I2C_PMIC 3 69 int power_init_board(void) 70 { 71 struct pmic *p; 72 int ret; 73 unsigned int reg, rev_id; 74 75 ret = power_pfuze3000_init(I2C_PMIC); 76 if (ret) 77 return ret; 78 79 p = pmic_get("PFUZE3000"); 80 ret = pmic_probe(p); 81 if (ret) 82 return ret; 83 84 pmic_reg_read(p, PFUZE3000_DEVICEID, ®); 85 pmic_reg_read(p, PFUZE3000_REVID, &rev_id); 86 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 87 88 /* disable Low Power Mode during standby mode */ 89 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®); 90 reg |= 0x1; 91 pmic_reg_write(p, PFUZE3000_LDOGCTL, reg); 92 93 /* SW1A/1B mode set to APS/APS */ 94 reg = 0x8; 95 pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); 96 pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); 97 98 /* SW1A/1B standby voltage set to 1.025V */ 99 reg = 0xd; 100 pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); 101 pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); 102 103 /* decrease SW1B normal voltage to 0.975V */ 104 pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); 105 reg &= ~0x1f; 106 reg |= PFUZE3000_SW1AB_SETP(975); 107 pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg); 108 109 return 0; 110 } 111 #endif 112 113 static iomux_v3_cfg_t const wdog_pads[] = { 114 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 115 }; 116 117 static iomux_v3_cfg_t const uart5_pads[] = { 118 MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 119 MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 120 }; 121 122 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 123 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 128 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 129 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 }; 135 136 #ifdef CONFIG_FEC_MXC 137 static iomux_v3_cfg_t const fec1_pads[] = { 138 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 139 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 140 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 141 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 142 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 143 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 144 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 145 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 146 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 147 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 148 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 149 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 150 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 151 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 152 MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 153 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 154 }; 155 156 #define FEC1_RST_GPIO IMX_GPIO_NR(6, 11) 157 158 static void setup_iomux_fec(void) 159 { 160 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 161 162 gpio_direction_output(FEC1_RST_GPIO, 0); 163 udelay(500); 164 gpio_set_value(FEC1_RST_GPIO, 1); 165 } 166 167 int board_eth_init(bd_t *bis) 168 { 169 setup_iomux_fec(); 170 171 return fecmxc_initialize_multi(bis, 0, 172 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 173 } 174 175 static int setup_fec(void) 176 { 177 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 178 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 179 180 /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */ 181 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 182 (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | 183 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); 184 185 return set_clk_enet(ENET_125MHz); 186 } 187 188 int board_phy_config(struct phy_device *phydev) 189 { 190 unsigned short val; 191 192 /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ 193 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 194 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 195 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 196 197 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 198 val &= 0xffe7; 199 val |= 0x18; 200 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 201 202 /* introduce tx clock delay */ 203 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 204 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 205 val |= 0x0100; 206 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 207 208 if (phydev->drv->config) 209 phydev->drv->config(phydev); 210 211 return 0; 212 } 213 #endif 214 215 static void setup_iomux_uart(void) 216 { 217 imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); 218 } 219 220 static struct fsl_esdhc_cfg usdhc_cfg[1] = { 221 {USDHC3_BASE_ADDR}, 222 }; 223 224 int board_mmc_getcd(struct mmc *mmc) 225 { 226 /* Assume uSDHC3 emmc is always present */ 227 return 1; 228 } 229 230 int board_mmc_init(bd_t *bis) 231 { 232 imx_iomux_v3_setup_multiple_pads( 233 usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); 234 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 235 236 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 237 } 238 239 int board_early_init_f(void) 240 { 241 setup_iomux_uart(); 242 243 #ifdef CONFIG_SYS_I2C_MXC 244 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); 245 #endif 246 247 return 0; 248 } 249 250 int board_init(void) 251 { 252 /* address of boot parameters */ 253 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 254 255 #ifdef CONFIG_FEC_MXC 256 setup_fec(); 257 #endif 258 259 return 0; 260 } 261 262 int board_late_init(void) 263 { 264 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 265 266 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 267 268 set_wdog_reset(wdog); 269 270 /* 271 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 272 * since we use PMIC_PWRON to reset the board. 273 */ 274 clrsetbits_le16(&wdog->wcr, 0, 0x10); 275 276 return 0; 277 } 278 279 int checkboard(void) 280 { 281 puts("Board: i.MX7D PICOSOM\n"); 282 283 return 0; 284 } 285 286 int board_usb_phy_mode(int port) 287 { 288 return USB_INIT_DEVICE; 289 } 290